GB2291233A - Semiconductor memory device with reduced data bus line load - Google Patents

Semiconductor memory device with reduced data bus line load Download PDF

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Publication number
GB2291233A
GB2291233A GB9513937A GB9513937A GB2291233A GB 2291233 A GB2291233 A GB 2291233A GB 9513937 A GB9513937 A GB 9513937A GB 9513937 A GB9513937 A GB 9513937A GB 2291233 A GB2291233 A GB 2291233A
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United Kingdom
Prior art keywords
data bus
bus line
data
equalizing
line control
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GB9513937A
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GB9513937D0 (en
GB2291233B (en
Inventor
Geoun Tae Kwon
Yong Chul Cho
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Publication of GB2291233B publication Critical patent/GB2291233B/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

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  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

A semiconductor memory device having a plurality of memory blocks 2001 - 2064 for storing data, and a plurality of sense amplifiers 2101- 2264 for sensing the data stored in the plurality of memory blocks. The semiconductor memory device comprises data bus lines for transferring the data sensed by the plurality of sense amplifiers. The data bus lines are divided into first and second parts. The semiconductor memory device further comprises a data bus line load reduction circuit 2400 for selecting one of the divided first and second data bus line parts in response to first and second data bus line control signals. The selected data bus line part inputs the data from one of the plurality of memory blocks selected in response to a memory block address. The other data bus line part, not selected, has a minimized load. The first and second data bus line control signals are produced in response to a most significant bit of the memory block address. The load reduction circuit 2400 includes CMOS transistors (Fig. 2B). <IMAGE>

Description

SEMICONDUCTOR MEMORY DEVICE WITH REDUCED DATA BUS LINE LOAD The present invention relates to a semiconductor memory device which is capable of reducing a data bus line load to enhance a data transfer speed.
Generally, data bus lines are included for data transfer in semiconductor memory devices such as a dynamic random access memory, a static random access memory, a read only memory and the like. The data bus lines have loads such as a routing capacitance, a fringing capacitance, a sheet resistance and the like, resulting in a delay in the data transfer. The routing capacitance is commonly called an intrinsic capacitance and produced between the data bus lines and a semiconductor substrate. The fringing capacitance is commonly called a coupling capacitance and produced between adjacent ones of the data bus lines.
A conventional 16M (mega) static random access memory (referred to hereinafter as SRAM) will hereinafter be mentioned with reference to Fig. 1 of the accompanying drawings.
Referring to Fig. 1, there is shown, in block form, the conventional 16M SRAM. As shown in this drawing, the conventional 16M SRAM comprises 64 memory blocks 1001-1064, each of which has a memory capacity of 256K bits. That is, each of the 64 memory blocks 1001-1064 includes 128 memory cells in the horizontal direction and 2048 memory cells in the vertical direction. Generally, as the semiconductor memory device becomes larger in scale, the bit line loads such as the sheet resistance, the routing capacitance, the fringing capacitance and the coupling capacitance are increased. The increased bit line loads have a bad effect on the data input and output, resulting in a limitation in the number of memory cells in one memory block. For this reason, the semiconductor memory device comprises a plurality of memory blocks.Here, the coupling capacitance signifies a capacitance produced at a contact point between the bit line and the memory cell.
The conventional 16M SRAM further comprises 64 firststage sense amplifier arrays 1101-1164, each of which senses eight output bits from a corresponding one of the memory blocks 1001-1064. Here, the number of the output bits from each of the memory blocks 1001-1064 is 8 as an example, which may be different according to the type of the semiconductor memory device.
The conventional 16M SRAM further comprises 64 secondstage sense amplifiers 1201-1264 for sensing output bits from the first-stage sense amplifier arrays 1101-1164 in the unit of 8 bits by weight, respectively. Output bits from the second-stage sense amplifiers 1201-1264 are placed on eight data bus lines in the unit of 8 bits by weight. The conventional 16M SRAM further comprises eight third-stage sense amplifiers 1301-1308 for sensing bits on the corresponding data bus lines, respectively. The data bus lines have such long lengths as to input the cell data from all the memory blocks 1001-1064.
As a result, as the semiconductor memory device becomes larger in scale, the data bus line is ir.creased in length, resulting in an increase in the load. The increased load of the data bus line causes a delay in the data transfer.
Further, in order to drive the data bus line with the increased load, the sense amplifier must be increased in size.
The increased size of the sense amplifier reduces a data sensing speed thereof and increases a lay-out area thereof.
In this connection, a data bus line load reduction circuit is required to reduce the data bus line load, so as to increase the data transfer speed and reduce the lay-out area of the sense amplifier.
There will be described below, by way of an example, a semiconductor memory device which is capable of reducing a data bus line load thereby to increase the data transfer speed and to reduce the lay-out area of a sense amplifier.
In a particular arrangement to be described below as an example, there is a semiconductor memory device having a plurality of memory blocks for storing data, and a plurality of sense amplification means for sensing the data stored in the plurality of memory blocks, including data bus lines for transferring the data sensed by the plurality of sense amplification means, the data bus lines being divided into first and second parts, and data bus line load reduction means for selecting one of the divided first and second data bus line parts in response to first and second data bus line control signals, so that the selected data bus line part can input the data from one of the plurality of memory blocks selected in response to a memory block address,and the other data bus line part, not selected, can have a minimized load, the first and second data bus line control signals being produced in response to a most significant bit of the memory block address.
An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 2A is a block diagram of a 16M SRAM, Fig. 2B is a detailed circuit diagram of a data bus line load reduction circuit in Fig. 2A, and Fig. 3 is a timing diagram illustrating an operation of the 16M SRAM in Fig. 2A.
Now, a 16M SRAM with a data bus line load reduction circuit in accordance with an embodiment of the present invention will be described in detail with reference to Figs.
2A and 2B.
Referring to Fig. 2A, there is shown a block diagram of the 16M SRAM in accordance with the embodiment of the present invention. As shown in this drawing, the 16M SRAM comprises 64 memory blocks 2001-2064, each of which has a memory capacity of 256K bits. That is, each of the 64 memory blocks 2001-2064 includes 128 memory cells in the horizontal direction and 2048 memory cells in the vertical direction.
The 16M SRAM further comprises 64 first-stage sense amplifier arrays 2101-2164, each of which senses eight output bits from a corresponding one of the memory blocks 2001-2064.
Here, the number of the output bits from each of the memory blocks 2001-2064 is 8 as an example, which may be different according to the type of the semiconductor memory device.
The 16M SEAM further comprises 64 second-stage sense amplifiers 2201-2264 for sensing output bits from the firststage sense amplifier arrays 2101-2164 in the unit of 8 bits by weight, respectively. Output bits from the second-stage sense amplifiers 2201-2264 are placed on eight data bus lines in the unit of 8 bits by weight.
The data bus lines are divided into two parts. Namely, the first data bus line part corresponds to the first to 32nd memory blocks and the second data bus line part corresponds to the 33rd to 64th memory blocks. The data bus line load reduction circuit 2400 is connected between the first and second data bus line parts to select one thereof.
The 16M SRAM further comprises eight third-stage sense amplifiers 2301-2308 for sensing bits on the data bus line part selected by the data bus line load reduction circuit 2400, respectively.
Referring to Fig. 2B, there is shown a detailed circuit diagram of the data bus line load reduction circuit 2400 in Fig. 2A. In this drawing, the reference numerals SO1L to SOBL and ISOlL to /SO8L designate the data bus lines of the first part, respectively, and the reference numerals SOlR to SOBER and /SOUR to /SO8R designate the data bus lines of the second part, respectively. In the first data bus line part, the data bus line SOL and the data bus line /SOL are complementary to each other to transfer complementary bits. Similarly, in the second data bus line part, the data bus line SOR and the data bus line /SOR are complementary to each other to transfer complementary bits.
As shown in Fig. 2B, the data bus line load reduction circuit 2400 comprises a plurality of CMOS transistors 25112586, each of which is formed by coupling a drain and a source of a p-type metal oxide semiconductor (referred to hereinafter as PMOS) transistor with a drain and a source of an n-type metal oxide semiconductor (referred to hereinafter as NMOS) transistor. Each pair of the complementary data bus lines corresponds to six of the CMOS transistors 2511-2586. In each of the CMOS transistors 2511, 2513, 2521, 2523 ...., 2581 and 2583, a first data bus line control signal PSOLZL is applied to a gate of the PMOS transistor and a first data bus line control bar signal /PSOLZL is applied to a gate of the NMOS transistor.The drains of the PMOS and NMOS transistors are connected in common to a corresponding one of the data bus lines SOlL-SO8L and /SO1L-/SO8L of the first part. The sources of the PMOS and NMOS transistors are connected in common to a corresponding one of the third-stage sense amplifiers 2301-2308. Similarly in each of the CMOS transistors 2514, 2516, 2524, 2526, ...., 2584 and 2586, a second data bus line control signal PSOLZR is applied to a gate of the PMOS transistor and a second data bus line control bar signal /PSOLZR is applied to a gate of the NMOS transistor. The drains of the PMOS and NMOS transistors are connected in common to a corresponding one of the data bus lines SO1R-SO8R and /SO1R-/S08R of the second part.The sources of the PMOS and NMOS transistors are connected in common to a corresponding one of the third-stage sense amplifiers 2301-2308. Each of the third-stage sense amplifiers 2301-2308 senses a corresponding one of output bits SO1-SO8 and /SO1-/S08 from the CMOS transistors 2511-2586 in the data bus line load reduction circuit 2400.
The CMOS transistors 2512, 2522, ...., 2582 are adapted to equalize the complementary data bus lines of the first part, respectively. Namely, in each of the CMOS transistors 2512, 2522, ...., 2582, the drains of the PMOS and NMOS transistors are connected in common to a corresponding one of the data bus lines SOlL-SOBL of the first part. The sources of the PMOS and NMOS transistors are connected in common to a corresponding one of the data bus lines /SOlL-/SOBL of the first part. The first data bus line control signal PSOLZL is applied to the gate of the NMOS transistor and the first data bus line control bar signal /PSOLZL is applied to the gate of the PMOS transistor.
Similarly, the CMOS transistors 2515, 2525 ...., 2585 are adapted to equalize the complementary data bus lines of the second part, respectively. Namely, in each of the CMOS transistors 2515, 2525 ...., 2585, the drains of the PMOS and NMOS transistors are connected in common to a corresponding one of the data bus lines SO1R-S08R of the second part. The sources of the PMOS and NMOS transistors are connected in common to a corresponding one of the data bus lines /SOlR /S08R of the second part. The second data bus line control signal PSOLZR is applied to the gate of the NMOS transistor and the second data bus line control bar signal /PSOLZR is applied to the gate of the PMOS transistor.
The first and second data bus line control signals PSOLZL and PSOLZR are produced by properly combining a most significant bit of a memory block address, an equalizing signal and a second-stage sense amplifier enable signal, as will be mentioned in detail later in conjunction with the operation of the data bus line load reduction circuit 2400.
Noticeably, each of the equalizing CMOS transistors 2512, 2522, ...., 2582, 2515, 2525, ...., 2585 equalizes the corresponding data bus line when it is not selected.
Therefore, the data input and output can be stably performed.
The operation of the data bus line load reduction circuit 2400 will hereinafter be described in detail with reference to Fig. 3.
Fig. 3 is a timing diagram illustrating input and output waveforms in the data bus line load reduction circuit 2400.
As shown in this drawing, the first data bus line control signal PSOLZL is "1" in logic when the most significant bit of the memory block address is "1" in logic. Also, the first data bus line control signal PSOLZL remains at its logic "1" state from a falling edge of the equalizing signal till a rising edge of the second-stage sense amplifier enable signal under the condition that the most significant bit of the memory block address is "0" in logic.
The second data bus line control signal PSOLZR is "1" in logic when the most significant bit of the memory block address is "0" in logic. Also, the second data bus line control signal PSOLZR remains at its logic "1" state from the falling edge of the equalizing signal till the rising edge of the second-stage sense amplifier enable signal under the condition that the most significant bit of the memory block address is "1" in logic.
When the first data bus line control signal PSOLZL is "0" in logic, the data bus line load reduction circuit 2400 selects the first part data bus lines SOlL-SOBL and /SOlL /SOBL. On the contrary, when the second data bus line control signal PSOLZR is "0" in logic, the data bus line load reduction circuit 2400 selects the second part data bus lines SOlR-S08R and /SOlR-/SO8R. That is, the data bus line load reduction circuit 2400 selects only an enabled one of the divided data bus line parts. The data bus line part, not selected, is equalized, resulting in production of no load therein.As a result, the entire data bus line load is reduced to half (50%). For example, the jth complementary bits SOj and /SOj are obtained by selectively combining the first and second part data bus line bits SOjL, /SOjL, SOjR and /SOjR in response to the first and second data bus line control signals PSOLZL and PSOLZR.
Alternatively, the most significant bit of the memory block address may be used directly as the first and second data bus line control signals PSOLZL and PSOLZR.
Also, the entire data bus line load may be reduced still more by equalizing all the data bus lines from the falling edge of the equalizing signal till the rising edge of the second-stage sense amplifier enable signal.
Further, the data bus lines may be divided into at least three parts. In this case, the data bus line control signals must properly be readjusted to select only an enabled one of the divided data bus line parts.
As apparent from the above description, according to the present invention, only a desired one of the divided data bus line parts is selected, resulting in production of no load in the data bus line part, not selected. Therefore, the entire data bus line load can significantly be reduced. In result, the present invention has the effect of increasing the data transfer speed and reducing the lay-out area of the sense amplifier.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the invention as defined in the accompanying drawings.

Claims (6)

1. A semiconductor memory device having a plurality of memory blocks for storing data, and a plurality of sense amplification means for sensing the data stored in the plurality of memory blocks, including data bus lines for transferring the data sensed by the plurality of sense amplification means, the data bus lines being divided into first and second part, and data bus line load reduction means for selecting one of the divided first and second data bus line parts in response to first and second data bus line control signals so that the selected data bus line part can input the data from one of the plurality of memory blocks selected in response to a memory block address and the other data bus line part, not selected, can have a minimized load, the first and second data bus line control signals being produced in response to a most significant bit of the memory block address.
2. A semiconductor memory device as claimed in Claim 1, wherein the data bus lines are divided into the first and second parts on the basis of the middle of the plurality of memory blocks; and wherein the first and second data bus line control signals are the most significant bit of the memory block address.
3. A semiconductor memory device as claimed in Claim 2, wherein the first and second data bus line control signals remain in their active states from a falling edge of an equalizing signal till a rising edge of a sense amplification enable signal to equalize both the first and second data bus line parts.
4. A semiconductor memory device as claimed in Claim 2, wherein the data bus line load reduction means includes a plurality of first switching means, each of the plurality of first switching means selecting a corresponding one of the data bus lines of the first data bus line part when the first data bus line control signal remains in its inactive state, a plurality of second switching means, each of the plurality of second switching means selecting a corresponding one of the data bus lines of the second data bus line part when the second data bus line control signal remains in its inactive state, a plurality of first equalizing means, each of the plurality of first equalizing means equalizing a corresponding one of the data bus lines of the first data bus line part when the first data bus line control signal remains in its active state, and a plurality of second equalizing means, each of the plurality of second equalizing means equalizing a corresponding one of the data bus lines of the second data bus line part when the second data bus line control signal remains in its active state.
5. A semiconductor memory device as claimed in Claim 3, wherein the data bus line load reduction means includes a plurality of first switching means, each of the plurality of first switching means selecting a corresponding one of the data bus lines of the first stat bus line part when the first data bus line control signal remains in its inactive state, a plurality of second switching means, each of the plurality of second switching means selecting a corresponding one of the data bus lines of the second data bus line part when the second data bus line control signal remains in its inactive state, a plurality of first equalizing means, each of the plurality of first equalizing means equalizing a corresponding one of the data bus lines of the first data bus line part when the first data bus line control signal remains in its active state, and a plurality of second equalizing means, each of the plurality of second equalizing means equalizing a corresponding one of the data bus lines of the second data bus line part when the second data bus line control signal remains in its active state.
6. A semiconductor memory device as claimed in Claim 1 substantially as described herein with reference to Figs.
2A, 2B and 3 of the accompanying drawings.
GB9513937A 1994-07-07 1995-07-07 Semiconductor memory device with reduced data bus line load Expired - Fee Related GB2291233B (en)

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KR1019940016356A KR970003337B1 (en) 1994-07-07 1994-07-07 A semiconductor memory device including an apparatus for reducing load of data bus line

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GB2291233A true GB2291233A (en) 1996-01-17
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2308702A (en) * 1995-12-29 1997-07-02 Hyundai Electronics Ind Semiconductor memory device having bit line sense amplifier array
GB2349968A (en) * 1995-12-29 2000-11-15 Hyundai Electronics Ind A semiconductor memory device with increased bandwidth

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474553B1 (en) * 1997-05-10 2005-06-27 주식회사 하이닉스반도체 Semiconductor memory device with dual data bus line sense amplifiers
CN100490014C (en) * 2002-04-27 2009-05-20 力旺电子股份有限公司 Memory and method for reading the memory
KR100654765B1 (en) 2005-09-26 2006-12-08 삼성전자주식회사 Head driving device, inkjet printer comprising the same and data processing method thereof
JP6539509B2 (en) * 2015-06-15 2019-07-03 オリンパス株式会社 Data transfer apparatus and data transfer method

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Publication number Priority date Publication date Assignee Title
EP0166642A2 (en) * 1984-05-30 1986-01-02 Fujitsu Limited Block-divided semiconductor memory device having divided bit lines
US5016224A (en) * 1988-09-12 1991-05-14 Kabushiki Kaisha Toshiba Semiconductor memory device
GB2246001A (en) * 1990-04-11 1992-01-15 Digital Equipment Corp Cache memory having sub-arrays of cells

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Publication number Priority date Publication date Assignee Title
US5126973A (en) * 1990-02-14 1992-06-30 Texas Instruments Incorporated Redundancy scheme for eliminating defects in a memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0166642A2 (en) * 1984-05-30 1986-01-02 Fujitsu Limited Block-divided semiconductor memory device having divided bit lines
US5016224A (en) * 1988-09-12 1991-05-14 Kabushiki Kaisha Toshiba Semiconductor memory device
GB2246001A (en) * 1990-04-11 1992-01-15 Digital Equipment Corp Cache memory having sub-arrays of cells

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2308702A (en) * 1995-12-29 1997-07-02 Hyundai Electronics Ind Semiconductor memory device having bit line sense amplifier array
GB2308702B (en) * 1995-12-29 2000-10-18 Hyundai Electronics Ind A semiconductor memory device with increased bandwidth
GB2349968A (en) * 1995-12-29 2000-11-15 Hyundai Electronics Ind A semiconductor memory device with increased bandwidth
GB2349968B (en) * 1995-12-29 2001-01-17 Hyundai Electronics Ind A semiconductor memory device with increased bandwidth

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GB9513937D0 (en) 1995-09-06
GB2291233B (en) 1998-08-12
KR970003337B1 (en) 1997-03-17
CN1054228C (en) 2000-07-05
CN1125887A (en) 1996-07-03

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