GB2289385A

GB2289385A - MOSFET driver circuit including dv/dt protection

Info

Publication number: GB2289385A
Application number: GB9509337A
Authority: GB
Inventors: Matti Havukainen
Original assignee: Nokia Telecommunications Oy
Current assignee: Nokia Oyj
Priority date: 1994-05-10
Filing date: 1995-05-09
Publication date: 1995-11-15
Anticipated expiration: 2015-05-09
Also published as: FI942163A; FI96552B; FI942163A0; SE515257C2; DE19517831A1; GB9509337D0; FI96552C; SE9501729L; SE9501729D0; GB2289385B

Description

2289385 1 Driver circuit for an enhancement-mode fet switch This invention

relates to a driver circuit for an enhancement-mode fet switch, preferably in a converter. More accurately, the invention relates to a driver circuit for an enhancement-mode fet switch, preferably in a converter, the circuit comprising means for storing a charge at a gate connection of the enhancement-mode fet switch during a first narrow control pulse and means for discharging said charge in response to a second narrow control pulse.

From converters (such as secondary choppers or synchronous rectifiers), for instance, a driver circuit for driving an enhancement -mode fet switch is previously known, in which circuit a gate connection of the enhancement-mode fet switch is controlled by narrow control pulses. In said known solution, a charge passes during a first control pulse to the gate connection and remains in "memory" at the gate connection after the termination of the effect of the control pulse. Said charge keeps the enhancement-mode fet switch conducting. During a second narrow control pulse, the charge of the gate connection of the enhancement-mode fet switch is discharged by the discharge means of the driver circuit.

A drawback of the above-mentioned known solution is the risk of the enhancement -mode fet switch being damaged at the moment the operating voltage is switched on. In a converter for instance, drain voltage of the enhancement -mode fet switch may change at the switching-on moment of the operating voltage stepwise very quickly, even by 10 V/p. When the rate of rise and the magnitude of the drain voltage exceed a predetermined level, a leakage current is generated due to the drain-gate capacitance of the enhancement-mode fet switch, which current passes to the gate connection of 2 the enhancement-mode fet switch. Said leakage current passing to the gate connection makes the enhancementmode fet switch conducting, due to which it may be damaged, because the duration of a pulse generated by the switching-on of the operating voltage is considerably longer than the duration of a normal control pulse of the enhancement-mode fet switch, whereby the maximum operating values of the enhancement-mode fet switch are exceeded. Especially the current exceeds the allowed current.

The object of this invention is to eliminate the above drawback and to provide a driver circuit by means of which the enhancement-mode fet switch can be prevented from being damaged at the moment the operating voltage is switched on. This object is achieved by means of a driver circuit according to the invention, which circuit is characterized in that the discharge means are arranged to form a discharge path from the gate connection of the enhancement-mode fet switch, after a predetermined time has passed since the last control pulse, whereby a leakage current, caused by an abrupt rise of drain voltage of the enhancement -mode fet switch and passing to the gate connection, may discharge via said discharge path.

The invention is based on the idea that an enhancement-mode fet switch can be prevented from being damaged at the moment the operating voltage is switched on by arranging an active pull-down for the gate connection of the enhancement-mode fet switch in the rest state of the driver circuit. This is provided according to the invention by arranging the discharge means in such a way that, after a predetermined time has passed since the last control pulse, the discharge means open a discharge path from the gate connection of the enhancement-mode fet switch, upon which the discharge A 3 means keep said discharge path open until the arrival of next control pulse. The discharge path is thus open at the switching-on moment of the operating voltage. The most significant advantage of the driver circuit according to the invention is that the enhancement-mode fet switch can be prevented from being damaged by means of this simple circuit at a fair price.

When a depletion-mode fet switch is used as discharge means of the gate connection of an enhancement-mode fet switch, the gate connection of the depletion-mode fet switch being used as a memory of a charge supplied thereto in connection with the second control pulse, the discharge means of the enhancement-mode fet switch can be implemented by means of a single component, i.e. a depletion-mode fet switch.

Preferred embodiments of the driver circuit according to the Invention appear f rom the attached dependent claims 2 to 5. The invention will be described in the following by way of example with reference to the attached figures, Figure 1 illustrating a first preferred embodiment of a driver circuit according to the invention, Figure 2 illustrating pulses occurring in the driver circuit of Figure 1, and Figure 3 illustrating properties of fet switches of Figure 1.

Figure 1 illustrates a first preferred embodiment of a driver circuit according to the invention. The driver circuit of Figure 1 can preferably be used in a converter, for instance. To illustrate this, a transformer T2 is drawn in Figure 1, one terminal of a primary winding of the transformer being connected to a drain connection D of a mosfet Q1. The load to be connected to the terminals of the secondary windings of the transformer T2 is not illustrated in Figure 1.

4 An enhancement-mode fet switch Q1, which preferably is an n-channel enhancement-mode mosfet transistor, is in Figure 1 driven by a bipolar control signal Ubip constituted by first P1 and second P2 control pulses. The control pulses P1 and P2 are narrow pulses, e.g. 200 ns long, which may have an amplitude of 10 V, for instance. By means of a transformer T1, the pulses are transferred in an isolated manner from a primary winding of the transformer to a secondary winding. In the case shown in Figure 1, the transformer Tl comprises two secondary windings. In case of a converter, the bipolar signal Ubip is preferably derived from a PWM (Pulse Width Modulation) control signal produced by a control circuit of the converter in a manner known per se.

During the first (positive) control pulse P1, a depletion-mode fet switch Q2, which preferably is an n-channel depletion-mode mosfet transistor, receives a negative drive for its gate connection G via the lower half of the transformer T1, a diode D3 and a resistor R4. The depletion-mode fet switch Q2 is then in a reverse blocking state, i.e. non-conducting. The charge remains in memory at the gate connection of the mosfet Q2 also after the termination of the control pulse P1, because a charge can discharge only via a leakage current when a pnp transistor Q3 is in a reverse blocking state.

During the first (positive) control pulse Pl, the mosfet Q1 receives a positive drive for its gate connection G via the upper half of the transformer T1, a diode D1 and a resistor R1. This charge, which keeps the mosfet Q1 conducting, remains in memory at the gate connection G also after the termination of the control pulse Pl, because a charge can discharge only via leakage currents when the mosfet Q2 is in a nonconducting state.

0 k A Q During the second (negative) control pulse P2, the pnp transistor Q3 is conducting, because it is driven via a diode D2 and resistors R2 and R3. Then the transistor Q3 discharges the charge from the memory at the gate connection G of the mosfet Q2, which makes the mosfet Q2 conducting. Then the mosfet Q2 in turn discharges the charge from the memory at the gate connection G of the mosfet Q1, due to which the mosf et Q1 passes into a non-conducting state. Accordingly, a U, signal shown in Figure 2 is generated to the gate connection of the mosfet Q1 of Figure 1.

According to the invention, the enhancementmode fet switch Q1 of Figure 1 is prevented from being damaged at the switching-on moment of the operating voltage by selecting such a type of means for discharging a charge from the gate of the mosfet Q1, i.e. the mosf et Q2 (an n-channel depletion-mode mosfet, type Siemens BSP 149, for instance), that a discharge path opens from the gate connection thereof after some time has passed since the termination of the influence of the control pulses P1 and P2. This means that, upon the termination of the influence of the control pulses P1 and P2 affecting the driver circuit of Figure 1, the charge possibly remained in memory at the gate connection G of the mosf et Q2 discharges. This charge discharges thanks to leakage currents in such a way that the mosfet Q2 becomes conducting. When the mosfet Q2 becomes conducting, it forms a discharge path for the gate connection of the mosfet Q1, whereby the charge stored at the gate connection G of the mosfet Q1 also discharges and the mosfet Q1 (n-channel enhancement-mode mosfet, type International Rectifier IRF 630, for instance) becomes non-conducting.

In case of a converter, in which the first P1 and the second control pulse P2 are derived from a PWM 6 signal produced by the control circuit of the converter, the second control pulse P2 is the last control pulse influencing the driver circuit. This is due to the fact that the PWM signal of the control circuit passes to logic 0-level when the operating voltage of the circuit disappears, whereby the control pulse P2 is supplied to the driver circuit due to said change.

When the operating voltage is connected to the driver circuit by a switch S1, the drain voltage of the mosfet Q1 increases stepwise (from logic 0level to logic 1-level). Because the mosfet Q2 is still in a conducting state, it forms a discharge path for the gate connection of the mosfet Q1, in which case the control coming through the drain-gate capacitance of the mosfet Q1 does not make the mosfet Q1 conducting (which could damage it), not even as a consequence of an abrupt rise of the drain voltage. Accordingly, an active pull-down is secured for the gate connection of the mosfet Q1 in the rest state of the driver circuit, i.e. when the first P1 and the second P2 control pulse have not been influencing the driver circuit for some time.

Figure 2 illustrates pulses occurring in the driver circuit of Figure 1. Ubi. indicates a bipolar signal to be transferred across the transformer Tl of Figure 1, by which signal the mosfet Q1 is driven. Said signal is constituted by positive first control pulses P1 and negative second control pulses P2. The control pulses P1 and P2 are narrow pulses, e.g. 200 ns long, which have an amplitude of 10 V, for instance.

Figure 2 illustrates a pulse U, generated at the gate connection of the mosfet Q1 by means of the driver circuit. Timing of the first P1 and the second P2 control pulses in relation to the signal U, is illustrated by broken lines in Figure 2. In case of a converter, in which the bipolar signal U,,,p is derived from 7 a PWM signal of the control circuit, the pulse UG to be supplied to the gate connection G of the mosfet Q1 corresponds to said PWM signal.

Figure 3 illustrates properties of the fet switches of Figure 1. In Figure 3, the horizontal axis represents a voltage V. between gate-source connections of the fet switches. The vertical axis again represents a current I,, passing through drain-source connections of the fet switches.

From Figure 3 appears that the depletion-mode fet switch Q2 of Figure 1 is of a type which is fully conducting already when its gate voltage is 0 volts. Correspondingly, from Figure 3 appears that the enhancement-mode fet switch Q1 of Figure 1 does not become conducting until at that stage when its gate voltage properly exceeds 0 volts. Typical trigger voltage of the enhancement-mode fet switch Q1 (making the switch conducting) is about 2 volts.

The above description and the figures associ ated therewith are only intended to illustrate the pres ent invention. Different variations and modifications of the invention will be obvious for persons skilled in the art, without any deviations from the scope of pro tection of the invention set f orth in the attached claims.

8

Claims

Claims:

1. A driver circuit of an enhancement-mode fet switch. preferably in a converter, the circuit comprising means for storing a charge at a gate connection of the enhancement-mode fet switch during a first narrow control pulse and means for discharging said charge in response to a second narrow control pulse.,.

c h a r a c t e r i z e d in that the discharge means are arranged to form a discharge path from the gate connection of the enhancement-mode fet switch, after a predetermined time has passed since the last control pulse, whereby a leakage current, caused by an abrupt rise of drain voltage of the enhancement-mode fet switch and passing to the gate connection, may discharge via said discharge path.

2. A driver circuit according to claim 1, c h a r a c t e r i z e d in that the discharge means comprise a depletion-mode fet switch, the drain connection of which is connected to the gate connec tion of the enhancement -mode fet switch in such a way that the drain-source connection of the depletion mode fet switch forms part of said discharge path.

3. A driver circuit according to claim 2, c h a r a c t e r i z e d in that the driver circuit f or storing a charge at the gate connection of the depletion-mode f et switch during the first narrow control pulse, and second means for discharging said charge in response to the second narrow control pulse.

4. A driver circuit according to any of the foregoing claims, c h a r a c t e r i z e d in that the driver circuit comprises a transformerf which comprises means A 9 transmits the first and the second control pulse to the driver circuit in an isolated manner.

5. A driver circuit according to any of the foregoing claims, c h a r a c t e r i z e d in that it is the driver circuit of an enhancement-mode fet switch of a converter, whereby the first and the second control pulse are constituted by a bi polar signal derived from a PWM signal produced by the control circuit of the converter.

6. A driver circuit of an enhancement mode fet switch substantially as hereinbefore described with reference to the accompanying drawings.