GB2288932A - Fast settling pulse width modulated digital to analogue conversion - Google Patents

Abstract

A Digital to Analogue Converter feeds a Pulse Width Modulated (PWM) signal into a filter. The total time period of the PWM signal is divided into a number of equal time units. If X is the digital input then the most significant bit of X is output to the filter every other time unit, the next most significant bit of X is output every other remaining time unit, and so on, until all time units are used up. The resulting DC output from the filter will be an analogue signal proportional to the digital value X. Fig 1 is a schematic, Fig 2 shows a bit to time unit mapping for a 4 bit convertor and Fig 3 shows the input to the filter for X = 9. <IMAGE>

Description

Fast settling Pulse Width Modulated Digital to Analogue Conversion This invention relates to electronic circuitry and associated software used to convert digital signals to analogue (D-A) or analogue signals to digital form (A-D) Pulse Width Modulation (PWM) is a well established tequnique for converting digital signals to analogue form. Basically it consists of a square wave whoose duty cycle is modulated in direct proportion to the digital signal. This square waveform is put through a filter or averaging circuit to produce an average value proportional to the duty cycle, and so proportional to the digital signal. Normally the square wave has a constant frequency.

The disadvantage of this tequnique is that severe filtering is required to reduce the residual fluctuations in the analogue signal to less than 1 least significant bit. This results in a settling time of many cycles of the square wave, and/or a complex, expensive output filter. The problem becomes more acute as the resolution of the D-A convertor increases.

This invention specifies a simple method to significantly reduce the number of cycles of the PWM waveform needed for the output to settle. It is particularly applicable to situations where the maximum frequency of the PWM waveform is limited, for instance when using low power microcontrollers to produce the PWM waveform. Such situations are becoming increasingly common in industrial and commercial equipment.

According to the present invention, the total time period of the PWM waveform is divided into a number (N) of equal time units.

This number is given by N = 2n - 1, where n is the number of bits to be converted, somtimes called the resolution. Assume the digital number to be converted to analogue is called X, and is stored in binary form. Then the most significant bit of X is output to the filter every other unit, the next most significant bit of X is output every other remaining unit, and so on, until the least significant bit of X is reached, which will be output once only, in the middle of the sequence. The result is that for mid values of X, the frequency seen at the input to the filter approaches 2n/2 times the fundamental PWM frequency. The output filter eliminates these high frequencies easily, so output fluctuations become negligable for mid values of X.

Using this invention, the worst case fluctuations in output occur at X=l or at X=2n-2. Here the input signal to the filter beomes the same as that from a standard PWM circuit, in the form of one narrow pulse per PWM cycle. Hence at these values of X the fluctuations are the same as for a standard PWM circuit with the same filter.

The reduction in settling time comes about because a standard PWM circuit generates its most severe output fluctuations for mid values of X (ie. X=2n/2). Here the fluctuations are about times times the size of those at X=l or X=2n-2. (See note 1.) Thus the filter has to be designed for an attenutaion ratio (at the PWM fundamental frequency) of (2n-1)/w times that of the filter used in this invention, in order to give the same worst case performance.

With a first order filter, increasing the attenuation ratio by (2-l)/ will increase the settling time by (2n-1)/w times. With a second order filter, increasing the attenuation ratio by (2fl-l)/u will increase the settling time by at least the square root of (2n-1)/x times. For example, an 8 bit converter using standard PWM tequniques with a second order filter, will have a settling time over 9 times as long as the same converter using the present invention.

Notel: The comparative values of the fluctuations have been obtained by performing a Fourrier analysis of the PWM waveforms.

The amplitude of the fundamental for a 50% duty cycle, unity amplitude pulse is 2/E. The amplitude of the fundamental for a narrow, unity amplitude pulse of width t in a total cycle time of T, is 2t/T. Thus the ratio of fundamentals is T/(xt).

For X=l, the waveform is high for one unit in 2n-1 total units, giving a ratio of (2n-1)/x.

For X=2n-2, the waveform is low for one unit in 2n-1 total units, giving the same ratio of fundamentals.

As the output filter will be linear, the output fluctuations will also be in the same ratio as the fundamentals, if harmonics are assumed to be negligable. Because the filter will provide significant attenuation for the fundamental. and the 3rd harmonic will be attenuated by three times as much as the fundamental using a 1SL order filter, or nine times as much using a 2nd order filter, this assumption is valid. (The lowest frequency harmonic present for a rectangular pulse waveform is the 3rd).

The accompanying drawings show details of circuits which can be used to implement this invention, and of the PWM waveform which forms the input to the filter.

Fig.l shows a specific embodiment of the invention in a 4 bit converter with a second order filter. Note that the choice of a 4 bit convertor is not of practical significance, but merely allows graphic representation of the waveforms involved. Extrapolation to higher resolutions is straightforward. The block marked "ENCODER" could be implemented purely in hardware (eg. logic circuits), or as a microcontroller or other software controlled device obeying a programme.

Settling time of this convertor would be 2.2 times faster than a standard PWM circuit, due to the use of this invention.

Fig.2 shows the allocation of the bits of the input number X to the time units in the PWM cycle, for the 4 bit convertor of fig.l Fig.3 depicts the waveform for an input value of X=9 (1001 binary), for the 4 bit convertor of fig.l.

Fig.4 shows a specific embodiment of the invention in a 12 bit converter which uses two 6 bit PWM waveforms, weighted by resitors in the ratio 64:1 and summed to yield the required 12 bit output. To guarantee monotonicity, the ratio needs to be accurate to better than one part in 64. In practice, standard 1% resistors will give a high probability of achieving this without trimming. In critical applications, 0.5% resistors may be used for the weighting.

The use of two six bit convertors reduces the required operating speed of the micro-controller for a given settling time, as only 63 units per PWM fundamental period need be considered instead of 4095. The settling time is 4.5 times faster than a standard PWM circuit.

Fig.5 shows the "bit to time unit" mapping for a specific embodiment of the invention in a 12 bit converter which uses the dual convertor design as in Fig.4, but treats the three most significant bits and the three least significant bits of each 6 bit part of X separately. Effectively, it comprises two pairs of 3-bit converters each operating as per Fig.1, which are time division mutiplexed into one pair of 6-bit outputs. and which are then weighted and summed into a single 12-bit output.

The purpose of this modification is to provide further gain in the ratio of micro-controller operating speed to settling time.

During the 8 time units where a constant output is given, the micro-controller can be calculating the four outputs required for the next 9 time units.

In terms of settling time, this configuration behaves like a 3 bit convertor. It exhibits a factor of 1.5 improvement in settling time over a standard PWM circuit not utilising the present invention.

Fig.6 shows a specific embodiment of the invention in a 12 bit combined D-A and A-D convertor, in schematic form. The D-A section utilises two outputs of a four bit (or more) output port, and operates as in fig 4, with or without the modifications of fig.5. The A-D section uses a further two outputs, encoded in the same fashion. Two independant digital values (X in the descriptions above) are used, one for the D-A section, one for the A-D section. The two X values are output from the port simultaneously, all four signals changing state syncronously at the boundary of each time unit.

Operation of the A-D section is as follows: The integrator is initially reset. One complete PWM cycle is then given, using a trial value of X. If the value of X is above the input value, then the integrator will be more negative after the cycle. If the value of X is below the input value, then the integrator will be more positive after the cycle. Thus the output of the comparator can be sampled to adjust the next trial value of X, for instance by using the Successive Approximation algorithm.

The signal marked "CONVERT" is used to freeze the D-A output filter during the interval between valid PWM cycles, and, after a suitable delay, to reset the integrator. Thus the microcontroller need not care about the state of the output port during gaps between cycles, or about the exact timing of the gaps. This gives time for the next trial value. or any other results, to be calculated.

The advantage due to the use of the present invention in this embodiment is that where X is nearly correct, the output of the integrator swings over a smaller range during a conversion. This allows a smaller integrator capacitor to be used without risk of the integrator saturating. A smaller capacitor amplifies the integrator output, which makes the highly critical comparison process faster and more accurate. The improvement factor in integrator swing over standard P\NN tequniques is about (2"-1)/4 times.

Note that a Succesive Approximation A-D conversion, plus an auto-zero operation, takes 13 PWM cycles for 12 bits. In this time, a 12 bit D-A convertor using the configuration of Fig.4 can be optimised to settle to better than 0.033%. (Equivalent to 11 bits). Thus this combination can settle to a new D-A output value for each input reading.

Claims (9)

1 A Digital to Analogue Converter (D-A), formed by feeding a modified Pulse Width Modulated (PWM) signal into a filter.

Wherein the total time period of the PWM waveform is divided into a number (N) of equal time units. This number is given by N=2n-1, where n is the number of bits to be converted, somtimes called the resolution. Assume the digital number to be converted to analogue is called X, and is stored in binary form. Then the most significant bit of X is output to the filter every other unit, the next most significant bit of X is output every other remaining unit, and so on, until the least significant bit of X is reached. The resulting DC output from the filter will be an analogue signal proportional to the digital value X.

2 A 12 bit Digital to Analogue Converter (D-A), formed by combining two 6 bit P\ waveforms both derived as in claim 1, weighted by resitors in the ratio 64:1 and summed to yield an output with 12 bit resolution.

3 An n bit Digital to Analogue Converter (D-A), formed by combining two (n/2) bit PWM waveforms both derived as in claim 1, weighted by resitors in the ratio 2(n/2) :1 and summed to yield an output with n bit resolution.

4 A 12 bit Digital to Analogue Converter (D-A), formed by deriving two pairs of 3-bit PWM waveforms, all 4 waveforms derived as in claim 1, which are time division multiplexed into one pair of 6-bit outputs, and which are then weighted and summed into a single 12-bit output as in claim 3 above.

5 An n bit Digital to Analogue Converter (D-A), formed by deriving at least one PWM waveform as in claim 1, and which waveform is derived from the three (or more) most significant bits of the digital input value X. And wherein the remaining bits of X are combined into the output in any other fashion, including time division multiplexing or weighted summing.

6 An n bit Analogue to Digital Convertor (A-D), formed by feeding PWM waveforms derived as in claims 1 to 5, into an Integrator and Comparator, in order to compare an unknown anaoluge signal with the digital value X. And wherein the result of the comparison is used to alter X in order to deduce the value of the unknown analogue signal.

7 Any Analogue to Digital Convertor which utilises the Digital to Analogue tecniques in claims 1 to 5 as an essential part of its operation.

8 A combined n bit Analogue to Digital Convertor (A-D) and n bit Digital to Analogue convertor (D-A), where the D-A section functions as in claims 1 to 5, and where the A-D section functions as in claims 6 to 7, and where the A-D and D-A operations occur simultaneously and synchronously.

9 A Digital to Analogue or Analogue to Digital convertor substantially as in Figs 1 to 6 of the accompanying drawing.