GB2287146A

GB2287146A - Frequency converters

Info

Publication number: GB2287146A
Application number: GB9503809A
Authority: GB
Inventors: Katsuzi Kimura
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1994-02-25
Filing date: 1995-02-24
Publication date: 1995-09-06
Anticipated expiration: 2015-02-24
Also published as: JP2861795B2; GB2287146B; JPH07240630A; GB9503809D0

Abstract

A frequency converter comprises a first differential circuit formed with first and second transistors M1, M2 and optionally a second differential circuit formed with third and fourth transistors M3, M4. The first and second differential circuits are driven by equal values of constant current. An input alternating current signal is supplied between the gates of the first and second transistors with an offset voltage difference. Also, an input alternating current signal is supplied between the gates of the third and fourth transistors with an offset voltage difference. Then, the differential outputs of the first and second differential circuits are connected in cross-connection to selectively extract frequency component double of the frequency of the input alternating current signal. The offset voltage may be provided by DC bias, a pair of transistors or a transistor resistor combination. <IMAGE>

Description

FREQUENCY CONVERSION CIRCUIT BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to a frequency conversion circuit. More specifically, the invention relates to a frequency conversion circuit suitable for MOS integrated circuit in construction and having a frequency mixing circuit and a frequency multiplication function.

Description of the Related Art As a frequency multiplication circuit suitable for semiconductor integrated circuit, a circuit employing bipolar transistor as shown in Fig. 8 is known. Such circuit has been disclosed in the applicant's Japanese Unexamined Patent Publication No. 4-79504.

In Fig. 8, transistors Q, and Q2 are first pair of transistors forming a differential amplifier and transistors Q3 and Q4 are second pair of transistors forming a differential amplifier. Such pair of transistors forming the differential amplifier will be hereinafter referred to as "differential pair of transistors". Both differential pairs are driven by a constant current sources 1o of equal values, respectively.

Respective differential pairs are differentiated to each other in current driving performances. Namely, an emitter size ratio between the transistors Q, and Q2 and the transistors Q3 and Q4 is selected to be Q2 : Q1 = Q, = 1 : K (K > 1).

Between bases of the transistors Q, and Q1, input signal VN is applied. Also, between base of the transistors Q, and Q4, the input signal VN is applied. The collectors of the transistors Q, and Q4 are commonly connected and the collectors of the transistors Qz and Q3 are also commonly connected. From two junctions of common connection of the collectors, differential output VOUT is output.

Resistors R, serve as a collector load resistor for the transistors Q1 to Q4.

To one of the common junction (common collector output point of the transistors Q1 and Q4), a constant current source of a{(k-1)/(k+1)}I0 is connected for determining operation voltage of the circuit.

In the construction set forth above, when direct current amplification factors of the transistors Q1 to Q4 are aF, collector currents IC1, IC2, lo, I, are expressed by the following equations (la) to (1d). It should be noted-that, in the following equations (la) to (ld), VT is expressed by Vt= kT/q with a Boltzmann's constant k, absolute temperature T and unit electron charge q, and V@ is expressed as the following equation (2) using VT.

Vk = VT ln k (2) 1C1 - IC2 (= #I1) is expressed by the following equation (3) and IC3 - IC4 (= #I2) is expressed by the following equation (4). Therefore, a differential output current Al becomes as expressed in the following equation

#I = (IC1 + IC3) - (IC2 + IC4) = (IC1 - IC2) - (IC3 - IC4) = #I1 + #I2

Since cosh x is progressively expanded as shown in the following equation (6), the differential output current expressed by the foregoing equation (5) may be expressed as shown in the following equation (7), wherein square term of the input signal VIN is included in the equation (7). cosh x = 1 + x2/2 + x4/12 + .... (x2 < #.).... (6)

Defining the input signal VZN by the following equation (8), the square term of the input signal VIN becomes as expressed by the following equation (9).

Thus, it should be appreciated that the frequency is duplicated.

VIN = |VIN| cos (2#ft) ..... (8) VIN = |VIN| cos (2#ft) |VIN| [cos {2# (2f) t}+1] 2 Next, as the frequency mixing circuit, a circuit employing Gilbert cell is known. This circuit is constructed on the bipolar integrated circuit. When the circuit is constructed on the MOS integrated circuit, the circuit structure will becomes as illustrated in Fig. 9.

In Fig. 9, the shown frequency mixing circuit includes two sets of differential pair of transistors M1l.

M12 and Ml3, M14 are arranged between a pair of input terminals 1 and 2, and one set of differential pair of transistors M15 and M16 for driving the two sets of differential pair of transistors are arranged between a pair of input terminals 3 and 4. The one set of differential pair of transistors M15 and M16 are driven by one constant current Ioo.

Namely, in the two sets of differential pairs of transistors Mali, M12 and M13, M14, drains of one of respective sets of transistors M11 and M13 are connected commonly, and drains of the other of respective sets of transistors M12 and M14 are connected commonly. One (Mll) of the differential pair of transistors M11 and M12 has the gate connected to one (1) of the pair of input terminals 1 and 2 commonly with the gate of the other (M14) of the differential pair of transistors M13 and M14. Also, the gate of the other (M12) of the differential pair of transistors M11 and M12 is connected to the other input terminal (2) commonly with the gate of one (M13) of the differential pair of transistors M13 and M14.

In the differential pair of transistors M15 and M16, one transistor M15 has the drain connected to the sources of the differential pair of transistors M1l and M12 and the gate connected to one (3) of the pair of input terminals 3 and 4. The other transistor M16 has the drain connected to the sources of the differential pair of transistors M13 and M14 and the gate connected to the other input terminal (4). For the pair of input terminals 1 and 2, a second alternating current signal (voltage VL0 is applied. On the other hand, for the pair of input terminals, a first alternating current signal (voltage VRF) is applied.

Hereinafter, discussion will be given for operation of the circuit shown in Fig. 9 as the frequency mixing circuit. In Fig. 9, it is assumed that ratios (W/L) of the gate widths W and the gate lengths L of the transistors M11, M12, M13, M14 are equal to each other and (W/L)1 , mobility of the transistor is n, a gate oxide layer capacity per unit area is Cax, then a transistor conductance parameter p1 can be expressed by the following equation (10). Further assuming that a threshold voltage is VT and gate/source voltage is Vasi (i = 11 to 14), the drain currents 1di 1' Id12, Id13 and 1d14 can be expressed by the following equations (11) to (14).

Id11 = ss1 (VGS11 - VT) ..... (11) Id12 = ss1 (VGS12 - VT) ..... (12) Id13 = ss1 (VGS13 - VT) ..... (13) Id14 = ss1 (VGS14 - VT) ..... (14) Here, Id15, Id16, 100 and VLO are expressed by the following equations (15) to (18).

Id11 + Id12 = Id15 ..... (15) Id13 + Id14 = Id16 ..... (16) Id15 + Id16 = I00 ..... (17) VGS11 - VGS12 = VGS14 - VGS13 = VL0 ..... (18) Subsequently, assuming the ratios of the gate width and the gate length of the transistors Mls and M16 are respectively (W/L)2, the transistor conductance p2 can be expressed by the following equation (19). Therefore, the drain currents Id15 and 1d16 may be expressed by the following equations (20) and (21). Also, the first alternating current (voltage VRF) is expressed by the following equation (22).

Id15 = ss2 (VGS15 - VT) ..... (20) Id16 = ss2 (VGS16 - VT) ..... (21) VGS15 - VGS16 = VRF ..... (22) When IVRF = Id15 - Id16 is obtained by solving the foregoing equations (17), (20) to (22), the following equation (23) is established. Then, Id15 and Id16 are expressed by the following equations (24) and (25).

Id15 = (1/2) (I00 + IVRF) ..... (24) Id16 = (1/2) (I00 - IVRF) ..... (25) On the other hand, defining IVL0 as expressed by the following equation (26), the input voltage VLO can be expressed by the following equation (27).

Accordingly, #I = I31 - I32 can be expressed by the following equation (28).

In the equation (28), assuming

Al can be approximated as expressed by the following equation (29).

#I # (I/I00) IVRF . IVL0 ..... (29) Here, IVL0 corresponds to a differential output current of a differential amplifier driven by a constant current source I00/2 with respect to an input voltage VLO.

On the other hand, IVRF expresses the differential output current of the differential amplifier driven by a constant current source IOo with respect to the input voltage VRF, as expressed by the equation (23).

Accordingly, IVL0 is substantially proportional to the input voltage VL0. IVRF is substantially proportional to the input voltage VRF. When the input voltages VRF and VLO are small, the circuit shown in Fig.

9 becomes a multiplier.

Also, when the foregoing equation (28) is progressively expanded, Al becomes as expressed by the following equation (30). Therefore, ignoring secondary or higher degree of terms of respective input voltages VLO and VRF, the following equation (31) can be obtained.

..... (30) #I = #2#ss1#ss2VL0 .VRF ..... (31) Here, by defining the input voltages VLO and VRF as expressed by the following equations (32) and (33) and obtaining the product thereof, components of sum and difference to two frequencies can be obtained as expressed by the following equation (34).

VL0 = |VL0| cos 2# fL0t ..... (32) VRF = |VRF| cos 2# fRFt ..... (33) VL0 . VRF = (1/2) |VL0| |VRF| [cos {2# (fL0t) + fRFt)t} + cos {2# (fL0t - fRFt)t}] ...... (34) Since 121 and 122 are differential currents, they can be expressed by the following equations (35) and (36), and respectively include #(1/2)#I. Accordingly, the gilbert cell as illustrated in Fig. 9 serves as the frequency mixing circuit.

I31 = (1/2)(I00 + #I) ..... (35) I32 = (1/2)(I00 - #I) ..... (36) The conventional frequency multiplication circuit is operable at low voltage. However, since emitter size of one of the transistors of the differential pair is set at K times (K > 1), the size of the transistor becomes large to degrade frequency characteristics.

Also, when the frequency mixing circuit is constructed as illustrated in Fig. 9 with employing the gilbert cell, the circuit becomes a vertically stacked circuit. Thus, the power source voltage becomes high.

Also, number of elements is large, NF (noise factor) is degraded, and circuit current becomes large. Furthermore, since the input voltages (VLO,VRF) are approximated to each other only when both are small, they may be adapted by adjustment of the resistance of the emitter for operation under large inputs to encounter a problem to cause tertiary distortion.

SUMMARY OF THE INVENTION Therefore, it is an object of at least the preferred embodiments of the present invention to provide a frequency conversion circuit suitable for packaging into MOS integrated circuits, operable at low voltage and having a frequency multiplication function and a frequency mixing function operable at high frequency.

According to one aspect of the invention, a frequency conversion circuit comprises: a first transistor arranged to receive a first alternating current signal at the gate thereof; a second transistor connected to said first transistor to form a differential amplifier; and offset voltage generating means for supplying a second alternating current signal having superimposed thereon an offset voltage to the gate of said second transistor.

According to another aspect of the invention, a frequency conversion circuit comprises: a first transistor arranged to receive an alternating current signal at the gate thereof; a second transistor connected to said first transistor to form a differential amplifier; and first offset voltage generating means for supplying said alternating current signal with an offset voltage superimposed thereon to the gate of said second transistor; third transistor and fourth transistors connected to form a differential amplifier and arranged to receive said alternating current signal at the gate of the fourth transistor; second offset voltage generating means for supplying said alternating current signal with an offset voltage superimposed thereon to the gate of said third transistor; and extracting means for selectively extracting an output having a frequency double that of the frequency of said alternating current signal from at least one of a junction of commonly connected drains of said first and fourth transistors and a junction of commonly connected drains of said second and third transistors.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood more fully from the detailed description given hereinafter and from the accompanying drawings of the preferred embodiments of the invention, which, however, should not be taken to be limitative to the invention, but are for explanation and understanding only.

In the drawings: Fig. 1 is a circuit diagram of the first embodiment of a frequency conversion circuit with a frequency multiplication function according to the present invention; Fig. 2 is a chart showing transfer characteristics of the frequency multiplication circuit of the present invention; Fig. 3 is a chart showing a transconductance characteristics of the frequency multiplication circuit of the invention; Fig. 4 is a circuit diagram of the second embodiment of the frequency conversion circuit with the frequency multiplication function according to the invention; Fig. 5 is a circuit diagram of the third embodiment of the frequency conversion circuit with the frequency multiplication function according to the invention; Fig. 6 is a circuit diagram of the fourth embodiment of the frequency conversion circuit with a frequency mixing function according to the invention; Fig. 7 is a circuit diagram of the fifth embodiment of the frequency conversion circuit with a frequency mixing function according to the invention; Fig. 8 is a circuit diagram of the conventional frequency multiplication circuit; and Fig. 9 is a circuit diagram showing the frequency mixer circuit constructed with a gilbert cell.

DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiment of the present invention will be discussed hereinafter in detail with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a through understanding of the present invention. It will be obvious, however, to those skilled in the art that the present invention may be practiced without these specific details. In other instance, wellknown structures are not shown in detail in order to unnecessary obscure the present invention.

Fig. 1 shows the first embodiment of a frequency conversion circuit with a frequency multiplication function, according to the present invention. The shown circuit is constructed with two differential pairs of transistors. Transistors M1 and M2 form a first differential pair of transistors and transistors M3 and M4 form a second differential pair of transistors. Both of the differential pairs of transistors are driven by constant current sources having equal current values 1o.

The drains of the transistors M1 and M4 are commonly connected and the drains of the transistors M2 and M3 are also commonly connected. From one or both of the common junctions of the drains, a frequency double of a frequency of the input signal V1 is selectively extracted via a band-pass filter (BPF) 10.

Between gates of the transistors M1 and M2, input signal V1 is applied. In the shown embodiment, for the input signal V1 to be applied to the gate of the transistor M2, an offset voltage Vk is superimposed.

Similarly, the input signal V1 is applied to the gates of the transistors M3 and M4. For the input signal V1 to be applied to the gate of the transistor M3, the offset voltage Vk is superimposed.

Accordingly, in the first embodiment illustrated in Fig. 1, while the input signal (voltage V1) is applied to the gates of the transistors M1 and M4, the input signal V1 superimposed with the offset voltage Vk is applied to the gates of the transistors M2 and M3. It should be noted that while the offset voltage Vk may be generated by employing a battery, it may also be generated by employing transistor as shown in Figs. 4 and 5.

In the shown construction, a differential output current Al1 of the transistors M1 and M2 becomes as expressed by the following equation (37), and thus becomes as expressed by the following equation (38).

Similar, a differential output current Al of the transistors M3 and M4 becomes as expressed by the following equation (39), and thus becomes as expressed by the following equation (40).

Accordingly, a differential output current Al to be obtained by alternately connecting the outputs of two differential pairs of transistors can be expressed by the following equation (41). Thus, the foregoing equation (37) can be approximated by the following equation (42). At this time, an approximation error is less than or equal to 3% within a range where the input voltage is in a range of

Similarly, the foregoing equation (39) can be approximated by the following equation (43).

#I = #I1 - #I2 ..... (41)

Namely, as can be clear from the foregoing equations (42) and (43), since a term of the square of the input voltage V1 is included, the circuit shown in Fig. 1 is a doubler circuit. Accordingly, by BPF 10, the frequency component double of the frequency of the input signal may be extracted. A transfer characteristics and a transconductance characteristics of the frequency conversion circuit are shown in Figs. 2 and 3, respectively.

Needless to say, the frequency conversion circuit of Fig. 1 may be used as a single type, in which an alternating current signal is applied to the input terminal of one of the transistors M1 and M4 and the other input terminal is grounded.

Next, examples of concrete construction of the frequency conversion circuit incorporating an offset voltage generation circuit and an output circuit to the circuit illustrated in Fig. 1 will be discussed with reference to Figs. 4 and 5, in which Figs. 4 and 5 show the second and third embodiment of the frequency conversion circuits with the frequency multiplication function.

At first, in Fig. 4, transistors Ms, M8 and M7, M8 form the offset voltage generating circuit, and transistors M9 and M10 are active loads forming the output circuit.

The offset voltage generation circuit in the shown embodiment is formed with two transistors driven by mutually different current values so that the offset voltage Vk is generated by the voltage difference between these two transistors.

Namely, the transistors M5 and Me take Ioo as a drive current and the transistors M6 and M7 take KIoo as drive current to perform source-follower operation. The input terminals of the transistors M5 and ME are connected commonly, and the input terminals of the transistors M7 and M8 are connected commonly, so that the input voltage (voltage V1) may be applied thereto. To the source of the transistor M5, the input terminal (gate) of the transistor M3 is connected. Similarly, to the source of the transistor M6, the input terminal (gate) of the transistor M1 is connected. The source of the transistor M7 is connected to the input terminal (gate) of the transistor M4, and the source of the transistor M8 is connected to the input terminal (gate) of the transistor M2.

Accordingly, between the input terminals of the transistors M1 and M3, the voltage difference (offset voltage) of the transistors M5 and M6 is applied. Also, between the input terminals of the transistors M2 and M4, the voltage difference (offset voltage) of the transistors M8 and M7 is applied. Then, the input signal is applied to the input terminals of the transistors M and M4 as is. On the other hand, the input signal is applied to the input terminals of the transistors M2 and M3 with the offset voltage superimposed thereon.

It should be noted that as a method for generating the offset voltage by a voltage difference of two transistors, other than the method of differentiating the drive current values, a method for differentiating performances (defined by a ratio of the gate length and the gate width) with the equal drive current, a method for differentiating both of the current values and the performances (hybrid system) of the transistors, and so forth may be taken. In particular, the hybrid system is advantageous since it permits selection of parameter depending upon weighting whether a chip size is given importance or reduction of current is given importance and thus is superior in flexibility in designing and facilitates down-sizing.

On the other hand, Fig. 5 shows an embodiment, in which the offset voltage generating circuit is constructed with respectively one transistors M1l and M12 so that the offset voltage is generated by voltage drop at resistors R1 inserted in respective sources. The transistors Mii and M12 are driven by the constant current sources Ioo of substantially the same values to perform source-follower operation. The source side of the resistor R1 inserted in the source of the transistor M is connected to the input terminal of the transistor M3, and the power source side thereof is connected to the input terminal of the transistor M1. Similarly, the source side of the resistor R1 inserted in the source of the transistor M12 is connected to the input terminal of the transistor M2 and the power source side thereof is connected to the input terminal of the transistor M4.

It should be appreciated that even the frequency conversion circuit shown in Figs. 4 and 5 may be used as single type.

Next, Fig. 6 shows the fourth embodiment of the frequency conversion circuit. The shown embodiment of the frequency conversion circuit incorporates a frequency mixing function. The frequency conversion circuit comprises one differential pair of transistors M1 and M2 driven by the constant current source 1o. To the input terminal (gate) of the transistor M1 , a first alternating current signal (voltage VRF) is applied. Likewise, to the input terminal (gate) of the transistor M2 , a first alternating current signal (voltage VLO) is applied.

In the construction set forth above, assuming that the transistors M1 and M2 are in operation within a saturation range, a drain current 1d1 can be expressed by the following equation (44) and a drain current 1d2 can be expressed by the following equation (45). A sum of both currents is the constant current source 1o and thus can be as expressed by the following equation (46).

Id1 = (VGS1 - VT) ..... (44) Id2 = (VGS2 - VT) ..... (45) Id1 + Id2 = I0 ..... (46) On the other hand, since a differential input voltage Vin can be expressed by the following equation (47), from the equations (44) to (47), the output current Al1 can be derived through the equations (48) to (50) depending upon the range of the input voltage. In the equations (48) to (50), V is

VRF - VLO - Vk = Vin ..... ( (47)

(|Vin| # V ) ..... (48) #I1 = Id1 - Id2 = I0 (Vin # V ) ..... (49) #I1 = Id1 - Id2 = 0 (Vin # V ) ..... (50) The foregoing equation (48) may be approximated by the following equation (51).

(|Vin| # V ) The foregoing equation (51) may maintain an error less than or equal to 3% when the input voltage is in a range of Vin < 5 V in comparison with the equation (48) derived from the equations (44) and (45). Comparing the current characteristics of the MOS transistor with a simulated value employing SPICE model expressed by Shockley's equation, the relationship between the SPICE value and the equation (51) is better approximated relationship than the relationship between the SPICE value and the equation (48). Here, the SPICE value also have an error less than or equal to 3% when the input voltage is in a range of IVini # Vp.

Accordingly, it can be said that the equation (51) achieves quit good level as approximated equation expressing the input/output characteristics of the differential pair of transistors. Expanding the equation (51), the following equation (52) is established.

Since VRFVL0 of the product of VRF and VLO is included in this equation (52), sum and difference of two frequencies can be obtained through the equations (32), (33) and (34). Here, since Id1 and Id2 are differential current, 1d1 can be expressed by the following equation (53) and 1d2 can be expressed by the following equation (54). These equations (53) and (54) include #(1/2)#I1, respectively. Accordingly, by voltage conversion of dI or Id1, Id2, the frequency mixing function can be achieved.

Id1 = (I0 + #I1)/2 ..... (53) Id2 = (I0 - #I1)/2 ..... (54) Accordingly, the sum or difference component of two frequencies can be extracted by BPF 10.

It should be appreciated that as the offset voltage Vk, the voltage difference between two transistors having input terminal (gate) connected commonly, or the voltage drop of the resistor interposed in the source of one transistor. In such case, the input signal of the transistor may be a sum signal and difference signal of the first and second alternating current.

On the other hand, assuming VRF = VLo, the frequency multiplication circuit can be established.

Next. Fig. 7 shows the fifth embodiment of the frequency conversion circuit with the frequency mixing function. The frequency conversion circuit comprises two differential pairs of transistors M1, M2 and M3, M4.

Between these two differential pairs of transistors, the output terminals (drains) are connected commonly to form a differential output pair. Between input terminals (gates) of the transistors M1 and M4 and between the input terminals (gates) of the transistors M2 and M3, offset voltage Vk having the same polarity to the polarity at the input terminals of the transistors which have output terminals connected commonly, is generated. The foregoing construction is substantially the same as that of Fig. 1.

In the frequency conversion circuit, the first alternating current signal (voltage VRF) is applied to the input terminal of the transistor M1 as is and to the input terminal of the transistor M4 as superimposed on the offset voltage Vk. Likewise, the first alternating current signal (voltage VL0) is applied to the input terminal of the transistor M3 as is and to the input terminal of the transistor M2 as superimposed on the offset voltage Vk.

In the construction set forth above, the differential output current Al can be derived through the following equation (55).

#I = I1 - I2 = (Id1 + Id3) - (Id2 - Id4) = (Id1 - Id2) + (Id3 - Id4) = #I1 + #I2 # f(VRF - VL0 - Vk) + f(-VRF + VL0 - Vk) Vk 1 1 = 2#2 I0 [- - (1- ) {-3VkVRF V #2 V -3 Vk VL0 + 6Vk VRF VL0 - Vk }]

Since, the foregoing equation (55) includes the produce VRFVL0 of VRF and VLO, the sum and difference of two frequencies can be derived through the equations (32), (33) and (34). Here, since I1 and I2 are differential currents, Ii can be expressed by the following equation (56), and I2 can be expressed by the following equation (57). These equations contain #(1/2)#I. Accordingly, by voltage conversion Al or I1, I2, the frequency mixing function can be established.

Ii = Ic + he/2 (56) I2 = Io + hI/2 (57) In the constructions of Figs. 6 and 7, two input signals are separated with each other and the first and second alternating current signals are applied to different input terminals. Therefore, the transistors forming the differential pair can be constructed with a minimum dimension. Therefore, degradation of the high frequency characteristics can be reduced. In case of the MOS transistor, the range of input voltage can be determined arbitrary with taking into account the relationship of

At this point, the present invention is differentiated from the bipolar transistor.

On the other hand, in the construction of Fig.

7, it is possible to take only one signal input terminal to apply the sum signal or difference signal of the first and second alternating current signals. Also, by applying one kind of alternating current signal to one signal input terminal, the frequency multiplication circuit can be established.

As set forth above, the frequency multiplication function and the frequency mixing function are differentiated in number of the input signals (i.e. one or two), and both circuits are the same in constriction for realizing doubler characteristics by connecting the output terminals of the two differential pairs in crossing manner to form the differential output pairs, and input terminals are also connected in crossing manner via the offset voltage. Thus, doubler characteristics can be realized.

Accordingly, the frequency conversion circuit with the frequency multiplication and frequency mixing functions according to the present invention is constructed with the MOS transistors. Even when number of the differential pair is two, the frequency conversion circuit may be constructed with laterally aligned arrangement to permit low voltage operation in theory.

Also, since minimum unit of transistors are employed, the scale of the circuit will not be increased to permit high frequency operation.

Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. Therefore, the present invention should not be understood as limited to the specific embodiment set out above but to include all possible embodiments which can be embodied within a scope encompassed and equivalents thereof with respect to the features set out in the appended claims.

Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

The appended abstract as filed herewith is included in the specification by reference.

Claims

CLAIMS: 1. A frequency conversion circuit comprising: a first transistor arranged to receive a first alternating current signal at the gate thereof; a second transistor connected to said first transistor to form a differential amplifier; and offset voltage generating means for supplying a second alternating current signal having superimposed thereon an offset voltage to the gate of said second transistor.
2. A frequency conversion circuit as set forth in Claim 1, which comprises selective extraction means for selectively extracting an alternating current component of a frequency of a sum or a difference of the frequencies of said first and second alternating current signals from the drain of at least one of said first and second transistors.
3. A frequency conversion circuit as set forth in Claim 1, wherein said first and second alternating current signals have the same frequency, and which comprises extracting means for extracting an alternating current signal having a frequency double that of the frequency of the received alternating current component from the drain of at least one of the first and second transistors.
4. A frequency conversion circuit as set forth in Claim 2 or Claim 3, wherein said offset voltage generating means comprises two transistors operating at mutually different values of drain current and being supplied with the first and second alternating current signals through respective gates thereof, the gate source voltage difference of the two transistors serving as the offset voltage.
5. A frequency conversion circuit comprising: a first transistor arranged to receive an alternating current signal at the gate thereof; a second transistor connected to said first transistor to form a differential amplifier; and first offset voltage generating means for supplying said alternating current signal with an offset voltage superimposed thereon to the gate of said second transistor; third transistor and fourth transistors connected to form a differential amplifier and arranged to receive said alternating current signal at the gate of the fourth transistor; second offset voltage generating means for supplying said alternating current signal with an offset voltage superimposed thereon to the gate of said third transistor; and extracting means for selectively extracting an output having a frequency double that of the frequency of said alternating current signal from at least one of a junction of commonly connected drains of said first and fourth transistors and a junction of commonly connected drains of said second and third transistors.
6. A frequency conversion circuit as set forth in Claim 5, wherein each of said first and second offset voltage generating means respectively comprise two transistors operable at mutually different values of drain current and being supplied with said alternating current signal at their gates, respective gatesource voltage differences of said two transistors being taken as said offset voltage.
7. A frequency conversion circuit as set forth in Claim 5, wherein each of said first and second offset voltage generating means comprises an offset generating transistor arranged to operate at a predetermined value of drain current and supplied with said alternating current signal at its gate, a resistor being connected to said offset generating transistor in series, a voltage across said resistor being taken as said offset voltage.
8. A frequency conversion circuit substantially as herein described with reference to Figures 1 to 7 of the accompanying drawings.