GB2284929A - High electron mobility transistors - Google Patents

Abstract

The transistor 1 comprises a first active layer and a second active layer separated by a barrier layer. A source region 5 and a drain region 7 are mutually separated and each contact the first and second active layers. A gate electrode 11 is arranged above the active layers in a region between the source and drain regions 5, 7. The barrier layer is sufficiently thin that in use, when a voltage applied to the gate electrode 11 is of a magnitude substantially to equalise carrier densities in the active layers, the electrical resistance between the source and drain regions 5, 7 is reduced. In one embodiment constituting a high speed switch, one of the active layers is divided into two branches in one of which a current flows constantly and in the other, the current is switched on or off by the gate voltage. <IMAGE>

Description

SEMICONDUCTOR DEVICE The present invention relates to a semiconductor device of the kind which controls electrical current by influencing high mobility carriers which can exist as a so-called two-dimensional electron gas (2DEG) adjacent a hetereointerface.

It is well known that by arranging layers of semiconductor layers of different bandgaps, it is possible to produce a quantum well adjacent an interface in order to confine carriers so that the current flowing in the well layer between source and drain regions can be modulated by means of a control potential applied to an overlying gate electrode. This modulation can be effected by predominantly influencing the number of carriers flowing as in a conventional MOSFET (their mobility staying relatively unchanged) or by changing their mobility (the total carrier concentration remaining relatively constant). The latter effect is hereinafter referred to as 'velocity modulation8.

In order to achieve a degree of velocity modulation sufficient to enable realisation of a practical device, there has been proposed a structure in which two separate quantum well layers are separated by a thin barrier layer. - Impurities in one of these layers enhance wave-function dependent scattering. Application of a gate control potential is used to match carrier densities in the respective well layers. When the densities are matched, the mobility in each changes. In the low mobility layer, mobility is increased and in the high mobility layer it is decreased. However the net conductivity is decreased, manifesting itself in a measurable negative transconductance. This phenomenon is described by Ohno Y. et al in Appl. Phys. Lett. 62 (16), 1993, 1952-1954 following an earlier similar proposal by Palevski A. et al. in Phys. Rev. Lett. 65 (15), 1990, 1929-1932.

It should be noted that the aforementioned known double quantum well devices are quite different in mode of operation to those described in our U. K. patent specification GB-A-2 262 385 where two quantum well layers are completely isolated from one another by an intermediate barrier layer (or the equivalent). The gate potential is used to transfer electrons from one (low mobility) layer to the other (high mobility) layer by distorting the confinement potentials experienced by the electrons. The intermediate barrier layer is substantially thicker than that in the device described by Ohno et al.

However, the intermediate barrier layer in the Ohno et al. type of device has to be so thin that it is difficult to control its formation accurately during fabrication. A new kind of device which avoids this disadvantage has now been devised in accordance with the present invention which provides a semiconductor device comprising a first active layer and a second active layer separated by a barrier layer, a source region and a drain region being mutually separated and each contacting at least one of said first and second active layers, and a gate electrode being arranged above the first and second active layers in a region between said source and drain regions, the barrier layer being sufficiently thin that in use, when a voltage applied to the gate electrode is of a magnitude to equalise substantially carrier densities in the first and second active layers, the electrical resistance across the source and drain regions is reduced.

Devices according to the present invention are more susceptible of high temperature operation (i.e.at or near room temperature) than devices of the kind described by Ohno et al since a thicker barrier layer can be used.

Without wishing to be bound by any theory, the applicants believe that the principle of operation of devices according to the present invention is as follows. One of the first and second active layers provides a main conduction channel which conducts a source-to-drain current, regardless of the applied gate potential. For example, if the lower layer is used as the main conduction channel layer, then the source-to-drain current is independent of the applied gate potential, due to screening of the potential by the upper active layer. In the absence of a gate switching potential, the other active layer does not act as a conduction channel, either because substantially no carriers are induced in it or because the carriers in it are isolated. In any event, the two active layers are isolated from each other except when the carrier densities are matched.

The main difference between devices according to the present invention and the kind of devices according to Ohno et al or as described in GB-A-2 262 385 is that with these earlier proposals, the change in device resistance is due to a change in mobility at resonance, or by moving the position of the conduction channel (quantum well). With the present invention, mobility is unaltered but device resistance is changed due to the fact that one conduction channel is isolated except at resonance, when the two channels become coupled.

Referring again to devices according to the present invention, the source and drain must contact at least the active layer constituting the main conduction channel. However, in practice the close proximity of the first and second active layers separated by the thin barrier layers means that for most practical devices, the source and drain will be in physical contact with both active layers. Therefore, if carriers already exist in the other active layer (i.e. the layer other than that acting as a main conduction channel) prior to application of the gate switching potential, they may be isolated by application of a depletion potential to a depletion gate electrode overlying the active layers between the aforesaid gate electrode (hereinafter referred to as the "primary gate electrode") and one of the source and drain regions. However, preferably there is a further depletion gate electrode, to be applied with substantially the same depletion potential, also arranged over the active layers between the primary gate electrode and the other of the source and drain regions.

If carriers are not already induced in the other active layer prior to application of the gate switching potential, then the device must be fabricated so that carriers are induced in the other active layer sufficient to reach the switching condition where the carrier densities are matched.

In any event, the threshold voltage is the potential applied to the gate to cause the carrier densities in the respective active layers to be equalised or substantially equalised. Then, electron tunnelling may occur across the barrier layer to transfer from the 2DEG in one active layer to the 2DEG in the other. In this way, the carriers from the other layer contribute to the current flowing in the main conduction channel, thus decreasing the resistance measured across the source and drain.

In practice, it is likely that equalising the carrier densities will not always just result in changing the density in only one of the active layers to match the other. Since one has control of the carrier densities in both layers, the equalisation of the carrier densities can be achieved at any chosen carrier concentration. In this way, the switching voltage can be altered as required.

In order to maximise the decrease in device resistance at the threshold voltage, it is preferred for the carrier mobilities in the respective active layers to be different. More especially, it is preferred if the mobility in the active layer acting as the main conduction channel is the lower of the two. Normally, this will means that the active layer with the high mobility will be that closest to the primary gate electrode.

If a second gate electrode (in addition to any depletion gate electrode(s)) is provided on the reverse side of the device relative to the primary gate electrode, this may be used to modify the threshold voltage.

In principle, there are several different ways of fabricating the device so that in use, the respective carrier mobilities in the active layers will be different. For example, one active layer may be doped, and the other left undoped, or they may be doped with respective different impurity concentrations. In practice, the lower of the two such layers (relative to the substrate) is likely to have a lower degree of doping because of upward diffusion of impurities.

Alternatively, the respective mobilities may be made different by providing two spacer layers of respective different thicknesses and/or doping balls outside (relative to the barrier layer) of each active layer.

Yet again, difference in surface roughness of the active layers may be used to the same end. In these cases, the difference in mobility is effected by controlling scattering in the respective quantum wells (2DEGs). In fact any means known to those skilled in the art for causing a difference in mobilities may be employed to this end.

In one embodiment, the active layer corresponding to the main conduction channel is divided into a plurality of branches. Current is arranged to flow in at least one of these branches, between source and drain regions. Current is switched on and off in one or more of the other branches by the gate voltage, to flow to a respective further drain region or regions. This is achieved by virtue of the gate voltage causing the 2DEG in the other active layer to be coupled with the other 2DEG in the branched layer. With this kind of device, only a small voltage is required to switch the current, so that very high speed switching can be achieved.

Furthermore, the same control gate can be used to switch current on and off in more than one current branch which may thus be used for addressing cells in arrays.

The barrier layer must be of a thickness sufficiently low to permit tunnelling of electrons across it when the carrier densities become equalised.

This will be materials dependent. For example, when the active layers are formed of GaAs with an intermediate Al GaAs barrier layer, then the barrier layer will usually have a thickness of 20 nm or less and preferably of 3 nm or more.

Although it is not absolutely necessary, usually the two active layers will be composed of the same semiconductor material, albeit usually with different doping levels. However, the two active layers could in principle be formed of different semiconductor materials. In any event, the barrier layer may be a discrete layer of high bandgap material formed between the active layers or it may be a thin region within a mass of a single semiconductor material and having a profiled composition having a higher bandgap, e.g.

AlxGal~xAs within a GaAs layer.

The present invention will now be explained in more detail by reference to the following description of a preferred embodiment and with reference to the accompanying drawings, in which: Figure 1A shows a simplified cross-section of a first embodiment of a semiconductor device according to the present invention, for explaining the principles of operation thereof; Figure 1B is a plan view of the device shown in Figure 1A, showing the electrical contacts thereto; Figure 2 is a detailed cross section through a central portion of the device shown in Figures 1A and 1B, showing individual semiconductor layers; Figure 3 is a graph showing the source/drain resistance of the device shown in Figures 1A, 1B and 2, as a function of front gate voltage; and Figure 4 shows a schematic diagram of a second embodiment of a semiconductor device according to the present invention.

Referring now to Figures 1A and 1B, a semiconductor device 1 according to the present invention comprises a layered semiconductor structure 3. At either end of this structure and situated, respectively, a source region 5 and a drain region 7 formed as ohmic contacts.

On the upper surface 9 is formed a primary gate electrode 11 provided with a contact pad 13. Also on the upper surface 9, spaced between the source region 5 and the primary gate electrode 11 is arranged a first depleting gate 13 provided with a contact pad 15.

Similarly on the upper surface 9, a second depleting gate 17 is arranged between the primary gate 11 and the drain 7 and is provided with a contact pad 19.

The semiconductor layer structure 3 is configured such that in use, an upper quantum well is induced, confining electrons of an upper 2DEG 21 below the upper surface 9. Below the upper 2DEG and spaced apart therefrom is induced a lower quantum well layer, confining electrons of a lower 2DEG 23. A lower gate 25 is situated below the layer structure 3. The lower gate 25 is also provided with a contact pad 27.

When a potential difference is applied across the source and drain, a current flows therebetween by virtue of the lower 2DEG 23. However, the upper 2DEG does not contribute to the current flowing between source and drain because it is depleted-out in regions 29,31 respectively below the first and second depleting electrodes 13, 17 when an appropriate depleting potential is applied to the latter.

The layer structure 3 is also formed such that the carriers in the upper 2DEG 21 have a higher mobility than those in the lower 2DEG 23. When a switching potential applied to the primary gate electrode 11 is of a magnitude sufficient to equalise the carrier densities, electron tunnelling can occur between the two 2DEGs across the barrier therebetween (see Figure 2) so that the high mobility electrons in the upper 2DEG contribute to the current flowing between source and drain, thus significantly lowering the source/drain resistance.

The semiconductor layer structure 3 is shown in detail in Figure 2.

On a GaAs 33 substrate is formed a 50 mm back 18 with barrier layer 35 of GaAs doped at 3 x 10 cm with n-type impurities. On the latter is formed next, a 250 nm AlGaAs back barrier layer 37, followed by a 20 nm AlGaAs buffer layer 39 doped n-type at 1 x 1018cam 3.

Next, above the latter structure, in turn are formed a 40 nm AlGaAs spacer layer 41, a 20 nm GaAs lower active layer 43, a 7nm AlGaAs intermediate barrier layer 45, a 20 nm GaAs upper active layer 47 and a 20 nm AlGaAs spacer layer 49. The structure is completed with a 40 nm AlGaAs buffer layer 51 n-type doped at 1 x 1018cm and finally, a 10 nm GaAs cap layer 53.

Turning now to Figure 3, there is shown a plot of the source/drain resistance as a function of the voltage (Vfg) applied to the front gate 11 for four different voltages Vbg applied to the back gate 25.

For Vbg = +1. 75V, the resistance falls from ca.

2. 6Kn to ca. 2. 3Kn at a threshold voltage of ca. Vfg = + 0. 12V. For Vbg = +1. 5V, the resistance falls from ca. 3Kn at ca. Vfg = + 0.06V. When Vbg = + 1.25V, the resistance falls from ca. 3.6 Kn to ca. 2. 7Kn at ca. Vfg = OV and for Vbg = + 1. 0V, from 4. 5Kn to ca. 3Kn. Thus ,it can be seen that changing the back gate voltage both adjusts the threshold voltage and the magnitude of change of resistance.

Figure 4 is a schematic diagram showing a second embodiment of a semiconductor device according to the present invention. The device of this embodiment is referred to here as a "resonant tunnelling switch" for reasons which will become apparent from the following description.

Although the layer structure of the device according to this second embodiment is not shown, the form of a suitable structure will be apparent to persons skilled in the art in the light of the description of the first embodiment of the invention. As in the first embodiment, there are two active layers separated by a thin barrier layer. An upper 61 and lower 63 2DEG are respectively induced in these upper and lower active layers.

The upper 2DEG 61 is divided into a first branch 65 and a second branch 67, e. g. by selective etching of the upper active layer to provide mutually isolated portions therein.

In use, the first branch 65 is in electrical connection between a source 69 and a first drain 71.

The second branch 67 is electrically isolated from the source 69, e.g. by means of a depletion gate as described for the first embodiment. However, the second branch is in electrical connection with a second drain 73. Thus, there is normally no electrical path through the second branch.

The lower 2DEG is not in electrical connection with either the source 69 or the first and second drains 71, 73 by virtue of depletion gate electrodes (not shown).

Overlying both branches 65, 67 of the upper 2DEG 61 and the lower 2DEG 63 is a control gate electrode 75.

In use, when a voltage is applied between the source 69, on the one hand, and first and second drains 71, 73 on the other hand, current can flow in the first branch 65 of the upper 2DEG 61. However, no current can flow in the right hand branch 67 because it is physically isolated from the left hand branch 65 and the source 69.

When a voltage applied to the control gate 75 is of a magnitude such as to equalize the carrier densities between the lower 2DEG 63 and upper 2DEG 61, then tunnelling can occur therebetween. Thus, carriers are exchanged between the upper and lower 2DEGs as denoted by the solid arrows 77. This enables current flowing in the left hand branch 65 of the upper 2DEG 61 from source 69 to be transferred via the lower 2DEG 63 to the right hand branch 67 of the upper 2DEG, to second drain 73.

In this way, the current flowing into second drain 73 is switched on and off by the control gate potential.

In the light of this disclosure, modifications of the described embodiments, as well as other embodiments, all within the scope of the present invention as defined by the appended claims will now be apparent to persons skilled in the art.

Claims (11)

Claims: -

1. A semiconductor device comprising a first active layer and a second active layer separated by a barrier layer, a source region and a drain region being mutually separated and each contacting at least one of said first and second active layers, and a gate electrode being arranged above the first and second active layers in a region between said source and drain regions, the barrier layer being sufficiently thin that in use, when a voltage applied to the gate electrode is of a magnitude to equalise substantially carrier densities in the first and second active layers, the electrical resistance across the source and drain regions is reduced.

2. A semiconductor device according to claim 1, also comprising a depletion gate electrode overlying said first and second active layers between said gate electrode and one of said source and drain regions, for application of a depletion potential to inhibit conduction in the active layer closest to said depletion gate electrode.

3. A semiconductor device according to claim 2, also comprising a further depletion gate electrode overlying said first and active layers between said gate electrode and the other of said source and drain regions.

4. A semiconductor device according to any preceding claim, wherein one of said first and second active layers is formed so that in use, it has a higher carrier mobility than the other.

5. A semiconductor device according to claim 4, wherein the active layer with the higher mobility is that closest to said gate electrode.

6. A semiconductor device according to any preceding claim, also comprising a back gate electrode overlying said first and second active layers on a side remote from said gate electrode, for modifying the gate threshold voltage of the device.

7. A semiconductor device according to any preceding claim, wherein one of said first and second active layers is divided into first and second branches.

8. A semiconductor device according to claim 7 wherein one of said first and second branches contacts said source and drain regions and the other branch contacts a further drain region, the magnitude of voltage applied to said gate electrode determining the switching on and off of the current flowing through said further drain region.

9. A semiconductor device according to any preceding claim, wherein the active layers are formed of GaAs and the barrier layer is formed of AlGaAs, the barrier layer having a thickness of 20 nm or less.

10. A semiconductor device according to claim 9, wherein the barrier layer has a thickness of 3 nm or more.

11. A semiconductor device substantially as hereinbefore described with reference to any of the accompanying drawings.