GB2281473A

GB2281473A - A method and apparatus for controlling power consumption in a telephone subset

Info

Publication number: GB2281473A
Application number: GB9417090A
Authority: GB
Inventors: Ronald Christopher Shaw Fox; Phil Leece; Raymond Michael Benham
Original assignee: Alcatel Australia Ltd
Current assignee: Nokia Services Ltd
Priority date: 1993-08-24
Filing date: 1994-08-24
Publication date: 1995-03-01
Anticipated expiration: 2014-08-24
Also published as: BE1009113A5; GB2281473B; GB9417090D0; NZ264200A

Abstract

Power consumption of a microprocessor, 13, controlled telephone subset is reduced in the off-line condition by sensing the off-line condition and switching the microprocessor to idle mode, and switching the ROM, 21, to a low energy consuming state when the microprocessor is in the idle mode. The microprocessor is programmed to be "woken up" by the operation of a key or the line switch, so that the microprocessor does not need to poll the keypad, 15. <IMAGE>

Description

A METHOD AND APPARATUS FOR CONTROLLING POWER CONSUMPTION IN A TELEPHONE SUBSET This invention relates to a current controlling circuit and more particularly to a method and apparatus for conserving power in a telephone subset.

Telephone utilities limit the amount of current that can be drawn by an inactive telephone connected to the phone line. In Australia this off line current is limited to SOiLA.

Modern telephones, particularly those which provide additional features, contain a microprocessor and electronic memories as well as other functional circuits which require some power in the off line mode. There is thus a problem in maintaining the standby current for these devices while not exceeding the permitted off line current.

The present invention seeks to provide a method and apparatus to reduce power consumption in a microprocessor controlled telephone subset in the on-hook mode.

According to one aspect of the invention, there is provided a method of controlling power consumption in a telephone subset including a microprocessor having at least an active state and a power down state wherein the microprocessor consumes less power in the power down state than in the active state, the method comprising detecting when the telephone is in an off-line condition and producing a first control signal to cause the microprocessor to be switched to the powered down state.

According to a further aspect of the invention, there is provided a telephone subset including a microprocessor switchable between at least an active state and a power down state by a first control signal, the subset including sensing means to detect whether or not the subset is in the off-line condition, the sensing means producing the first control signal to switch the microprocessor to the power down state when the subset is off-line.

In order that the invention and its various other features may be understood more easily, an embodiment thereof will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a block diagram representing functional elements of a telephone subset embodying the invention, and Figure 2 shows details of the control logic of Figure 1.

In Figure 1: 1. is a tone caller circuit; 13 is a microprocessor; 2. is a bridge rectifier; 13a is a watchdog Reset; 3. is a FET line switch; 14 is a keypad latch; 4. is a current source; 15 is a keypad; 5. is a line switch control circuit; 16 is a control logic device; 6. is the transmission circuit; 17 is a clock generator; 7. is the handsfree circuit; 18 is a display circuit; 8. is a facility tone detector; 19 is a LCD; 9. is a transistor switch; 20 is an EEPROM; 10 is a voltage regulator; 21 is a ROM; 11 is a transmission latch; 22 is a RAM; 12 is a DTMF generator; 23 is an 12C Bus; and 24 is an address/data bus.

A Capacitor C1 serves to store power for the subset when FET 3 is open circuit. A Zener diode Z1 limits the charge on Cl.

When the handset is ON-HOOK, the subset's hookswitch (not shown) causes the line switch control 5 to switch the line switch 3 to open circuit. In this condition the 45yA current source 4 provides a trickle current around the open line switch 3, and this trickle current is used to top up capacitor C1 via a current path through the line switch control circuit 5.

When the phone is first plugged in, all voltages within the phone are OV. The 45 yA current source is directed into the line switch control 5 to turn the FET line switch 3 on during cold start.

When the phone is on-hook, diode D1 stops capacitor C1 from powering the transmission circuit.

Capacitor C1 supplies a voltage of, eg. 8.2v, as determined by zener diode Z1, to voltage regulator 10 which provides a regulated supply of, eg. 3v, to processor 13 and the other devices attached to the output of regulator 10.

The microprocessor 13 may advantageously be a single chip 8 bit microcontroller as used in conjunction with the Philips 12C bus system as described in the Philips publication P83CL410 of September 1991. Pages 15 to 17 of this publication describe the idle and power down operation of the processor.

The microprocessor 13 in Figure 1 has three possible states each with a different current consumption: (1) operating mode drawing 2.5mA; (2) idle mode drawing l.OmA; and (3) power down mode drawing 1OyA.

When the subset is on-hook the microprocessor must primarily reside in the power down mode to ensure the current demand does not exceed the 504A allowable supply.

However the processor cannot spend all of its time in power down mode since certain on-hook subset features (updating the clock, keypad presses) require the processor to enter operating and idle modes briefly.

Such features consume current since they require microprocessor operation. A suitable arrangement of hardware and software ensures this onhook current demand is kept to a minimum.

The microprocessor switches between the three states of operating, idle, and power down by a combination of software commands and interrupts. The microprocessor has a register (not shown), which controls which state the microprocessor is in. If the microprocessor is in operating mode, and the zero'th bit the register is set, then the microprocessor will go into idle mode. If bit one of register is set while the microprocessor is in operating mode, then the microprocessor will go into power down mode. The microprocessor can be woken up from power down mode by either interrupts (keypad matrix elements are coupled to respective interrupt input pins (not shown) of the microprocessor, the clock is attached to a further interrupt input pin (not shown) of the microprocessor), or by a reset (generated by the hook-switch, clock, or when the phone first powers up).The microprocessor can be woken up from idle mode by either enabled interrupts, or by a reset.

As mentioned in the Philips publication the microprocessor's state is controlled by two bits of the register, (PD and IDL). The microprocessor will go into power down state by setting PD (bit 1 of the register).

This is the last instruction executed prior to going into the power down mode. The interrupt input pins from the keypad, and interrupt input pin from the clock causes the register to be cleared by hardware internal to the microprocessor, thus causing the microprocessor to be switched from power down mode to operating mode.

The processor also is switched from power down mode to operating mode by a reset, which is generated by the hookswitch transition from on hook to off hook, the clock, or when the phone first powers up.

A second device which uses a large amount of current is ROM 21. When the ROM 21 is being accessed it draws 8mA. While it is not being accessed it draws of the order of 10yea. The microprocessor 13 accesses ROM 21 when the microprocessor's program store enable PIN PSEN is low. However PSEN is low while the microprocessor is powered down. Thus ROM 21 would be selected when the microprocessor is powered down and draw excessive current. To avoid the ROM being selected during power down, control logic 16 shown in Figure 2 is interposed between microprocessor 13 and ROM 21.

Control logic 16 consists of NOR gates 31 and 32, transistor TR1, capacitor C2, and resistor Rl pin of microprocessor 13. The first input of gate 31 is connected to the PSEN and the second input of gate 31 is connected to the collector of transistor TR1 which is connected to the 3v supply via resistor R1. Capacitor C2 bridges the collector emitter path of transistor TR1.

The base of transistor TR1 is connected to the address latch enable (ALE) output pin of microprocessor 13.

ALE output serves to latch the low byte of the address during access to external memory, and is emitted at a constant rate of 1/6 of the oscillator frequency when the microprocessor is running. Thus when the microprocessor is active, ALE output is pulsing at about 600 kHz. If C2 is of the order of 30 YF and resistor R1 is of the order of 300 kQ, then the impedance of C2 is small compared with resistor R1 and the collector of transistor TR1 is at approximately Ov when the microprocessor 13 is running. Thus the output of gate 31 is PSEN, and the output of gate 32 is PSEN.

When microprocessor 13 is powered down, ALE. is low so the collector of transistor TRl is at 3v, while PSEN is low. Thus the output of gate 31 is low and the output of gate 32 is high. The output of gate 32, provides a logic signal CE to control access to ROM 21, ensuring that when microprocessor 13 is powered down, ROM 21 is not accessed and so draws less current.

In a further improvement, the microprocessor 13 is programmed to be switched from the power down state to the active state when any key of the keypad is pressed. This is achieved by connecting the keypad lines to the interrupt inputs of microprocessor 13. This obviates the necessity for the microprocessor 13 to continually poll the state of the keys, which would require the microprocessor to be active and draw excessive current.

The sequence of events for a key press is as follows. The microprocessor sets all outputs of the keypad latch high, then goes on to power down mode (in the case where the phone is off-line). If a key is pressed, then one of the interrupt inputs goes high, waking the microprocessor up. The microprocessor will then clear the keypad latch, then shift a high through the latch outputs. If only one key is pressed, then only one of the interrupt inputs will detect a high on one of the 8 pulses. This uniquely determines the key. (If more than one key is being pressed, then it is ignored). The outputs of the latch are then set high, the interrupts set to detect a negative edge, and the microprocessor goes back to sleep, waiting for the key to be released.

Claims

CLAIMS:

1. A method of controlling power consumption in a telephone subset including a microprocessor having at least an active state and a power down state wherein the microprocessor consumes less power in the power down state than in the active state, the method comprising detecting when the telephone is in an off-line condition and producing a first control signal to cause the microprocessor to be switched to the powered down state.

2. A method as claimed in claim 1, wherein the off-line condition is detected by sensing the condition of the hook-switch of the telephone.

3. A method as claimed in claim 1 or claim 2, wherein the telephone includes a ROM associated with the microprocessor, and wherein the ROM is switchable between a non-accessed state and an accessed state in which it consumes more power than in its non-accessed state under the control of a second control signal, wherein the second control signal enables the ROM to be switched to its accessed state when required by the microprocessor, the second control signal ensuring that the ROM is switched to its non-accessed state when the microprocessor is in its power down state.

4. A method as claimed in any one of claims 1 to 3 wherein the microprocessor is programmed to be in the power down state when the subset is off-line, and wherein the action of depressing a key of the keypad produces an interrupt signal which switches the microprocessor to the active state.

5. A method of controlling power consumption in a telephone subset substantially as herein described with reference to the accompanying drawings.

6. A telephone subset including a microprocessor switchable between at least an active state and a power down state by a first control signal, the subset including sensing means to detect whether or not the subset is in the off-line condition, the sensing means producing the first control signal to switch the microprocessor to the power down state when the subset is off-line.

7. A telephone subset as claimed in claim 6 wherein the sensing means includes the hook-switch of the subset.

8. A telephone subset as claimed in claim 6 or claim 7, including a ROM switchable by a second control signal between a non-accessed state and an accessed state which consumes more power than the non-accessed state, wherein the microprocessor generates a third control signal intended to switch the ROM to the accessed state by changing to a binary low voltage level, wherein the subset includes a control signal to which the third control signal and a fourth control signal from the microprocessor are applied, wherein the fourth control signal indicates that the microprocessor is in the active state, the logic circuit causing the second control signal to be in the binary high voltage level when the microprocessor is in the power down state.

9. A subset as claimed in claim 8 wherein the control signal includes a first NOR gate to a first input of which the third control signal is applied, inverter means to which the fourth control signal is applied, the output of the inverter means being applied to the second input of the first NOR gate, the output of the first NOR gate being applied to a first input of a second NOR gate, the second input of the second NOR gate being held at the binary low voltage logic level.

10. A subset as claimed in claim 9 wherein the inverter means includes a transistor whose collector-emitter path is connected between the high and low binary logic levels via a first resistor, the junction between the first resistor and the collector-emitter path forming the output of the inverter means.

11. A telephone subset substantially as herein described with reference to the accompanying drawings.

11. A subset as claimed in claim 10 wherein the fourth control signal is a binary pulse stream and wherein a capacitor bridges the collector-emitter path.

12. A subset as claimed in any one of the preceding claims wherein the keypad output is connected to interrupt inputs of the microprocessor to switch the microprocessor to the active state when a key is pressed.

13. A telephone subset substantially as herein described with reference to the accompanying drawings.

Amendments to the claims have been filed as follows

1. A method of controlling power consumption in a telephone subset including a microprocessor having at least an active state and a power down state wherein the microprocessor consumes less power in the power down state than in the active state, the method comprising detecting when the telephone is in an off-line condition and producing a first control signal to cause the microprocessor to be switched to the powered down state, and wherein the telephone includes a ROM associated with the microprocessor, and wherein the ROM is switchable between a non-accessed state and an accessed state in which it consumes more power than in its non-accessed state under the control of a second control signal, wherein the second control signal enables the ROM to be switched to its accessed state when required by the microprocessor, the second control signal ensuring that the ROM is switched to its non-accessed state when the microprocessor is in its power down state.

3. A method as claimed in claim 1 or claim 2, wherein the microprocessor is programmed to be in the power down state when the subset is off-line, and wherein the action of depressing a key of the keypad produces an interrupt signal which switches the microprocessor to the active state.

4. A method of controlling power consumption in a telephone subset substantially as herein described with reference to the accompanying drawings.

5. A telephone subset including a microprocessor switchable between at least an active state and a power down state by a first control signal, the subset including sensing means to detect whether or not the subset is in the off-line condition, the sensing means producing the first control signal to switch the microprocessor to the power down state when the subset is off-line, the telephone subset including a ROM switchable by a second control signal between a nonaccessed state and an accessed state which consumes more power than the non-accessed state, wherein the microprocessor generates a third control signal intended to switch the ROM to the accessed state by changing to a binary low voltage level, wherein the subset includes a logic circuit to which the third control signal and a fourth control signal from the microprocessor are applied, wherein the fourth control signal indicates that the microprocessor is in the active state, the logic circuit causing the second control signal to be in the binary high voltage level when the microprocessor is in the power down state.

6. A telephone subset as claimed in claim 5, wherein the sensing means includes the hook-switch of the subset.

7. A subset as claimed in claim 5 or claim 6, wherein the logic circuit includes a first NOR gate to a first input of which the third control signal is applied, inverter means to which the fourth control signal is applied, the output of the inverter means being applied to the second input of the first NOR gate, the output of the first NOR gate being applied to a first input of a second NOR gate, the second input of the second NOR gate being held at the binary low voltage logic level.

8. A subset as claimed in claim 7, wherein the inverter means includes a transistor whose collectoremitter path is connected between the high and low binary logic levels via a first resistor, the junction between the first resistor and the collector-emitter path forming the output of the inverter means.

9. A subset as claimed in claim 8, wherein the fourth control signal is a binary pulse stream and wherein a capacitor bridges the collector-emitter path.

10. A subset as claimed in any one of claims 5 to 9, wherein a keypad output is connected to interrupt inputs. of the microprocessor to switch the microprocessor to the active state when a key is pressed.