GB2275851A - A combined digital video/audio synchroniser - Google Patents
A combined digital video/audio synchroniser Download PDFInfo
- Publication number
- GB2275851A GB2275851A GB9304587A GB9304587A GB2275851A GB 2275851 A GB2275851 A GB 2275851A GB 9304587 A GB9304587 A GB 9304587A GB 9304587 A GB9304587 A GB 9304587A GB 2275851 A GB2275851 A GB 2275851A
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- samples
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- frame
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/132—Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/587—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/93—Regeneration of the television signal or of selected parts thereof
- H04N5/95—Time-base error compensation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/24—Systems for the transmission of television signals using pulse code modulation
- H04N7/52—Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal
- H04N7/54—Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal the signals being synchronous
- H04N7/56—Synchronising systems therefor
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
- H04N9/802—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving processing of the sound signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/915—Television signal processing therefor for field- or frame-skip recording or reproducing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/92—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
- H04N5/926—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback by pulse code modulation
- H04N5/9265—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback by pulse code modulation with processing of the sound signal
- H04N5/9267—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback by pulse code modulation with processing of the sound signal using time division multiplex of the PCM audio and PCM video signals
- H04N5/9268—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback by pulse code modulation with processing of the sound signal using time division multiplex of the PCM audio and PCM video signals with insertion of the PCM audio signals in the vertical blanking interval of the PCM video signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/93—Regeneration of the television signal or of selected parts thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/93—Regeneration of the television signal or of selected parts thereof
- H04N5/94—Signal drop-out compensation
- H04N5/945—Signal drop-out compensation for signals recorded by pulse code modulation
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Systems (AREA)
Abstract
A data synchroniser 1 used to synchronise an incoming video/audio signal SDI with a reference clock SPG is adapted for operation with a signal in which the numbers of audio samples in a sequence of fields differ to accommodate the fact that the number of audio samples per field is not an integer. During a resynchronisation operation in which a frame is dropped or repeated, the frame is selected in such a manner as to ensure that the number of audio samples in each outputted sequence of fields is constant, Figs. 3a, 3b, (not shown). The synchroniser operates with both 625 line 50Hz and 525 line 59.94Hz video systems. <IMAGE>
Description
A COMBINED DIGITAL VIDEO/AUDIO SYNCHRONISER
The present invention relates to a combined digital video/audio synchroniser and a method of synchronization.
A synchroniser may be used to phase and frequency lock two independent video/audio programme sources having the audio data embedded in the horizontal/vertical timing intervals of the video signal. The independent sources, although being of nominally the same frequency, have an arbitrary phase relationship which is subject to continual change. This results in the synchroniser memory being filled up faster than it can be emptied or vice versa until it becomes necessary for information to be dropped or repeated so as to realign the sources, resynchronise the data from the synchronise memory, by adjusting the read address. This information may be dropped or repeated as whole frames each comprising two video fields.
In a combined digital video and digital audio synchroniser having a Serial Digital Interface (SDI), the audio data may be embedded in the horizontal and vertical timing interval of the video signal. A device of this type may treat the audio and video information as a single entity thus providing a "DATA" synchroniser. The advantages of this arrangement are that perfect "lip-sync" between the video and audio is maintained and no audio signal degradation occurs in the synchroniser during normal operation.
With 525-line 59.94Hz systems which use 48KHz audio sampling, a problem arises from the fact that there is a non-integral number of audio samples per field of the video signal. This requires that when the audio and video samples are combined, the same number of audio samples cannot be interleaved with each field, and instead, over a sequence of fields, (five with 525 line, 59.94Hz systems with 48KHz sampling) that does correspond with a whole number of audio samples, different number of audio samples are interleaved with the video data to make up the total.
This, however, presents a problem in operation of the synchroniser, namely that the pattern of numbers of audio samples from the synchroniser output in a field sequence which is in progress when a resynchronisation operation occurs may not be correct.
According to the present invention, there is provided a synchroniser for a combined video and audio signal, which is in a format in which blocks of audio sample data are time-interleaved with the samples of successive fields of video sample data in a repeating sequence of numbers of audio samples per field of video samples, such that the number of audio samples in at least one of the fields of the sequence differ from that in the remainder of the fields of the sequence and that, prior to passage through the synchroniser, the total number of audio samples in each sequence is constant, comprising::
a) a memory buffer having a capacity for storing at least two frames' worth of video and audio samples;
b) write- and read-control circuits for writing incoming video/audio data sample to the memory buffer and reading the buffered data therefrom at rates which are respectively synchronised in frequency and phase with the incoming data and with a reference clock signal;
c) resynchronising means for resynchronising the data read from the buffer by adjusting the sequence of read and/or write addresses used for reading and/or writing data from and to the memory buffer to avoid overflow or underflow of the buffer contents, so selectively repeating or dropping frames of the stored data; wherein
d) the resynchronising means is operative, when resynchronisation is required, to select the timing of the resynchronisation operation and adjustment of the read address, and thereby the frame to be repeated or dropped, such that the total number of audio samples in the sequence of fields being read from the memory buffer when the resynchronisation is carried out is unchanged.
Preferably when a resynchronisation operation is carried out, the read address is adjusted by an amount corresponding to an integral number of frames' worth of data stored in the memory buffer.
Preferably, where a frame is to be dropped, the frame selected for dropping is one having a total number of samples which is equal to the total number of samples in the first two fields of the sequence and where a frame is repeated, the frame to be repeated is one having a total number of samples which is equal to the total number of samples in the last two fields of the sequence.
Preferably the sequence inputted to the synchroniser has a first field of a first predetermined number of audio samples, a second field of a second predetermined number of audio samples and a last field of said second predetermined number of audio samples and when a resynchronisation operation is required, if a frame is to be dropped, the frame selected for dropping is one which comprises both a field of said first number of samples and a field of said second number of samples and, if a frame is to be repeated, the frame selected for repeating comprises two fields of said second number of audio samples.
Preferably the apparatus is adapted for use with a signal in which said sequence comprises a field of 800 samples and 4 fields of 801 samples, per channel of audio.
Typically, there may be up to four channels of audio in the signal.
The invention will be more clearly understood from the following description given by way of example only with reference to the accompanying drawings in which:
Figure 1 illustrates a block diagram of a synchroniser according to an embodiment of the present invention.
Figure 2(a) and (b) illustrate a frame sequence before and after a frame is respectively dropped or repeated according to a previous arrangement.
Figures 3(a) and (b) illustrate a frame sequence before and after a frame is respectively dropped or repeated, according to the embodiment of Figure 1.
Figure 1 illustrates in block diagram form synchronizer 1 to which, for instance, a signal from a video source may be input for synchronization with other signals which are to be broadcast from a main transmitter.
In this embodiment, the input signal, in the form of a serial video/audio data bit stream is inputted to the serial to parallel converter 2 and resulting parallel video/audio data, eg. 10 bit video/audio data at 27M samples/sec, is transferred to a 2-frame memory 3 under the control of the write control circuit 4 which derives from the serial to parallel converter 2 a write clock signal which clocks the writing of data to the 2-frame memory 3.
The 2-frame memory 3 acts as a circular buffer from which the stored data may be read out at a different rate from that at which it is written.
A reference signal synchronised with the horizontal and vertical synchronizing signals of the signal with which the input signal is to be synchronised, is input from a signal pulse generator (SPG) 5 to a read control circuit 6. The read control circuit 6 provides a read clock signal to the 2-trame memory 3 so as to control the rate at which data is read from the 2-frame memory and this data can then pass to the parallel to serial converter 7 for reconversion to a 270 Mbit/second bit serial stream output from the synchroniser.
A system control circuit 8 is also provided which accepts external control signals to control the synchroniser and controls the operation of the other elements of the synchroniser.
As discussed above, at some point in the normal operation of the combined digital video/audio synchroniser, it will become necessary to drop or repeat information to maintain synchronisation. This is due to the limited size of data storage inside the synchroniser and its inability to indefinitely buffer the continually changing phase relationship between input and output signals.
With 625 line 50Hz video systems, the audio sample rate of 48KHz when locked to a video reference, produces an integer number of audio samples per frame (1920 samples).
When the synchroniser drops or repeats frames of information, an integer number of audio samples will be effected by the frame disturbance.
However, because the field rate of the 525 line system is not exactly 60Hz, but 59.94Hz, there will not be an integer number of 48KHz audio samples in a frame period, but 1601.6 samples.
Assuming the audio sample rate is locked to the video reference, when audio sample data is time compressed to fit in the horizontal timing interval of the video signal for the SDI, a five field audio sample sequence is produced.
Over five fields of 59.94Hz video there will be an integer number of 48KHz audio samples (4004). These samples are preferably distributed within the SDI such that, for each audio channel, there is one field containing 800 samples followed by four fields of 801 samples each and this sequence is illustrated in Figures 2 and 3.
However, when the synchroniser drops or repeats information, if the synchroniser were not operated according to the present invention it would be possible to disturb this five field sequence so that a sequence of 4003 audio samples is produced.
For instance, referring to Figure 2(a), if frame 5 is dropped, frame 6 replaces it in its block thereby creating a block of only 4003 audio samples rather than the usual 4004. Similarly, referring to Figure 2(b), repetition of frame 6 will result in a block of 4003 samples. As discussed above, this can give rise to unacceptable disturbances in the audio signal. More particularly, when the audio data is separated from the SDI and time expanded as may be required prior to transmission or recording, a sequence of 4003 samples will result in single sample audio disturbance and the risk of propagating errors into downstream equipment.
In the preferred embodiment of the present invention as illustrated in Figure 1, the system control circuit 8 is arranged to control the read control circuit 6 so as to drop or repeat a frame in such a manner as to maintain the block of five fields at 4004 samples.
Referring to Figure 3(a), if frame 6 is dropped, it will be noted that the resulting block is still of 4004 samples. Thus, in the example of the 4004 sample sequence, when the synchroniser must drop a frame of information, if a frame boundary containing one field of 800 samples, plus one field of 801 samples is dropped, then the 4004 samples five field sequence is maintained.
Similarly from Figure 3(b) if frame 5 is repeated, the resulting block is of 4004 samples and thus when the synchroniser must repeat a frame of information, choosing a frame boundary that contains two fields of 801 samples each will similarly preserve the sample count.
In accordance with the invention, the system controller 8 selects which frame to drop or to repeat when performing a resynchronising operation, so as to maintain the number of output audio samples in each five field sequence of blocks constant at 4004. Repeating a frame effectively retards the incoming sequence by two fields whereas dropping a frame effectively advances the incoming sequence by two fields. In order to maintain the value 4004, therefore, the frame to be repeated is selected by the system controller 8 to be one which has the same number of audio samples as the last two fields in a sequence, whereas the frame which is selected for dropping has a total number of audio samples equal to that in the first two fields of the sequence.
In view of the above, by the particular choice of frame boundaries used during resynchronisation, the synchronizer may drop or repeat a frame without disrupting the 4004 audio sample sequence.
It is therefore possible to ensure that the five field digital audio sample sequence can be maintained in a combined digital video/audio synchroniser, when operating with 525 line 59.94Hz video signals.
This allows such a "DATA" synchroniser to operate with both 625 50Hz and 525 59.94Hz video systems having a
Serial Digital Interface (SDI), in which both video and audio data are combined.
It should be noted that the invention is not limited to interlaced TV signals, but is also applicable to non-interlaced TV signals. As applied to non-interlaced TV signals, the term "field" as used herein is intended to be synonymous with "frame".
Claims (6)
1. A synchroniser for a combined video and audio signal, which is in a format in which blocks of audio sample data are time-interleaved with the samples of successive fields of video sample data in a repeating sequence of numbers of audio samples per field of video samples, such that the number of audio samples in at least one of the fields of the sequence differ from that in the remainder of the fields of the sequence and that, prior to passage through the synchroniser, the total number of audio samples in each sequence is constant, comprising::
a) a memory buffer having a capacity for storing at least two frames' worth of video and audio samples;
b) write- and read-control circuits for writing incoming video/audio data sample to the memory buffer and reading the buffered data therefrom at rates which are respectively synchronised in frequency and phase with the incoming data and with a reference clock signal;
c) resynchronising means for resynchronising the data read from the buffer by adjusting the sequence of read and/or write addresses used for reading and/or writing data from and to the memory buffer to avoid overflow or underflow of the buffer contents, so selectively repeating or dropping frames of the stored data; wherein
d) the resynchronising means is operative, when resynchronisation is required, to select the timing of the resynchronisation operation and adjustment of the read address, and thereby the frame to be repeated or dropped, such that the total number of audio samples in the sequence of fields being read from the memory buffer when the resynchronisation is carried out is unchanged.
2. A synchroniser according to claim 1 in which, when a resynchronisation operation is carried out, the read address is adjusted by an amount corresponding to an integral number of frames' worth of data stored in the memory buffer.
3. A synchroniser according to claim 1 or 2, wherein when a frame is required to be dropped, the resynchronising means is operative to select for dropping a frame having a total number of samples which is equal to the total number of samples in the first two fields of a sequence and when a frame is required to be repeated, the resynchronising means is operative to select for repeating a frame having a total number of samples which is equal to the total number of samples in the last two fields of a sequence.
4. An synchroniser according to any one of claims 1 to 3, wherein a first field of the sequence has a first predetermined number of samples, a second field of the sequence has a second predetermined number of samples and a last field of said second predetermined number of samples and wherein, the resynchronising means is operative such that when a frame is required to be dropped, the frame selected for dropping is one which comprises both a field of said first number of samples and a field of said second number of samples and, when a frame is required to be repeated, the frame selected for repetition is one which comprises two fields of said second number of audio samples.
5. A synchroniser according to any one of the preceding claims, wherein the number of fields in a sequence is five, four fields of the sequence having 801 audio samples and one having 800 samples.
6. A synchroniser constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9304587A GB2275851B (en) | 1993-03-05 | 1993-03-05 | A combined digital video/audio synchroniser |
| JP3603294A JPH0898158A (en) | 1993-03-05 | 1994-03-07 | Coupling image-voice synchronizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9304587A GB2275851B (en) | 1993-03-05 | 1993-03-05 | A combined digital video/audio synchroniser |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9304587D0 GB9304587D0 (en) | 1993-04-21 |
| GB2275851A true GB2275851A (en) | 1994-09-07 |
| GB2275851B GB2275851B (en) | 1997-02-26 |
Family
ID=10731578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9304587A Expired - Fee Related GB2275851B (en) | 1993-03-05 | 1993-03-05 | A combined digital video/audio synchroniser |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0898158A (en) |
| GB (1) | GB2275851B (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2300055A (en) * | 1995-04-15 | 1996-10-23 | Samsung Electronics Co Ltd | Recording apparatus for IC memory card |
| EP0777383A1 (en) * | 1995-06-19 | 1997-06-04 | Sony Corporation | Data communication device |
| US6631429B2 (en) * | 1999-12-23 | 2003-10-07 | Intel Corporation | Real-time processing of a synchronous or isochronous data stream in the presence of gaps in the data stream due to queue underflow or overflow |
| WO2004095460A3 (en) * | 2003-03-28 | 2007-10-11 | Grass Valley Us Inc | Asynchronous jitter reduction technique |
| WO2012044434A1 (en) * | 2010-09-30 | 2012-04-05 | Apple Inc. | Overflow control techniques for image signal processing |
| US8643859B2 (en) | 2010-09-30 | 2014-02-04 | Samsung Electronics Co., Ltd. | Image forming apparatus and control method thereof |
| US8817120B2 (en) | 2012-05-31 | 2014-08-26 | Apple Inc. | Systems and methods for collecting fixed pattern noise statistics of image data |
| US8872946B2 (en) | 2012-05-31 | 2014-10-28 | Apple Inc. | Systems and methods for raw image processing |
| US8917336B2 (en) | 2012-05-31 | 2014-12-23 | Apple Inc. | Image signal processing involving geometric distortion correction |
| US8953882B2 (en) | 2012-05-31 | 2015-02-10 | Apple Inc. | Systems and methods for determining noise statistics of image data |
| US9014504B2 (en) | 2012-05-31 | 2015-04-21 | Apple Inc. | Systems and methods for highlight recovery in an image signal processor |
| US9025867B2 (en) | 2012-05-31 | 2015-05-05 | Apple Inc. | Systems and methods for YCC image processing |
| US9031319B2 (en) | 2012-05-31 | 2015-05-12 | Apple Inc. | Systems and methods for luma sharpening |
| US9077943B2 (en) | 2012-05-31 | 2015-07-07 | Apple Inc. | Local image statistics collection |
| US9105078B2 (en) | 2012-05-31 | 2015-08-11 | Apple Inc. | Systems and methods for local tone mapping |
| US9131196B2 (en) | 2012-05-31 | 2015-09-08 | Apple Inc. | Systems and methods for defective pixel correction with neighboring pixels |
| US9142012B2 (en) | 2012-05-31 | 2015-09-22 | Apple Inc. | Systems and methods for chroma noise reduction |
| US9332239B2 (en) | 2012-05-31 | 2016-05-03 | Apple Inc. | Systems and methods for RGB image processing |
| US11089247B2 (en) | 2012-05-31 | 2021-08-10 | Apple Inc. | Systems and method for reducing fixed pattern noise in image data |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111432258B (en) * | 2019-04-29 | 2022-09-30 | 杭州海康威视数字技术股份有限公司 | Audio and video signal synchronization method and device |
| CN114554027B (en) * | 2022-03-16 | 2022-11-25 | 湖南双菱电子科技有限公司 | Audio embedding processing and video-audio synchronous output processing method |
-
1993
- 1993-03-05 GB GB9304587A patent/GB2275851B/en not_active Expired - Fee Related
-
1994
- 1994-03-07 JP JP3603294A patent/JPH0898158A/en active Pending
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2300055A (en) * | 1995-04-15 | 1996-10-23 | Samsung Electronics Co Ltd | Recording apparatus for IC memory card |
| GB2300055B (en) * | 1995-04-15 | 1997-11-05 | Samsung Electronics Co Ltd | Recording apparatus for integrated circuit card |
| EP0777383A1 (en) * | 1995-06-19 | 1997-06-04 | Sony Corporation | Data communication device |
| EP0777383A4 (en) * | 1995-06-19 | 2003-07-16 | Sony Corp | Data communication device |
| US6631429B2 (en) * | 1999-12-23 | 2003-10-07 | Intel Corporation | Real-time processing of a synchronous or isochronous data stream in the presence of gaps in the data stream due to queue underflow or overflow |
| WO2004095460A3 (en) * | 2003-03-28 | 2007-10-11 | Grass Valley Us Inc | Asynchronous jitter reduction technique |
| US7496728B2 (en) | 2003-03-28 | 2009-02-24 | Grass Valley (U.S.) Inc. | Asynchronous jitter reduction technique |
| WO2012044434A1 (en) * | 2010-09-30 | 2012-04-05 | Apple Inc. | Overflow control techniques for image signal processing |
| US8629913B2 (en) | 2010-09-30 | 2014-01-14 | Apple Inc. | Overflow control techniques for image signal processing |
| US8643859B2 (en) | 2010-09-30 | 2014-02-04 | Samsung Electronics Co., Ltd. | Image forming apparatus and control method thereof |
| US9014504B2 (en) | 2012-05-31 | 2015-04-21 | Apple Inc. | Systems and methods for highlight recovery in an image signal processor |
| US9131196B2 (en) | 2012-05-31 | 2015-09-08 | Apple Inc. | Systems and methods for defective pixel correction with neighboring pixels |
| US8917336B2 (en) | 2012-05-31 | 2014-12-23 | Apple Inc. | Image signal processing involving geometric distortion correction |
| US8953882B2 (en) | 2012-05-31 | 2015-02-10 | Apple Inc. | Systems and methods for determining noise statistics of image data |
| US8817120B2 (en) | 2012-05-31 | 2014-08-26 | Apple Inc. | Systems and methods for collecting fixed pattern noise statistics of image data |
| US9025867B2 (en) | 2012-05-31 | 2015-05-05 | Apple Inc. | Systems and methods for YCC image processing |
| US9031319B2 (en) | 2012-05-31 | 2015-05-12 | Apple Inc. | Systems and methods for luma sharpening |
| US9077943B2 (en) | 2012-05-31 | 2015-07-07 | Apple Inc. | Local image statistics collection |
| US9105078B2 (en) | 2012-05-31 | 2015-08-11 | Apple Inc. | Systems and methods for local tone mapping |
| US8872946B2 (en) | 2012-05-31 | 2014-10-28 | Apple Inc. | Systems and methods for raw image processing |
| US9142012B2 (en) | 2012-05-31 | 2015-09-22 | Apple Inc. | Systems and methods for chroma noise reduction |
| US9317930B2 (en) | 2012-05-31 | 2016-04-19 | Apple Inc. | Systems and methods for statistics collection using pixel mask |
| US9332239B2 (en) | 2012-05-31 | 2016-05-03 | Apple Inc. | Systems and methods for RGB image processing |
| US9342858B2 (en) | 2012-05-31 | 2016-05-17 | Apple Inc. | Systems and methods for statistics collection using clipped pixel tracking |
| US9710896B2 (en) | 2012-05-31 | 2017-07-18 | Apple Inc. | Systems and methods for chroma noise reduction |
| US9743057B2 (en) | 2012-05-31 | 2017-08-22 | Apple Inc. | Systems and methods for lens shading correction |
| US9741099B2 (en) | 2012-05-31 | 2017-08-22 | Apple Inc. | Systems and methods for local tone mapping |
| US11089247B2 (en) | 2012-05-31 | 2021-08-10 | Apple Inc. | Systems and method for reducing fixed pattern noise in image data |
| US11689826B2 (en) | 2012-05-31 | 2023-06-27 | Apple Inc. | Systems and method for reducing fixed pattern noise in image data |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9304587D0 (en) | 1993-04-21 |
| GB2275851B (en) | 1997-02-26 |
| JPH0898158A (en) | 1996-04-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 730A | Proceeding under section 30 patents act 1977 | ||
| 730A | Proceeding under section 30 patents act 1977 | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20110305 |