GB2275570A - Diffusion barriers for FET connections - Google Patents
Diffusion barriers for FET connections Download PDFInfo
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- GB2275570A GB2275570A GB9313120A GB9313120A GB2275570A GB 2275570 A GB2275570 A GB 2275570A GB 9313120 A GB9313120 A GB 9313120A GB 9313120 A GB9313120 A GB 9313120A GB 2275570 A GB2275570 A GB 2275570A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53247—Noble-metal alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A field effect transistor includes source and drain electrodes (3a, 3b) disposed on a semiconductor substrate (1), a flat insulating film (4) disposed on the substrate (1) and having contact holes (4a, 4b) which are positioned on the source and drain electrodes (3a, 3b) and filled with metal films (7a, 7b), barrier metal layers (8a, 8b) disposed on the metal films (7a, 7b) covering the interfaces between the metal films (7a, 7b) and the insulating film (4), and source and drain wiring layers (9a, 9b) disposed on the barrier metal layers (8a, 8b). Impurity diffusion between the source (drain) electrode and the electrode wiring layer is effectively prevented by the barrier metal layer. In addition, since the interface between the metal film buried in the contact hole and the insulating film, is covered with the barrier metal layer, the mutual impurity diffusion between the electrode and the wiring layer along the interface is prevented by the barrier metal layer. <IMAGE>
Description
SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to a structure for connecting source and drain electrodes to source and drain wiring layers. The invention also relates to a method for forming the wiring layers.
RACKGROUND OF THE INVENTION Figure 5(a) is a sectional view illustrating a prior art field effect transistor (hereinafter referred to as
FET), in which barrier metal layers are inserted between source and drain electrodes and source and drain wiring layers. This structure is disclosed in, for example, "A
High-Speed 16-kb GaAs SRAM of Less than 5 ns Using Triple
Level Metal Interconnection", IEEE TRANSACTIONS ON ELECTRON
DEVICES Vol.39 (1992) p. 494.
In the figure, reference numeral 120 designates an FET fabricated on a GaAs substrate 1. Source and drain electrodes 3a and 3b comprising an alloy of AuGe-Ni-Au are disposed on the GaAs substrate 1 spaced apart from each other. A Schottky gate metal 21, such as tungsten silicide (WSi), is disposed on a prescribed part of the GaAs substrate 1 between the source and drain electrodes.
An SiO2 film 2 (first insulating film) is disposed on the GaAs substrate 1 where the gate, source, and drain electrodes are absent. An SiO2 film 4 (second insulating film) is disposed on the first insulating film 2 and on portions of the source and drain electrodes 3a and 3b.
Contact holes 4a and 4b penetrate through the second insulating film 4 at positions opposite the source electrode 3a and the drain electrode 3b, respectively. Barrier metal layers 18a and 18b comprising tungsten silicide nitride (WSiN) or the like are disposed in the contact holes 4a and -4b, respectively, extending on the second insulating film 4 in the vicinity of the contact holes. Source and drain wiring layers 19a and 19b comprising Al, Cu, or the like are disposed on the barrier metal layers 18a and 18b, respectively.
A contact hole 4c penetrates through portions of the insulating films 2 and 4 opposite the Schottky gate metal 21. A gate wiring layer 23 comprising Al or Cu is disposed on the Schottky gate metal 21 via a barrier metal layer 8c.
Relatively high dopant concentration n type source and drain regions lia and lib are disposed within the GaAs substrate 1 lying under the source and drain electrodes 3a and 3b, respectively. An n type channel region 13 is disposed within the GaAs substrate 1 lying under the
Schottky gate metal 21. Relatively low dopant concentration n type regions 12a and 12b are disposed between the active region 13 and the respective source and drain regions lia and llb.
In the conventional compound semiconductor FET, the activation rate of dopant in the compound semiconductor is low and even if an n type dopant is heavily doped into the compound semiconductor, for example, GaAs, only 1018 carriers per cm3 are produced. Therefore, when the source and drain electrodes are formed on the compound semiconductor substrate, in order to achieve a reliable low resistance ohmic contact between the substrate and the source and drain electrodes, the following steps are carried out. That is, after heavily doping the dopant into regions in the substrate to be the source and drain regions and activating the doped regions by annealing, AuGe, Ni, and Au are successively deposited on the substrate and annealed at 400"C to alloy the laminated AuGe/Ni/Au films, which annealing step is called sintering.
However, since the resistance of metal is usually reduced when it is alloyed, the source and drain electrodes comprising the AuGe-Ni-Au alloy are significantly damaged by heat.
When the wiring layers are directly disposed on the source and drain electrodes as shown in figure 5(a), the mutual diffusion of impurities between the source and drain electrodes and their wiring layers unfavorably increases the resistances at the contact parts. Particularly when the wiring layers comprise aluminum or copper, the aluminum or copper unfavorably makes an ohmic contact with gold included in the source and drain electrodes, significantly increasing the contact resistances.
This problem may be solved if a refractory material including no gold is employed for the source and drain electrodes, but no material satisfying these conditions and suitable for mass-production has been discovered yet.
For the present, the barrier metal layers for preventing the mutual impurity diffusion are inserted between the source and drain electrodes and their wiring layers to reduce the deterioration at the interfaces between the electrodes and the wiring layers.
Figures 6(a)-6(d) illustrate process steps for producing the wiring layers on the source and drain electrodes via the barrier metal layers. Since the process steps are carried out symmetrically with respect to the source side and the drain side of the FET, only a part of the FET on the source side is shown in figures 6(a)-6(d) for simplification. In addition, the impurity diffused regions within the substrate are omitted.
Initially, an SiO2 film 2 is deposited over the surface of the GaAs substrate 1 to a thickness of about 2000 A and patterned to form an opening opposite a prescribed region where the source electrode is to be formed. Thereafter, a metal is deposited using the first SiO2 film 2 as a mask, and the SiO2 film 2 and the overlying portions of the metal are removed by lift-off, forming the source electrode 3a.
After depositing an SiO2 film 4 over the surface to a thickness of 4000 to 8000 A, a photoresist is deposited on the SiO2 film 4 and patterned to form a first photoresist pattern 25 having openings 25a opposite the source electrode 3a (figure 6(a)).
Using the photoresist pattern 25 as a mask, the SiO2 film 4 is etched by a reactive ion etching using a gas mixture of CHF3 and 02, forming the contact hole 4a on the source electrode 3a (figure 6(b)).
After removing the photoresist pattern 25 using 02 ash or organic solvent (figure 6(c)), WSi is deposited over the surface to form the barrier metal layer 18, and a low resistance metal 19, such as Au or Cu, is deposited on the barrier metal layer 18 (figure 6(d)). Finally, the barrier metal layer 18 and the low resistance metal layer 19 are patterned to form the source wiring layer l9a.
In the above-described process steps, however, since the barrier metal layer 18 is deposited on two different levels, i.e., on the source electrode 3a in the contact hole 4a and on the SiO2 insulating film 4, the coverage of the barrier metal layer 18 in the contact hole is poor. As shown in figure 5(b), the quality of the barrier metal layer 18 deteriorates particularly at the corner C of the contact hole 4a, and the barrier metal layer 18 at the corner C does not effectively prevent the mutual impurity diffusion between the source electrode 3a and the wiring layer 19a.
Figure 7(a) is a sectional view illustrating an electrode structure disclosed in Japanese Published Patent
Application No. 2-90610, in which an electrode wiring layer 209 is disposed on a prescribed region of a semiconductor substrate 201 via a barrier metal layer 208 that prevents the mutual diffusion of components between the electrode wiring layer 209 and the semiconductor substrate 201. A field oxide film 202 is disposed on the substrate 201 where the barrier metal layer 208 is absent. An insulating film 204 is disposed on the field oxide films 202 and on portions of the barrier metal layer 208. A contact hole 204a penetrates through the insulating film -204 to expose a portion of the barrier metal layer 208.
In the structure of figure 7(a), since the barrier metal layer 208 is disposed beneath the contact hole 204a of the insulating film 204, the above-described problem, i.e., the poor coverage of the barrier metal layer in the contact hole, is avoided. However, when the contact hole 204a is formed by selectively etching the insulating film 204 as shown in figure 7(b), it is necessary to select an etching method and an etchant that do not etch the barrier metal layer 208, whereby the production process is restricted.
Figure 8 is a sectional view illustrating a semiconductor device disclosed in Japanese Published Patent
Application No. 63-283161, in which a wiring layer 309 is electrically connected to a semiconductor substrate 301 via a contact hole 304a which penetrates through an insulating film 304 disposed on an impurity diffused region 311 in the semiconductor substrate 301. In this prior art, the contact hole 304a is filled with an electrode layer 307 to even the surface of the insulating film 304, whereby the coverage of the wiring layer 309 in the contact hole 304 is improved.
Further, a barrier metal layer 308 is disposed between the electrode layer 307 and the wiring layer 309 to avoid an increase in resistance due to deposition of silicon at the interface between the electrode layer 307 and the wiring layer 309.
In the structure of figure 8, however, since the barrier metal layer 308 and the electrode layer 307 are buried in the contact hole 304a, components of the electrode layer 307 and the wiring layer 309 are mutually diffused along the interface between the side surface of the barrier metal layer 308 and the internal side surface of the contact hole 304a, which means that the mutual impurity diffusion is not effectively prevented by the barrier metal layer 308.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device including barrier metal layers inserted between source and drain electrodes and source and drain electrode wiring layers, respectively, which barrier metal layers effectively prevent the mutual impurity diffusion between the electrodes and the wiring layers.
It is another object of the present invention to provide a relatively simple method for producing the source and drain electrodes, the barrier metal layers, and the wiring layers with no restriction on the production process.
Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
According to a first aspect of the present invention, a semiconductor device includes source and drain electrodes disposed on a semiconductor substrate apart from each other, a flat insulating film disposed on the substrate and having contact holes which are positioned on the source and drain electrodes and filled with metal films, barrier metal layers disposed on the metal films covering the interfaces between the metal films and the insulating film, and source and drain wiring layers disposed on the barrier metal layers.
Therefore, the quality of the barrier metal layer covering the contact hole and the insulating film in the vicinity of the contact hole is uniform, i.e., the coverage of the barrier metal layer on the source (drain) electrode is improved, whereby the mutual impurity diffusion between the source (drain) electrode and the electrode wiring layer is effectively prevented by the barrier metal layer. In addition, since the interface between the metal film buried in the contact hole and the internal side wall of the contact hole, i.e., the insulating film, is covered with the barrier metal layer, the mutual impurity diffusion between the electrode and the wiring layer along the interface is prevented by the barrier metal layer.
According to a second aspect of the present invention, a method for producing a semiconductor device includes forming an insulating film on a compound semiconductor substrate on which source and drain electrodes are disposed apart from each other, selectively removing portions of the insulating film to form contact holes on the source and drain electrodes, filling the contact holes with first metal films to even the surface of the insulating film, successively depositing a barrier metal layer and a second metal film on the entire surface of the insulating film, and patterning the barrier metal layer and the second metal film to form source and drain wiring layers electrically connected to the source and drain electrodes. In this method, the barrier metal layer with uniform quality is formed on the contact hole and the insulating film in the vicinity of the contact hole. In addition, when etching the insulating film to form the contact holes, it is not necessary to select an etchant that etches the insulating film but does not etch the barrier metal layer, increasing the degree of freedom in the production process.
According to a third aspect of the present invention, in the method for producing the semiconductor device, the contact holes are formed by selectively etching portions of the insulating film using a prescribed photoresist film as a mask, and the contact holes are filled with the first metal films by depositing the first metal on the entire surface using the photoresist film as a mask and then removing the photoresist film and overlying portions of the first metal by lift-off, whereby the surface of the insulating film is evened.
According to a fourth aspect of the present invention, in the method for producing the semiconductor device, the contact holes are filled with the first metal films by selectively growing the first metal on the source and drain electrodes exposed in the respective contact holes
Therefore, no space is produced between the side surface of the metal film filled in the contact hole and the internal side wall of the contact hole, resulting in a highly reliable semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a sectional view illustrating a semiconductor device in accordance with a first embodiment of the present invention;
Figures 2(a)-2(f) are sectional views illustrating process steps for producing an electrode wiring layer in a production method for the semiconductor device of figure 1;
Figures 3(a)-3(c) are sectional views illustrating process steps for producing an electrode wiring layer according to a second embodiment of the present invention;
Figures 4(a) and 4(b) are sectional views for explaining an effect of the wiring layer formation process of the second embodiment in comparison with that of the first embodiment;
Figures 5(a) is a sectional view illustrating a semiconductor device in accordance with the prior art and figure 5(b) is an enlarged view of a part of the semiconductor device;
Figures 6(a)-6(d) are sectional views illustrating process steps for producing an electrode wiring layer in a production method of the semiconductor device of figure 5(a);
Figures 7(a) and 7(b) are sectional views illustrating an electrode wiring structure of a semiconductor device according to the prior art; and
Figure 8 is a sectional view illustrating an electrode wiring structure of a semiconductor device according to the prior art.
DETAILED DESCRIPTION OF THE PREFERRED EMRODIMENTS
Figure 1 is a sectional view illustrating an FET in accordance with a first embodiment of the present invention.
In the figure, the same reference numerals as in figure 5(a) designate the same or corresponding parts. The contact holes 4a and 4b of the SiO2 film 4 is filled with metal films 7a and 7b comprising tungsten (W) or molybdenum (Mo), respectively, to even the surface of the SiO2 film 4.
Barrier metal layers 8a and 8b comprising tungsten silicide nitride (WSiN) or titanium nitride (TiN) are disposed on the metal films 7a and 7b and on portions of the Si02 film 4 in the vicinity of the metal films, respectively. Source and drain wiring layers 9a and 9b are disposed on the barrier metal layers 8a and 8b, respectively.
Figures 2(a)-2(f) illustrate process steps for producing the source and drain wiring structure of the FET of figure 1. Since the process steps are carried out symmetrically with respect to the source side and the drain side of the FET, only a part of the FET on the source side is shown in figures 2(a)-2(f) for simplification. In addition, the impurity doped regions in the substrate are omitted.
The process steps of figures 2(a) and 2(b) are identical to those already described with respect to figures 6(a) and 6(b) and, therefore, do not require repeated description.
After forming the contact hole 4a, a first metal film 7 is deposited over the entire surface (figure 2(c)). The first metal film 7 is deposited to the same thickness as the
SiO2 film 4, i.e., 4000 - 8000 A. Preferably, the metal film 7 comprises W or Mo which does not act on AuGe, Ni, and
Au contained in the source and drain electrodes, or Au which acts on AuGe, Ni, and Au but does not increase the resistance.
Then, the photoresist mask 5 is melted using organic solvent or the like and removed together with the overlying portions of the metal film 7 by lift-off, leaving a portion 7a of the metal film in the contact hole 4a (figure 2(d)).
Thus, the contact hole 4a is filled with the metal film 7a.
Thereafter, a first metal is deposited by sputtering to a thickness of about 1000 A, forming the barrier metal layer 8, and a second metal is deposited thereon by sputtering to a thickness of about 6000 A, forming a second metal layer 9 (figure 2(e)). Preferably, the barrier metal layer 8 comprises WSiN or TiN and the second metal layer 9 comprises
Au, Ti/Au, Al base alloy including Si and Cu, or Cu.
Finally, the second metal layer 9 and the barrier metal layer 8 are selectively etched using a second photoresist mask 10, forming a source wiring layer 9a electrically connected to the source electrode 3a (figure 2(f)).
According to the first embodiment of the present invention, the contact holes 4a and 4b penetrating through the SiO2 film 4 to expose the underlying source and drain electrodes are filled with the metal films 7a and 7b to even the surface of the Si02 film 4, and the source and drain wiring layers 9a and 9b are disposed on the flat surface via the barrier metal layers 8a and 8b, respectively.
Therefore, the quality of the barrier metal layers 8a and 8b is uniform on the contact holes 4a and 4b and on the SiO2 film 4 in the vicinity of the contact holes, improving the coverage of the barrier metal layers on the source and drain electrodes, whereby the barrier metal layers effectively prevent the mutual diffusion between the source and drain electrodes and the respective wiring layers.
Particularly when the second metal film 9 comprises Al base alloy, the barrier metal layers prevent the purple plague, i.e., an unwanted aluminum-gold eutectic mixture at the boundary between the wiring layers containing Al and the source and drain electrodes containing Au.
Since the interface between the metal film 7a (7b) and the internal side wall of the contact hole 4a (4b) is covered with the barrier metal layer 8a (8b), the barrier metal layer prevents the mutual impurity diffusion between the electrode 3a (3b) and the wiring layer 9a (9b) along the interface.
In the production method according to the first embodiment of the present invention, since the barrier metal layer is formed after the selective etching of the SiO2 film 4 to form the contact hole, it is not necessary to select an etchant that etches the SiO2 film 4 but does not etch the barrier metal layer, which means that the production process is not restricted.
While in the above-described first embodiment the first metal film 7 is filled in the contact hole by the conventional deposition and lift-off technique, other methods may be employed.
Figures 3(a)-3(c) are sectional views illustrating process steps for producing a source and drain wiring structure in accordance with a second embodiment of the present invention. In this second embodiment, a selective
CVD (Chemical Vapor Deposition) method is employed to fill the metal film in the contact hole.
After forming the contact hole 4a in the SiO2 film 4 (figure 3(a)), the GaAs substrate 1 is exposed to an atmosphere in which SiH4/WF6 gas is flown at the pressure of 0.2 Torr and the temperature of 300 "C, whereby tungsten is selectively grown on the source electrode 3a in the contact hole 4a (figure 3(b)). After successively depositing the barrier metal layer 8 and the second metal layer 9 (figure 3(c)), these layers are patterned to form the source wiring layer 9a which is in contact with the source electrode 3a via the barrier metal layer.
The selective CVD method provides a highly reliable semiconductor device compared with the deposition and liftoff techniques employed in the first embodiment.
In the production process according to the first embodiment in which the first metal film 7 is formed in the contact hole 4a using the deposition and lift-off techniques, unwanted spaces are sometimes produced between the opposite side surfaces of the buried metal film 7a and the internal side walls of the contact hole 4a (portions indicated by "A" in figure 4(a)), which spaces reduce the reliability of the device.
In the second embodiment of the present invention, since the contact hole 4a is filled with the metal film 17 selectively grown on the source electrode 3a in the contact hole by CVD, no space is produced between the opposite side surfaces of the metal film 17 and the internal side walls of the contact hole 4a (portions indicated by "B" in figure 4(b)), resulting in a highly reliable semiconductor device.
Claims (8)
1. A field effect transistor including:
source and drain electrodes (3a,3b) disposed on a semiconductor substrate (1) apart from each other;
an insulating film (4) disposed on the semiconductor substrate (1) and on the source and drain electrodes (3a,3b), having first and second contact holes (4a,4b) opposite the source and drain electrodes (3a,3b), respectively, said first and second contact holes (4a,4b) being filled with first and second metal films (7a,7b) to even the surface of the insulating film (4);
first and second barrier metal layers (8a,8b) respectively disposed on the first and second metal films (7a,7b) and on portions of the insulating film (4) in the vicinity of the metal films (7a,7b), covering the surfaces of the first and second metal films (7a,7b) and the interfaces between the first and second metal films (7a,7b) and the insulating film (4); and
source and drain wiring layers (9a,9b) respectively disposed on the first and second barrier metal layers (8a,8b).
2. The field effect transistor of claim 1 wherein said source and drain electrodes (3a,3b) comprise gold, copper, or gold base alloy, and said first and second barrier metal layers (8a,8b) comprise tungsten silicide nitride or titanium nitride.
3. A method for producing a field effect transistor including:
forming an insulating film (4) on a compound semiconductor substrate (1) on which source and drain electrodes (3a,3b) are disposed apart from each other;
selectively removing portions of said insulating film (4) to form contact holes (4a,4b) on said source and drain electrodes (3a,3b);
filling said contact holes (4a,4b) with first metal films (7a,7b) to even the surface of the insulating film (4);
successively depositing a barrier metal layer (8) and a second metal film (9) on the entire surface and patterning said barrier metal layer (8) and said second metal film (9) to form source and drain wiring layers (9a,9b) electrically connected to the source and drain electrodes (3a,3b) via the first metal films (7a,7b).
4. The method of claim 3 wherein said contact holes (4a,4b) are formed by selectively etching portions of the insulating film (4) using a prescribed photoresist film (5) as a mask, and said first metal films (7a,Zb) are formed by depositing a first metal (7) on the entire surface using said photoresist film (5) as a mask and then removing said photoresist film (5) and overlying portions of the first metal (7) by lift-off.
5. The method of claim 3 wherein said first metal films (7a,7b) are formed by selectively growing metal films (17) on the source and drain electrodes (3a,3b) exposed in the contact holes (4a,4b).
6. The method of claim 3 wherein said source and drain electrodes (3a,3b) are formed by selectively depositing
AuGe, Ni, and Au and alloying these metal films by annealing.
7. A field effect transmitor substantially as hereinbefore described with reference to either one of the two embodiments illustrated in Figures 1 to 4 of the accompanying drawings.
8. A method according to claim 3 substantially as hereinbefore disclosed.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3591393A JPH06252088A (en) | 1993-02-25 | 1993-02-25 | Semiconductor device and its manufacture |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9313120D0 GB9313120D0 (en) | 1993-08-11 |
| GB2275570A true GB2275570A (en) | 1994-08-31 |
| GB2275570B GB2275570B (en) | 1996-11-27 |
Family
ID=12455276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9313120A Expired - Fee Related GB2275570B (en) | 1993-02-25 | 1993-06-24 | Diffusion barriers for F.E.T. connections |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH06252088A (en) |
| FR (1) | FR2702089B1 (en) |
| GB (1) | GB2275570B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08160450A (en) * | 1994-12-12 | 1996-06-21 | Ricoh Co Ltd | Laminated metal material for wiring and method for forming pattern using that material |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4954214A (en) * | 1989-01-05 | 1990-09-04 | Northern Telecom Limited | Method for making interconnect structures for VLSI devices |
| US5104826A (en) * | 1989-02-02 | 1992-04-14 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor integrated circuit device using an electrode wiring structure |
| GB8907898D0 (en) * | 1989-04-07 | 1989-05-24 | Inmos Ltd | Semiconductor devices and fabrication thereof |
| JP2839579B2 (en) * | 1989-10-02 | 1998-12-16 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| EP0507881A1 (en) * | 1990-01-04 | 1992-10-14 | International Business Machines Corporation | Semiconductor interconnect structure utilizing a polyimide insulator |
| EP0491433A3 (en) * | 1990-12-19 | 1992-09-02 | N.V. Philips' Gloeilampenfabrieken | Method of forming conductive region on silicon semiconductor material, and silicon semiconductor device with such region |
-
1993
- 1993-02-25 JP JP3591393A patent/JPH06252088A/en active Pending
- 1993-06-24 GB GB9313120A patent/GB2275570B/en not_active Expired - Fee Related
- 1993-07-29 FR FR9309369A patent/FR2702089B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06252088A (en) | 1994-09-09 |
| FR2702089A1 (en) | 1994-09-02 |
| FR2702089B1 (en) | 1995-05-12 |
| GB9313120D0 (en) | 1993-08-11 |
| GB2275570B (en) | 1996-11-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20000624 |