GB2274954A - Flicker reduction in progressive to interlace converter - Google Patents

Abstract

An image display system comprises circuitry (20) for scanning line by line an array of progressive scan pixel data in a memory (10). Data corresponding to a first set of scanning lines is held in line memory (22) and data corresponding to an adjacent line is held in a second line memory (23). Data is taken alternately from the first and second stores (22, 23), (see fig. 6) and supplied to a colour palette circuit (41) for converting the pixel signals into respective interlaced colour analog signals for supply on lines (15, 16, 17) to a TV display (90). This removes the need for averaging circuits for flicker reduction. <IMAGE>

Description

IMAGE DISPLAY SYSTEM The invention relates to an image display system and methods of displaying video signals with reduced flicker.

Problems of flicker can arise in displaying pixel information on a video display device such as a conventional TV set particularly where the pixel information is in the form of computer generated graphics information. High resolution computer graphics such as VGA image or text normally results in high contrast in both brightness and colour between adjacent lines. Such video graphics are normally of a non-interlace field format and have a high frame rate of for example 75 frames per second. In a non-interlace field format adjacent lines in a frame are successively scanned. In order for high resolution computer graphics to be displayed on a colour television screen these non-interlaced frames must be converted to an interlaced field format.In television these fields are called odd and even in that the odd field consists of all odd lines of a frame and the even field consists of the even lines of the frame. After the lines of the odd field are successively scanned the lines of the even field are successively scanned to produce a single frame.

Conventional TV pictures also differ from high resolution computer graphics in that the frame rate may be 25 frames per second and therefore significantly slower than that used for high resolution computer graphics. A picture which appears flicker free when displayed in a non-interlaced format at 75 frames per second on a computer graphics terminal may well provide an unacceptable flicker when shown on a television set at 25 frames per second with an interlaced format. This flicker can be due to the high contrast in brightness and colour between adjacent lines. To avoid this problem when using a display on a conventional TV set it is necessary to reduce the contrast in brightness and colour between adjacent lines. In a known method of reducing this problem the pixel values in successive pairs of lines in the frame have been averaged.

It is an object of the present invention to provide improved display apparatus and methods which reduce picture flicker without needing to form average pixel values for a pair of lines.

The present invention provides a method of forming a video display of pixel data, which method comprises storing pixel data corresponding to successive lines of an input video array, outputting successive pixel values from the stored data to form lines of a video output, each line of said video output comprising a plurality of successive values taken alternately from each of a pair of adjacent lines in said input video array, and supplying said lines of video output successively to a video display device.

The present invention also provides a video display system for displaying pixel data of a video signal on a TV screen, which system comprises scanning means for scanning line by line an array of pixel data, pixel store means for receiving and storing pixel data from the scanning means, the store means having a first set of store locations for holding pixel data corresponding to a first set of lines in said array and a second set of store locations for holding data corresponding to a second set of lines in said array, pixel data readout means for reading pixel data alternately from said first and second locations to produce a succession of pixel signals, taken alternately from said first and second sets of store locations, colour palette means for converting said succession of pixel signals into respective colour analog signals and output circuitry for supplying said colour analog signals to a TV display screen for each pixel in said succession.

Preferably said first and second store locations are arranged to hold respectively pixel values for adjacent lines in said array so that each line in the output contains successive pixel values derived alternately from an adjacent pair of lines in said array.

Preferably said scanning means is arranged to scan said array as a non-interleaved field format and said pixel data readout means is arranged to output pixel values as an interlaced field format. Preferably said scanning means is arranged to scan said array with a line scan time which is half the line output time of said pixel data readout means. Preferably said scanning means is arranged to scan said array at twice the frame rate of said output circuitry.

The aforesaid method is particularly applicable to the display on a TV screen of pixel data derived from a computer generated video array.

Preferably the video input array is scanned at twice the frame rate of the video output.

Preferably the video output has more pixel values per line than said input video array.

Preferably the video input array is scanned as a non-interlaced field format and said video output is formed as an interlaced field format.

Preferably each line of said video input array is read at half the line scan time of said video output.

The aforesaid method is particularly applicable to colour video displays and the pixel values of said video output may be converted to respective colour analog signals to form a colour video display. Preferably the pixel values derived from both lines forming an adjacent pair are fed to a common colour palette.

An embodiment of the invention will now be described by way of example and with reference to the accompanying drawings in which: Figure 1 shows a block diagram of a known system for converting computer graphics to television pictures, Figure 2 is a schematic diagram of the conversion circuit of Figure 1 according to the prior art, Figure 3 is a schematic view of a conversion circuit which may be used in Figure 1 according to the present invention, Figure 4 shows pixel information which is entered into the conversion circuit of Figure 2 or Figure 3, Figure 5 shows pixel information as it is output from the conversion circuit to the television set according to the circuit of Figure 2, Figure 6 shows pixel information as it is output from the conversion circuit to the television set by use of the circuit of Figure 3.

Figure 1 is a block diagram of a known system, also applicable to the present invention, for displaying high resolution computer graphics on a conventional TV set. A memory 10 stores computer generated eight bit binary numbers, each eight bit binary number representing an analog pixel value. A frame on the television display is made up of a plurality of lines, each line being made up of a plurality of pixels. A conversion circuit 12 addresses the memory 10 on an address bus 13 and thereby scans the pixel data in memory 10 on a line by line basis in a non-interlaced format. The pixel data for each line is read out successively on bus 14 and fed to the conversion circuit 12.The conversion circuit converts the succession of non-interlaced frames at its input to interlaced frames at its output and provides three analog output signals 15, 16 and 17 which represent red, green and blue values for each pixel. The conversion circuit 12 also produces a synchronisation signal 18 and these four output signals 15, 16, 17 and 18 are fed to a conventional television set 19.

The prior art conversion circuit 12 will now be described with reference to Figure 2. The conversion circuit 12 consists of a controller 20 which provides scanning addresses on bus 13 and receives data on bus 14 which has been read from the memory 10. The controller 20 provides eight bit pixel data on bus 21 to both a first FIFO 22 and a second FIFO 23. Each FIFO 22 and 23 acts as a buffer to hold one line of pixel data from the memory 10. The pixel values held in the buffers are each eight bit values and they are supplies serially on respective buses 24 and 25 to separate colour palettes 26 and 27. Each colour palette is arranged to provide three serial analog outputs 28, 29 and 30 representing red, green and blue values respectively. The outputs from both colour palettes 26 and 27 are fed to three summing amplifiers. Amplifier 31 receives both red signals and forms an average. Amplifier 32 receives both green signals and provides an average. Amplfier 33 receives both blue signals and forms an average. The outputs of the summing amplifiers are respectively signals 15, 16 and 17 which are fed to the television 19. The controller 20 provides timing inputs 35 and 36 to a state machine 37 which provides the synchronisation signal 18 to the television 19 and is also connected to both FIFO 23 and FIFO 22. The operation of this arrangement is as follows. The memory 10 holds a frame of pixel values which have been computer generated conforming to a VGA graphic standard. The pixel data for one frame is represented in Figure 4 in which the frame consists of lines 0-N and each line has pixels Pl. . PN For ease of identification the pixel values in the first three lines have been indicated by appropriate letters in Figure 4.The controller 20 scans the frame of stored data by appropriate addresses on bus 13 and reads out the eight bit pixel values on a line by line basis. In this way the N pixel values for line 0 are fed serially into FIFO 22 and then the end pixel values corresponding to line 1 are fed serially into FIFO 23. The frame is scanned in a non-interlaced format so that lines 0 to N are scanned successively. The pixel array in the memory 10 is scanned at an effective frame rate of 50 frames per second and the line scan duration in reading the data into the FIFO 22 and 23 is 32 microseconds. When line 0 is in FIFO 22 and line 1 is in FIFO 23 the contents of the two FIFO's are read simultaneously so that the pixel values in each of them are supplied serially to their respective colour palettes 26 and 27.The pixel values are converted to the appropriate analog red, blue and green signals for lines 28, 29 and 30 and the outputs of the two colour palettes 26 and 27 are averaged by the summing amplifiers 31, 32 and 33. The state machine 37 controls reading of the pixel values from the FIFO 22 and FIFO 23 so that data is read from both FIFO's simultaneously but at half the input rate of pixel data to the FIFO's 22 and 23. In this way the output video information which is supplied to the television 19 is in the form shown in Figure 5. Each line now has a line scan duration of 64 microseconds and has two N pixels per line as each of the averaged pixel values is repeated. In this way, in line 0 of Figure 5 pixel value P1 is the average of A + I from Figure 4 and pixel value P2 in line 0 is a repeat of pixel value P1.

Similarly P3 in line 0 is the average of B + J from Figure 4 and P4 equals P3. Similarly P5 is the average of values C + K in Figure 4 and P6 equals P5.

To produce the interlaced field format the state machine 37 controls the buffers 22 and 23 so that when the pixel values from lines 0 and 1 in Figure 4 have been used to generate line 0 for Figure 5 the contents of those buffers are cleared and replaced by lines 2 and 3 of Figure 4 in buffers 22 and 23 respectively. This then allows lines 2 and 3 of Figure 4 to be used to generate the average values for line 2 of Figure 5. In this way the even field of an interlaced frame is generated. Once the even frame has been completed the buffers 22 and 23 are loaded by a repeated scan of the same frame in the memory 10. This time buffer 22 is loaded with line 1 from Figure 4 and buffer 23 is loaded with line 2 from Figure 4.

The pixel values are then again read simultaneously from both buffers and the output values averaged to generate values for line 1 of Figure 5. This is then repeated to generate lines 3, 5 etc of Figure 5 thereby completing the odd field for the interlaced frame. This odd field is output to the television 19 in succession after the even frame so as to complete the interlaced fields for a full frame scan in the television 19.

By use of average pixel values from two adjacent lines it is possible to achieve reduced flicker in the television even though using pictures of high contrast in the original video array. This prior art arrangement does however require additional circuitry in providing separate colour palettes for each of the buffers 22 and 23 as well as the summing amplifiers 31, 32 and 33 in order to produce the average values.

The embodiment which will now be described with reference to Figures 3 and 6 avoids this additional circuitry. In this example similar reference numerals have been used for those components which are similar to those of Figure 2. The pixel data in the memory 10 is the same as previously described and this is read by the controller 30 as previously described.

Pixel data of the type shown in Figure 4 is thereby read into the FIFO buffers 22 and 23 on a line by line basis during a scan of one frame of pixel data in the memory 10. The data is again read from the memory 10 in a non-interleaved manner so that data is taken from each line successively. When the FIFO 22 holds data corresponding to line 0 from Figure 4 and FIFO 23 holds data corresponding to line 1 of Figure 4 the state machine 37 causes pixel data to be read out of the buffers as a serial data string in which successive pixels in the string are taken alternately from each of the buffers 22 and 23. This string of pixel values is supplied on a single bus 40 to a single colour palette 41.It will be seen that the string of pixel values derived from line 0 and line 1 of Figure 4 will be used to generate line 0 of the video data output as shown in Figure 6 and as illustrated in Figure 6 line 0 will consist of a succession of pixel values corresponding to values A, I, B, J, C, K, D, L, E taken alternately from line 0 and line 1 of the input video array.

Data is read from each buffer 22 and 23 at a rate equal to half the rate at which the controller 20 accesses data from the memory 10. However, as the data string is formed by alternate data from each of the buffers 22 and 23 the combined output data rate on bus 40 to the colour palette 41 is the same as the input data rate through the controller 20. The input data rate through the controller 20 has a line scan duration of 32 microseconds but as the output lines each comprise in succession all pixel values derived from two input lines the output line duration is now 64 microseconds. In order to produce the interleaved field format for the television 19 the state machine 37 controls the loading and reading from the buffers 22 and 23 so that during even field formation line 0 and line 1 of Figure 4 are used to generate the output line 0 shown in Figure 6. Lines 2 and 3 of Figure 4 are then used to form line 2 of Figure 6. Lines 4 and 5 of Figure 4 are then used to produce line 4 of Figure 6 and so on. When the full even field has been completed the frame in memory 10 is scanned a second time and the buffers 22 and 23 sequentially reloaded to produce the odd field. This time lines 1 and 2 of Figure 4 are loaded respectively into buffers 22 and 23 and used to generate line 1 of the output shown in Figure 6. Similarly lines 3 and 4 of Figure 4 are then used to produce the output line 3 in Figure 6 and so on.

It will therefore be seen that the output video pixel format shown in Figure 6 is supplied to the television 19 in two interleaved fields for each frame. Each line of pixel data fed to the television consists of interleaved pixels taken alternately from two adjacent lines of the video input. The interleaved pixels are too fine for the human eye to notice and the effect of the pixel interleaving is to reduce flicker by reducing contrast between adjacent lines in the picture displayed on the television.

It will be seen that by use of the arrangement shown in Figures 2 and 6 the circuitry needed to reduce picture flicker has been substantially reduced in that it is only necessary to use one colour palette and no summing amplifiers are needed.

It will be appreciated that the colour palette 41 translates the interleaved pixel data to analog pixels consisting of interleaved red, interleaved green and interleaved blue components.

This embodiment is particularly applicable to arrangements where circuit space is limited. Due to the simplicity of the circuit needed it is possible to implement on a single printed circuit card circuitry capable of displaying a plurality of different VGA pictures, for example four pictures, onto a plurality of TV sets without noticeable flicker.

The invention is not limited to the details of the foregoing example.

Claims (13)

CLAIMS:

1. A method of forming a video display of pixel data, which method comprises storing pixel data corresponding to successive lines of an input video array, outputting successive pixel values from the stored data to form lines of a video output, each line of said video output comprising a plurality of successive values taken alternately from each of a pair of adjacent lines in said input video array, and supplying said lines of video output successively to a video display device.

2. A video display system for displaying pixel data of a video signal on a TV screen, which system comprises scanning means for scanning line by line an array of pixel data, pixel store means for receiving and storing pixel data from the scanning means, the store means having a first set of store locations for holding pixel data corresponding to a first set of lines in said array and a second set of store locations for holding data corresponding to a second set of lines in said array, pixel data readout means for reading pixel data alternately from said first and second locations to produce a succession of pixel signals, taken alternately from said first and second sets of store locations, colour palette means for converting said succession of pixel signals into respective colour analog signals and output circuitry for supplying said colour analog signals to a TV display screen for each pixel in said succession.

3. An image display system according to claim 2 in which said first and second store locations are arranged to hold respectively pixel values for adjacent lines in said array so that each line in the output contains successive pixel values derived alternately from an adjacent pair of lines in said array.

4. An image display system according to claim 2 or claim 3 in which said scanning means is arranged to scan said array as a non-interleaved field format and said pixel data readout means is arranged to output pixel values as an interlaced field format.

5. An image display system according to any one of claims 2 to 4 in which said scanning means is arranged to scan said array with a line scan time which is half the line output time of said pixel data readout means.

6. An image display system according to any one of claims 2 to 5 in which said scanning means is arranged to scan said array at twice the frame rate of said output circuitry.

7. A method according to claim 1 in which said input video array comprises a computer generated video array and said video display unit comprises a TV screen.

8. A method according to claim 1 or claim 7 in which the video input array is scanned at twice the frame rate of the video output.

9. A method according to claim 1 or claim 7 or claim 8 in which the video output has more pixel values per line than said input video array.

10. A method according to claim 1 or any one of claims 7 to 9 in which the video input array is scanned as a non-interlaced field format and said video output is formed as an interlaced field format.

11. A method according to claim 1 or any one of claims 7 to 10 in which each line of said video input array is read at half the line scan time of said video output.

12. A method according to claim 1 or any one of claims 7 to 11 in which the pixel values of said video output are converted to respective colour analog signals to form a colour video display.

13. An image display system substantially as hereinbefore described with reference to the accompanying Figures 3, 4 and 6.