GB2274037A

GB2274037A - Video signal main processor for radar system

Info

Publication number: GB2274037A
Application number: GB9227077A
Authority: GB
Inventors: Seoung-Cheol Lee
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1992-12-30
Filing date: 1992-12-30
Publication date: 1994-07-06
Anticipated expiration: 2012-12-30
Also published as: GB9227077D0; GB2274037B

Abstract

A video signal main processor for a radar system includes a digitizer 40, a constant false alarm rate (CFAR) processor 50 for detecting a pure target signal using a built-in algorithm for canceling the clutter, noise and interference thereof, and a buffer/pixel timing controller 60 for synchronizing video data with the pixels. Using the CFAR-processing for properly reducing the clutter and noise level contained in a radar video signal, the main processor efficiently detects a target and prevents the displaying of a false target. Further, the processor uses an exclusive memory in feedback integration and threshold decoding, thereby enhancing the target detection capability and processing the video signal at high speed. <IMAGE>

Description

VIDEO SIGNAL MAIN PROCESSOR FOR RADE SYSTEM The present invention relates to a video signal processing technology for a radar system, and more particularly to a video signal processor for canceling various kinds of clutter and noise contained in video signal for a radar and extracting a target signal.

Radars are classified into pulse radar, continuous-wave radar, frequency-modulation radar, and phase-modulation radar. A general radar for use in navigation, meteorological observation, coastal defense, topographical surveying and vehicle transportation observation is illustrated in Fig. 1. A pulse modulator 10 generates repetitive pulse trains, and a transmitter 11 amplifies a signal in accordance with the pulse trains and sends it to an antenna 14. Duplexer 12 separates the transmission and reception functions of antenna 14 so that the antenna mav be commonly used for transmission and reception.Antenna 14 radiates the pulses and receives echoes reflected by a target. the surface of the ground, sea surfaces. and atmospheric moisture (e.g., rain, clouds and fog). As the position coordinates of antenna 14 are controlled by a position servo 22 connected between a pedestal 13 for driving antenna 14 and displavicontroller 21, the azimuth angle on the display and the position of antenna 14 are synchronized. The echo signals received by antenna 14 are input to a low-noise radio frequency (RF) amplifier 15 via duplexer 12. Low noise RF amplifier 15 reduces noise and amplifies the received signals. Mixer 16 mixes a local oscillating signal from local oscillator 17 and the received RF signal, usually to form an intermediate frequency (IF) signal of 30120MHz.An IF amplifier 18 is a matched filter to amplify a signal while improving its signal-to-noise (S/N) ratio. A detector 19 detects a video signal from the received IF signal. The detected video signal contains a signal reflected from a target, as well as noise and clutter. A video signal processor 20 cancels the noise and/or clutter which is undesirable in radar operation, being counter to the radar system's purpose, and extracts a genuine target signal to be displayed. A display/controller 21 displays a target picked up by the radar and various information on the target. Additionally, a regulator for selecting a clutter algorithm is provided so that the screen state can be controlled by a user.

Fig.2 shows video signal processor 20 in more detail. In Fig.2, the processor has a clutter canceler 23 for canceling clutter from a received echo signal, and a video signal main processor 24 for extracting a target signal while lowering the extracting level of various noise signals below a predetermined level. The video signal main processor functions to extract a genuine target signal by CFAR-processing (constant false alarm rate processing).

Fig.3 is a block diagram for explaining a conventional video signal processing technology. A conventional CFAR processing method is one wherein video data is stored and data having various pulse repetition times (referred to as PRT hereinafter) is compared to detect onlv the relatively large target signal. One such a method is disclosed in USP No. 4,845,500 (issued Julv 4,1989). In this method, as shown in Fig.3, a video processor 30 has a digitizer 32, an averager 33 and a video storage unit 34. Digitizer 32 converts a received analog radar signal into a digital word in accordance with a sampling rate and outputs it.Averager 33 finds the average of digital words in a window portion whose size is appropriately controlled according to the target size, and stores the averaged digital word in video storage unit 34.

Averager 33 is svnchronized with a trigger signal and the position coordinates of the antenna.

Here, the window size is determined by the number of azimuth sectors and the number of range bins. The number of azimuth sectors is determined by an azimuth start/stop signal which is generated by a target size/position circuit 37 and is input to video storage 34. The number of range bins is determined by a range start/stop signal which is generated by a range start circuit 39 and is input to averager 33.

A tracking processor 31 controls the window size to have an adequate number of range bins and azimuth sectors in accordance with the target size.

In Fig.3, in order to detect the movement of a target, tracking processor 31 has a noise reducer 35, a target detector 36, a target size/position circuit 37, a speed/heading circuit 38, and a range start circuit 39. Since such a conventional method does not sufficiently satisfy a video signal processing algorithm and is thus difficult to keep a constant noise level, the detection capability of a pure target (target signal only) is reduced, increasing the likelihood of displaying a false target. Further, since the video signal processor for the conventional method is operated in connection with the tracking processor, the processor cannot be used for ground surface mapping or meteorological observation and is only used for a radar having a tracking processor.

Therefore, it is an object of the present invention to provide a video signal main processor for appropriately canceling various clutter and noise contained in a received radar signal. so as to increase its capability of detecting or picking up a target.

To accomplish the object of the present invention, there is provided a video signal main processor for a radar system comprising: digitizing means for converting an analog video signal into digital form and storing the digital signal in a memory; CFAR (constant false alarm rate) processing means for receiving the output signal from the digitizing means and detecting a pure target signal using a built-in algorithm for canceling the clutter, noise and interference thereof; and buffer/pixel timing control means for receiving the target signal of the CFAR processing means and sequentially outputting the signal according to pixel timing so as to synchronize video data with the pixels.

The above object and other advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: Fig. 1 is a block diagram of a general radar system to which both the prior art and the present invention are applied; Fig.2 is a detailed block diagram of the video signal processor shown in Fig.l:: Fig.3 is a block diagram of a conventional video signal main processor for a radar system; Fig4 is a block diagram of a video signal main processor for a radar system according to the present invention Fig.5 is a detailed block diagram of the digitizer shown in Fig.4; Fig.6 is a detailed block diagram of the CFAR processor shown in Fig.4; Fig.7 is a detailed block diagram of the bufferípixel timing controller shown in Fig.4; Fig. 8A is a block diagram in which the interference canceler of Fig.7 is incorporated in the threshold decoder; Fig.8B is a block diagram in which the interference canceler of Fig.7 is provided on the output of the threshold decoder; ; Fig.9A illustrates an example in which a round plan position indicator is formed on a square screen; and Fig.9B illustrates the change in the number of pixels according to the change of angle on the screen.

Fig.4 is a block diagram of a video signal main processor for a radar system according to the present invention.

Referring to Fig.4, the video signal main processor comprises a digitizer 40, a CFAR processor 50, and a buffer/pixel timing controller 60. A received radar signal including clutter which first has been reduced in the clutter canceler (element 23 of Fig.2). is input to digitizer 40. Digitizer 40 converts an analog video signal into a digital video signal and stores it in a built-in memory, so as to process the digital signal.

The output of digitizer 40 is supplied to CFAR processor 30 so as to cancel the noise and clutter of the received signal and to detect a genuine target. In detecting a target signal, CFAR processor 50 keeps the false alarm rate constant by canceling the clutter and noise of the digital video signal. If desired, the output of digitizer 40 is supplied directly to buffer/pixel timing controller 60 for raw video processing in which a received radar signal is displayed without its noise or clutter being removed.

Buffer/pixel timing controller 60 sequentially outputs the target signal input from CFAR processor 50 or the digital signal directly input from digitizer 40 according to pixel timing so as to supply the output to a tracking processor, display and video memory (all not shown), and generates various timing signals for displaying. Along with clutter canceler 23 shown in Fig.2, video signal main processor 24 of the present invention is the essenrial signal processing system in a navigational radar system, and performs signal processing for noise cancellation, reduction of the undesired clutter, and CFAR functions.

Fig.5 is a detailed block diagram of digitizer 40 shown in Fig.4. Here, the digitizer comprises an A/D converter 41, a video distributer 42 and a video buffer memory 13. An analog video signal is sampled in AID converter 41 according to a clock input, to be converted into a digital video signal. The digital video signal is input to a video distributor 42 to be classified in accordance with pulse repetition time (PRT). and is stored in video buffer memory 43. A sampling clock 100 input to A/D converter 41 is determined bv resolution. pulse width, range and pulse repetition frequency (referred to as PRF), and is obtained by dividing a fundamental clock frequency.The number of digital bits for every range cell is between two and twelve bits and is varied according to the purpose and specification of the radar system. In navigation, for example, two to weight bits are sufficieni.

Video buffer memory 43 is composed of two or more memory groups.

While a first buffer X stores data for one pulse repetition time (PRT), a second buffer 45 outputs previously stored PRT data. If the number of buffers is expanded to N, N sets of PRT video data can be stored, the memory is capable of separately performing reading and writing operations.

Referring to Fig.6, the CFAR processor (element 50 of Fig.4) has a summer 51, a main memory 52, a threshold decoder 53, a feedback integration memory 54, and an interference canceler 56. In CFAR processing, the false-target detection rate and noise are kept below predetermined levels to suppress the displaying of false targets as much as possible and to improve the S/N ratio. The CFAR function is similar in various radars but the algorithm therefor varies according to radar type and the distribution characteristics of the clutter and noise contained in the reflected signal.The determining factors of such a CFAR algorithm are false alarm probability (PtS)* detection probability (Pd), the number of integration pulses, the number of range bins, threshold level, and S/N ratio. A general false alarm rate (FAR) is expressed in the following equation: FAR = false target number - Not Pfa time range sampling interval where Ntot is the overall number of range bins.

In Fig.6, video input data is supplied to summer 51 for feedback integration and accumulation. The other input of summer 51 receives PRT data which is stored for the number of integration pulses and is fed back via feedback integration memory 54. Video input data is continuously accumulated to reach a quantity equivalent to the number of the integration pulses times the number of A/D conversion bits.Here. the number of integration pulses (M) indicates the number of pulses stored for a beam azimuth angle da (unit: radian), that is, for one sweep line, which is calculated according to the following equation: #a #a M = PRF = #RPM #RPM X PRT where 9RPM is a rotation angle of the antenna per minute; PRF is the number of transmitted pulses per second (in ordinary navigational radar. this number is typically between 5 and 150.: and PR T is the pulse period.

Summer 51 sums currently input PRT data and the fedback PRT data, and n memory 52 stores the summed data. The capacity of main memory D is determined bv the number of integration pulses, period of one PRT, the number of range cells, the AiD sampling clock and the resolution of the disiav. Feedback integration memory 54 outputs video data from main memory 52 according to a feedback factor selected by PRF signal 110 to thus feed back the data to summer 51. Here, since the feedback factor is below one and its value varies in accordance with PRF, when external information on the PRF signal is supplied, feedback integration memory 54 extracts an amount of video data equivalent to the corresponding factor. The resulting value of a feedback integration algorithm, that is. a feedback fac:or or feedback integration constant, can be calculated according to Kopt=@-1.17/M where K,pi is a feedback factor, and 'vi is the number of integration pulses.

The relationship between Kopt and Ntis shown in TABLE 1.

TABLE 1

Kopt M S/N ratio (dB) Kopt (%) 1/2 1-3 0 50 3/4 2-7.5 4 75 7/8 3-16 7 87.5 15/16 7.5-30 10 93.7 31/32 16-80 13 96.8 63/64 40-160 16 98.4 127/128 80-320 19 99.2 In TABLE 1, feedback factor Kopt increases with the increase in the number of integration pulses, and is expressed as a percentage. Here, the S/N ratio represents the CFAR gain according to the number of integration pulses, that is, the degree of the improvement of the S/N ratio.

The CFAR loss, which is determined by the number of integration pulses and the number of output bits 120 of summer 51, is illustrated in TABLE 2.

TABLE 2

Number of Number of summed bits/CFAR loss integration 3 bits 5 bits 10 bits 15 bits pulses 3 5.1 dB 3.1 dB 1.4 dB 1.0 dB 10 2.2 dB 1.3 dB 0.7 dB 0.4 dB 30 1.4 dB 1.0 dB 0.5 dB 0.2 dB 100 1.0 dB 0.6 dB 0.3 dB 0.1 dB TABLE 2 shows CFAR loss (unit:dB) when false alarm probability Pfa is 10-6 and detection probability P@ is 0.95.In TABLE 2, it should be noted char. as he number of integration pulses anci the number of summed bits increase. the loss decreases.

W:nen the S/N ratios of TABLEs 1 and 2 are compared, it is shown that, as the number of integration pulses increases. the CFAR gain increases more sharply than CFAR loss. This indicates that CFAR processing generally improves the S. ratio.

Video data summed in accordance wit the feedback fac:or is the sum or signal components. and can be expressed as: VTi + VTI VTl + Vm aim N N 7 7 ... 7 where, V,= is summed data; VTi is currently input data; VT1 is the first previously input data; VT2 is the second previously input data; VTn is the nth previously input data; N is the feedback factor (Kopt); and n is the number of integration pulses (M).

The video data Vsum passing through summer 51 is digital video data in which, among digital video data having a feedback factor N, the data is summed and stored up to Vm. The video data is equally divided into multiple levels by the PRF signal according to a logarithmic uniform division method in threshold decoder 53. Specifically, the output of threshold decoder 53 is determined by stages, according to the threshold levels of a previously set algorithm by detecting the number of hits (each "hit" is a signal detected in one range) for every range cell in PRT data consisting of as many bits as the number of integration pulses.

One example of the algorithm forming such a threshold level is shown in TABLE 3. TABLE 3

Number of Number of bits according to threshold levels Output integration bits@ 1st level 2nd level 3rd level 4th level pulses 32 1 11 16 10 64 8 01 4 oo 17 1 11 9 10 32 5 01 3 00 *Number of output bits is two In TABLE 3, when the output of the threshold decoder 53 is two bits, if the number of integration pulses is 32 and a range cell is hit seventeen times, the output of the threshold decoder is "11." If the range cell is hit nine times. the threshold decoder output is "10. " If the range cell is hit five times, the output is "01." If the cell is hit three times, the output is "00." Such a level algorithm is varied according to the PRF signal, the distribution characteristics of the clutter, and noise conditions. However, usually, the levels are equally divided logarithmically.

Threshold decoder 53 stores the algorithms in a built-in memory and selects an appropriate algorithm according to an externally supplied PRF signal 110. This processing method improves the S/N ratio by reducing random noise and false alarms.

An interference cancellation function is performed in interference canceler 56 by comparing two successive PRTs, and as the case mav be the output of threshold decoder 53 does not pass through the interference canceler. so that the interference cancellation function is not performed. That is. interference canceler 56 compares PRT(N) data with PRT(N data, and decides whether a level change of the video signal is present, so as to suppress the passing of a signal component having a drastic change, such as an interference component. Interference canceler 56 is of two types: one which uses part of the video integration and the other which compares output data of two successive PRTs after threshold decoding. Those two types are illustrated in Figs.8A and 8B. In Fig.8A, a function of controlling the interference level for canceling interference is realized inside the threshold decoder (53 and 56). The level is selected according to an interference level signal 141. In Fig.8B, the function of canceling interference is realized by providing a comparator 58 and a 1-PRT delay 57 at the output of the threshold decoder. If necessary, the interference function can be on or off according to an interference on/off signal 140. Here, interference indicates a very intense interference signal which has the same frequency or is received from other nearby radar systems.

Fig.7 is a detailed block diagram of the bufferipixel timing controller (element 60 of Fig.4). The buffer!pixel timing controller has a video data speed controller 61, an output buffer 62 and a timing controller 63. In video signal processing and input/output interfacing, data processing speed should be essentially in synchronization with pixel timing. Contrary to a conventional analog displaying method, since a raster scan displaying method requires a great amount of digital video data corresponding to individual pixels, the video data processing speed should be coincident with the pixel timing. Since the number of pixels is increased or decreased depending upon the resolution and angle of the display. the pixel timing cannot be realized as a continuous clock having a specific form.Due to the increase or decrease of pixels, the pixel timing and video data processing speed should be coincident with each other. Only the precise synchronization between these two can reduce the range error and azimuth error. Therefore, the control of pixel timing and the transmission of video data are in close connection.

First, Fig.9A illustrates a screen form in which a round plan position indicator (PPI) of 960-by-960 pixels is formed in a square screen of 102$by 1024 pixels. Fig.9B illustrates the change of the number of pixels according to the change of angle in the round PPI. In Fig.9A, for a video display, the square screen of 1024-by-1024 pixels forms the round PPI of 960-by-960 pixels. The round screen has 480 pixels for the 90o, 1800, 270 and 3600 radii which form the coordinate axes. In Fig.9B, since the pixels are square, there are 480 pixels on the coordinate axes but the number varies with the change of angle.The number of pixels is minimum at 45, 135", 225" and 315", that is. about 340 (480 x cos l5 ) .

In Fig.7. video data speed controller 61 synchronizes a digital video input signal without noise and clutter with the pixels of the display according to the control signal of timing controller 63. Timing controller 63 generates a control signal for synchronizing the pixels and video data speed according to pixel control signal 130 varied by the increase or decrease of the pixels, and supplies the control signal to video data speed controller 61. Output buffer 62 outputs the input video signal to an apparatus (not shown) requiring a CFARprocessed video signal, such as a tracking processor, display or video memory (all not shown).

As described above, using CFAR-processing for properly reducing the clutter and noise level contained in a radar video signal, the present invention efficiently detects a target and prevents the displaying of a false target.

Further, the present invention uses an exclusive memory in feedback integration and threshold decoding, thereby enhancing the target detection capability, and employs a digital signal processing method for high-speed processing, thus miniaturizing the apparatus. The present invention can be applied in navigation, marine surveying, meteorological observation and color video signal processing for a mapping radar system.

Claims

1. A video signal main processor for a radar system comprising: digitizing means for converting an analog video signal into digital form and storing the digital signal in a memory; constant false alarm rate (CFAR) processing means for receiving the output signal from said digitizing means and detecting a pure target signal using a built-in algorithm for canceling the clutter, noise and interference thereof; and buffer/pixel timing control means for receiving the target signal of said CFAR processing means and sequentially outputting the signal according to pixel timing, so as to synchronize video data with pixels.

2. A video signal main processor for a radar system as claimed in claim 1, wherein said digitizing means comprises: an analog-to-digital converter for converting an analog signal into a digital signal; a video distributor for receiving the digital video signal from said analog-to-digital converter and distributing said digital video signal; and a video buffer memory for alternately storing the digital video signal distributed by said video distributor in a plurality of buffers.

3. The video signal main processor for a radar system as claimed in claim 1, wherein said CFAR processing means comprises: a summer for accumulating current pulse repetition time data input from said digitizing means and previous pulse repetition time data previously input and fedback to said summer; a main memory for storing the result accumulated from said summer; a feedback integration memory for receiving the previous data from said main memory and feeding back said data according to a feedback algorithm; and a threshold decoder for receiving video data from said main memory and dividing the received video data into multiple levels according to a threshold level algorithm.

4. The video signal main processor for a radar system as claimed in claim 3 further comprising an interference canceler for canceling interference contained in a video signal.

5. The video signal main processor for a radar system as claimed in claim 1, wherein said buffer/pixel timing control means comprises: a video data speed controller for receiving a target signal detected by said CFAR processing means and controlling the output speed of video data according to a control clock for display; output buffer means for receiving and providing as an external output, the output of said video data speed controller; and a timing controller for receiving an external signal containing data about the number of pixels and supplying a signal for synchronizing video data with pixels, to said video data speed controller.

6. The video signal main processor for a radar system as claimed in claim 1, wherein said CFAR processing means comprises: a summer for accumulating current pulse repetition time data input from said digitizing means and previous pulse repetition time data which is previously input and fedback to said summer; a main memory for storing the result accumulated from said summer; a feedback integration memory for receiving the previous data from said main memory and feeding back said data according to a feedback algorithm; a threshold decoder/interference canceler for receiving video data from said main memory, dividing the received video data into multiple levels according to a threshold level algorithm, and additionally having an interference cancellation algorithm so as to cancel interference.

7. A video signal main processing method for a radar system comprising the steps of: converting an analog video signal into a digital video signal; summing data fed back according to a feedback algorithm previously set depending upon PRF, clutter and noise conditions, and current pulse repetition period data; storing the summed result; dividing video data into multiple levels according to a threshold level algorithm previously set depending upon said PRF and clutter and noise conditions, and outputting the divided video data; and converting said divided video outputs into a display signal.

8. A video signal main processing method for a radar system substantially as hereinbefore described with reference to the accompanying drawings.

9. A video signal processor for a radar system comprising means for digitising a received radar signal, means for storing said digitised radar signal and means for feeding back values of the digitised radar signal to affect later values of said digitised radar signal, so as to perform a leaky integration process.

10. A radar signal processor comprising means for reducing radar clutter and noise in a received radar signal so as to provide a substantially constant false alarm rate.