GB2273201A - High reliability contact scheme - Google Patents

High reliability contact scheme Download PDF

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Publication number
GB2273201A
GB2273201A GB9219856A GB9219856A GB2273201A GB 2273201 A GB2273201 A GB 2273201A GB 9219856 A GB9219856 A GB 9219856A GB 9219856 A GB9219856 A GB 9219856A GB 2273201 A GB2273201 A GB 2273201A
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Prior art keywords
contact
layer
barrier layer
forming
scheme according
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Granted
Application number
GB9219856A
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GB9219856D0 (en
GB2273201B (en
Inventor
George William Punter
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Texas Instruments Ltd
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Texas Instruments Ltd
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Publication of GB2273201A publication Critical patent/GB2273201A/en
Application granted granted Critical
Publication of GB2273201B publication Critical patent/GB2273201B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

A high reliability contact scheme is provided for electronic devices such as heterojunction bipolar transistors used in cell phones. A multilayer contact scheme is etched and patterned to produce an upper level (26) of power resistance conductor material, such as gold, contacting a lower barrier layer (14) of higher resistance material through an interviewing insulating layer (16) of air or inorganic or organic material. The higher resistance material may be titanium, palladium, germanium, indium, titanium tungstenate, tungsten silicide or an alloy of any of these. A direct interface between the lower resistance conductor material and the semiconductor material of the transistor is thus eliminated. <IMAGE>

Description

HIGH RELIABILITY CONTACT SCHEME This invention relates to a High Reliability Contact Scheme for electronic devices.
There are many known contacting schemes used in the production of electronic devices.
These schemes are used to make electrical contact between the electronic device in question and other circuit elements. Most contacting schemes have limitations which can result in poor performance in certain applications.
Gallium Arsenide (GaAs) Heterojunction bipolar transistors (HBT) have been developed for high efficiency use at RF and microwave frequencies. GaAs HBTs can be used in communication systems for example, cellular telephones. In these applications it is important that the device is reliable. Certain prior contacting schemes have resulted in poor performance devices due to spiking at the junctions.
In general, contacting schemes to make electrical contact with the GaAs semiconducting layers have followed the techniques used in silicon processes. This has been to use a metallic layer which forms an ohmic contact with the GaAs but which will not react with or diffuse into the GaAS. This layer, which is usually of relatively high resistance, is then coated with another layer of low resistance metal, such as gold or aluminium, to reduce lead and contact series resistances thereby maintaining the device performance.
Testing over long periods of time and at elevated temperatures, of devices which have been made in this way, has shown the device parameters can degrade. The degradation in performance is generally attributed to the low resistance metai l ligrating into the GaAs through the ohmic contact layer by diffusion or by finding cracks ant oids and then spiking the junctions causing the loss in device performance.
The spiking problems are most significant in GaAs devices, although other types of devices, for example silicon devices, can also exhibit the same phenomenon.
Accordingly, although GaAs devices are described throughout, it is understood that the invention can relate to any type of electronic device in which a contact scheme might be utilised.
One object of the present invention is to provide a system which overcomes at least some of the disadvantages of known contacting schemes.
According to one aspect of the present invention, there is provided a contact scheme for a semiconductor device comprising a first conducting barrier layer connected to the device at one or more predetermined locations; a first insulation layer located on said barrier layer; a contact layer located on the insulating layer and contact means forming an electrical contact between the contact layer and the barrier layer at one or more predetermined points.
One of the advantages of this system is that the interface between the low resistance metal layers of the electrical contact and the semiconductor layers is eliminated. This means that migration and diffusion are minimised whilst maintaining a low electrical resistance between the semiconductor and other circuit elements.
According to a second aspect of the present invention there is provided a method of forming a contact scheme on a semiconductor device comprising the steps of forming a junction on said device, depositing a first insulation layer over said junction, forming contacts through said first insulation layer to said junction and forming a contact layer on said insulation layer which makes electrical contact with said contacts.
According to a third aspect of the present invention there is provided a contact scheme for an electronic device, comprising a multilayer structure of insulative and conductive layers, arranged to eliminate a direct path from the surface of the device to the outer layer of said structure, but capable of conducting electrically between said surface and said outer layer.
Reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is a schematic diagram showing a first contact scheme according to one embodiment of the present invention; Figure 2 is a schematic diagram showing a second contact scheme according to a second embodiment of the invention, and Figure 3 is a schematic diagram showing a third contact scheme according to a third embodiment of the present invention.
Like elements in the figures are indicated by the same reference numerals. Referring to figure 1, there is shown a surface 10 of, for example, a GaAs device 12. The surface 10 in use contacts an emitter or base finger, for example. The emitter (or base) is formed using a first barrier layer 14 which is applied in a photolithographic technique. This barrier layer is typically of a relatively high resistance metal such as, for example, Titanium, Palladium, Germanium, Indium, Titanium Tungsten, Tungsten Silicide or any alloy of these metals. This first layer must make a good ohmic contact with the underlying GaAs surface, and will be chosen accordingly.
Having formed the emitter (or base), a first layer of insulation 16 is laid over layer 14 in a standard depositionlphotolithographic technique. This insulation layer may be an organic or inorganic film, for example Silicon Nitride, Silicon Dioxide or Polyimide. As an alternative the insulation layer may be an airbridge.
The insulation layer is patterned and etched such that contact openings 18, 18' are produced in the layer allowing access to the first barrier layer below.
A second barrier layer 20 is then deposited over the insulation layer. In the contact openings 18, 18' electrical contact is made between layers 14 and 20. The second barrier layer 20 is then etched and patterned in a conventional way so that the layer is substantially as shown in the schematic drawings. That is to say that the second layer has roughly a uniform thickness after the first insulation layer 16 and the contact openings 18, 18'.
The second barrier layer can be of the same material as the first barrier layer.
Alternatively, the second barrier layer can be chosen for the thermal or electrical properties they exhibit if these considerations are necessary for a particular design.
A second insulation layer 22 is then applied to the second barrier layer 20. This insulation layer can be of any appropriate material such as those of the first insulation layer, for example. The second insulation layer is patterned and etched using a conventional photolithographic process such that contact openings 24, 24', 24" are produced in the second insulation layer. These contact openings expose a surface of the second barrier layer.
A final metal layer 26 is then applied over the second insulation layer and into the contact openings 24, 24', 24" such that electrical contact is made between the second barrier layer and the final metal layer. The final metal layer is typically of low resistance metal such as gold, for example.
The contacting scheme 28 ensures that a direct path from the GaAs of the device to the gold of the final metal layer is eliminated. In addition to this advantage, it would also be possible to dispense with some or all of the ballast resistors which may be used to stabilise of the device. This is due to the fact that the series resistance of the contact will be higher than in conventional contact schemes since the barrier layers are of relatively high resistivity metals.
The embodiment shown in figure 2, is substantially the same as that shown in figure 1.
However, the final metal layer 26 is substantially outside the device structure. This has the advantage of reducing the processing complexity of the contact scheme 28.
Clearly, each of the two above described embodiments could be varied in many ways, for example the number of contact openings 18, 24 may be different than that shown. In addition, the physical layout may be different as long as a direct path between the device and the final metal layer is eliminated or minimised.
The third embodiment in figure 3, is a less preferred embodiment but still ensures that the direct contact between the device and the final metal layer, if not eliminated, is minimised. In this embodiment, a single barrier layer 30 and a single insulation layer 32 lie between the final metal layer and the surface of the device. Electrical contact is made between the barrier layer and the final metal layer in contact openings 34, 34' in the insulation layer. A second insulation layer 36 may be applied to the contact scheme 38 if this is necessary.
The contact schemes 28, 38 described above may be adapted for use on Silicon, InGaAs (Indium Gallium Arsenide) or other types of semiconductor devices. Different choices of material may be appropriate in each of these circumstances.
The contact scheme can prevent moisture penetration when using non-hermetically packaged devices, due to the fact that the active part of the transistor is encapsulated in passivation (i.e. the insulation layer(s)).
An example of a contact scheme according to the invention is one in which the surface of the device is shielded from the outer contact layer (gold, for example) by an appropriate layer or layers.
A GaAs device having the above described contact scheme could be used in many applications, for example in telecommunications such as the cell phone. The device may be a HBT or any other type of semiconductor device adapted for the required application.

Claims (19)

1. A contact scheme for an electronic device, comprising a multilayer structure of insulative and conductive layers, arranged to eliminate a direct path from the surface of the device to the outer layer of said structure, but capable of conducting electrically between said surface and said outer layer.
2. A contact scheme for a semiconductor device comprising: a first conducting barrier layer connected to the device at one or more predetermined locations; a first insulation layer located on said barrier layer; a contact layer located on the insulating layer, and contact means forming an electrical contact between the contact layer and the barrier layer at one or more predetermined points.
3. A contact scheme according to claim 2, wherein the scheme further comprises a second conducting barrier layer on said first insulating layer and a second insulating layer located above said contact layer; wherein the contact means comprise a first set of contact means between the first barrier layer and the second barrier layer; and a second set of contact means between the contact layer and the second barrier layer.
4. A contact scheme according to claim 2 or claim 3, wherein the contact means comprise vias through the or each insulation layer.
5. A contact scheme according to any of claims 2 to 4, wherein the or each barrier layer comprises a relatively high resistance material.
6. A contact scheme according to any of claims 2 to 5, wherein the or each barrier layer comprises Titanium, Palladium, Germanium, Indium, Titanium Tungstenate, Tungsten Silicide or any alloy thereof.
7. A contact scheme according to any of claims 2 to 6, wherein the or each insulating layer comprises an inorganic film.
8. A contact scheme according to claim 7, wherein the inorganic film comprises a silicon compound.
9. A contact scheme according to any of claims 2 to 6, wherein the or each insulating layer comprises an organic film.
10. A contact scheme according to claim 9, wherein the organic film comprises a polyimide.
11. A contact scheme according to any of claims 2 to 6, wherein the insulation layer comprises an airbridge.
12. A contact scheme according to any of claims 2 to 11, wherein the contact layer is a relatively low resistivity metal.
13. A contact scheme according to any of claims 2 to 12, wherein the contact layer is gold.
14. A contact scheme substantially as described with reference to the accompanying drawings.
15. A semiconductor device including a contact scheme according to any preceding claim.
16. A semiconductor device according to claim 15 in the form of a Gallium Arsenide Heterojunction Bipolar Transistor (GaAs HBT).
17. A cell phone including a device according to claim 15 or claim 16.
18. A method of forming a contact scheme on a semiconductor device comprising the steps of: forming a junction on said device; depositing a first insulation layer over said junction; forming contacts through said first insulation layer to said junction; and forming a contact layer on said insulation layer which makes electrical contact with said contacts.
19. A method according to claim 18, furdler comprising the steps of: depositing a second barrier layer on said first insulation layer and forming an electrical contact between the second and first barrier layers; forming a second insulation layer over said second barrier layer; and forming second contacts through said second insulation layer to the second barrier layer, wherein said step forming a contact layer comprises forming a contact layer on said second insulation layer thereby making a second electrical contact with said second contacts.
GB9219856A 1992-09-18 1992-09-18 High reliablity contact scheme Expired - Fee Related GB2273201B (en)

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GB9219856A GB2273201B (en) 1992-09-18 1992-09-18 High reliablity contact scheme

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GB9219856A GB2273201B (en) 1992-09-18 1992-09-18 High reliablity contact scheme

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GB9219856D0 GB9219856D0 (en) 1992-10-28
GB2273201A true GB2273201A (en) 1994-06-08
GB2273201B GB2273201B (en) 1996-07-10

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2296375A (en) * 1994-12-19 1996-06-26 Korea Electronics Telecomm Fabricating hetro-junction bipolar transistors

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207808A (en) * 1987-06-19 1989-02-08 Mitsubishi Electric Corp Wiring for a semiconductor device
EP0335720A2 (en) * 1988-03-30 1989-10-04 Kabushiki Kaisha Toshiba Bipolar transistor device and method of manufacturing the same
US4897513A (en) * 1988-03-11 1990-01-30 Alps Electric Co., Ltd. Rotary switch
US4970574A (en) * 1988-05-31 1990-11-13 Nec Corporation Electromigrationproof structure for multilayer wiring on a semiconductor device
US5000818A (en) * 1989-08-14 1991-03-19 Fairchild Semiconductor Corporation Method of fabricating a high performance interconnect system for an integrated circuit
US5026664A (en) * 1988-04-07 1991-06-25 Hitachi, Ltd. Method of providing a semiconductor IC device with an additional conduction path

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207808A (en) * 1987-06-19 1989-02-08 Mitsubishi Electric Corp Wiring for a semiconductor device
US4897513A (en) * 1988-03-11 1990-01-30 Alps Electric Co., Ltd. Rotary switch
EP0335720A2 (en) * 1988-03-30 1989-10-04 Kabushiki Kaisha Toshiba Bipolar transistor device and method of manufacturing the same
US5026664A (en) * 1988-04-07 1991-06-25 Hitachi, Ltd. Method of providing a semiconductor IC device with an additional conduction path
US4970574A (en) * 1988-05-31 1990-11-13 Nec Corporation Electromigrationproof structure for multilayer wiring on a semiconductor device
US5000818A (en) * 1989-08-14 1991-03-19 Fairchild Semiconductor Corporation Method of fabricating a high performance interconnect system for an integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2296375A (en) * 1994-12-19 1996-06-26 Korea Electronics Telecomm Fabricating hetro-junction bipolar transistors
GB2296375B (en) * 1994-12-19 1998-06-24 Korea Electronics Telecomm Fabricating hetero-junction bipolar transistors

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Publication number Publication date
GB9219856D0 (en) 1992-10-28
GB2273201B (en) 1996-07-10

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 20070918