GB2271652A - Efficient computer system processing operations - Google Patents

Efficient computer system processing operations Download PDF

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Publication number
GB2271652A
GB2271652A GB9221496A GB9221496A GB2271652A GB 2271652 A GB2271652 A GB 2271652A GB 9221496 A GB9221496 A GB 9221496A GB 9221496 A GB9221496 A GB 9221496A GB 2271652 A GB2271652 A GB 2271652A
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United Kingdom
Prior art keywords
data
host
record
processing
transaction
Prior art date
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Granted
Application number
GB9221496A
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GB9221496D0 (en
GB2271652B (en
Inventor
Finn O'sullivan
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STELTON Ltd
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STELTON Ltd
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Priority to BE9200819A priority Critical patent/BE1004539A6/en
Application filed by STELTON Ltd filed Critical STELTON Ltd
Priority to GB9221496A priority patent/GB2271652B/en
Publication of GB9221496D0 publication Critical patent/GB9221496D0/en
Publication of GB2271652A publication Critical patent/GB2271652A/en
Application granted granted Critical
Publication of GB2271652B publication Critical patent/GB2271652B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/466Transaction processing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

A computer system (1) comprising a host computer (2) and an off-host microcomputer (8) which can be instructed to carry out transaction processing in an efficient manner. Efficient transaction processing is achieved by selection of on-host or off-host processing and by the off-host processor (8) communicating with remote computer systems via a modem (9). Efficient transaction processing is also ensured by writing of messages and processed data to a tracking record according to the nature of the message or processed data. In addition, transaction records are updated. Batch processing is carried out by reading flags corresponding to records and only loading and processing each record if necessary, as determined by the flag value. The flag file requires little memory capacity because cross-references are not required. <IMAGE>

Description

"Efficient Computer System Processing Operations" The invention relates to the carrying out of processing operations by a computer system for which there is shared access by many terminals to data and to processing facilities.
More particularly, the invention relates to the carrying out of processing operations for transactions on such a computer system in an efficient manner so that the chances of an interruption or data corruption occurring are minimised. The transactions may, for example, relate to van imports or exports where the job of moving cargo into a country or out of a country is regarded as one transaction or job. In any such transaction, there is a need to give the customer a guarantee of a delivery time which allows for relatively little transport time. These transport operations involve teamwork by people working on different transport stages such as delivery to port, shipping and local distribution. It is essential that these people have very quick and shared access to data and processing facilities.In such circumstances, a processing interruption delay or data corruption would cause considerable disruption. Because of the manner in which the different transport stages are dependent on each other, even a minor processing delay or interruption involving one transport stage would have a major downstream effect on the other stages.
There are several requirements for such processing operations on the host computer. One requirement is that users have access immediately to data so that they may determine immediately the status of any particular transaction, for example, the location and expected arrival time of an item of cargo. Another requirement is that the host computer be capable of handling all processing operations, even at peak processing times without delaying either enquiries or generation of transaction documents, such as shipping requisitions etc. A still further requirement is that batch processing involving the same operation being carried out on a large number of records be carried out efficiently.
European Patent Specification No. EP 445 456 B (Flavors Technology Inc.) discloses a parallel processing system having several processors which are interconnected. Such an arrangement would be suitable for the carrying out of parallel processing to achieve maximum efficiency. However, it has been found by carrying out processing in such a distributed manner, it is difficult to achieve the necessary control of processing operations where these operations relate to transactions involving data inputting and enquiry inputting from many different sources, both local and remote.
The invention is directed towards providing a computer system constructed to operate efficiently so that processing delays or interruptions are avoided. Another object is to minimise the chances of data corruption occurring.
According to the invention, there is provided a computer comprising a host computer connected to a storage device which is connected to a multi-protocol data switch which is in turn connected to at least one microcomputer and to a plurality of data communications controllers, wherein the host computer comprises the following processing circuits to allow efficient transaction processing; means for generating a transaction record in the storage device for each transaction, the transaction record being of variable length; means for generating a tracking record in the storage device, the tracking record being of variable length; means for monitoring incoming data for a particular parameter value to determine if its contents may be immediately written to the tracking record; means for monitoring incoming data to determine if on host or off-host processing may be carried out;; means for carrying out on-host processing according to programs stored on the storage device; an updating circuit for incrementing the transaction record size and up-dating the transaction record with data which has been processed on-host or off-host; means for determining if the processed data should be written to the tracking record; means for updating the tracking record; an on-host communications controller for transmitting received data to the off-host processor; means in the off-host processor for processing the data and converting its protocol and subsequently transmitting the data to a remote computer system; means in the off-host processor for repeatedly polling the remote system for a response; and means in the off-host processor for receiving a response from the remote computer system and processing the received data and for subsequently converting the protocol to the original protocol and transmitting the data to the host computer via the data switch.
Preferably, the computer comprises: means for generating a flag file having a flag value stored in sequence according to records within a record file; means for loading an index file into a memory circuit; means for reading flags of the flag file; means for retrieving a record index corresponding in sequential order to a flag if the flag has a pre-set value; and means for processing the record for which the index has been retrieved.
The invention will be more clearly understood from the following description of some preferred embodiments there of, given by way of example only with reference to the accompanying drawings in which: Fig. 1 is a schematic representation of a computer system of the invention; Fig. 2 is a flow chart illustrating the manner in which processing operations are carried out; and Fig. 3 is a flow chart illustrating the manner in which batch operations are carried out in an efficient manner.
Referring to the drawings, and initially to Fig. 1, there is illustrated a computer system of the invention indicated generally by the reference numeral 1. The system 1 comprises a host computer 2 which is of the superminicomputer type and which is connected to a bank of fixed disk drives 3. The host computer 2 is also connected to a multi-protocol data switch 4 by 180 cables 5. The data switch 4 includes an SNA/BISYNC protocol converter 15 connected to a modem 6 which is in turn connected to a leased line terminal node 7 providing a connection to a leased line for international communications.
The host computer 2 is also connected directly to a microcomputer 8, which is in turn connected to a modem 9 for switched line communications.
The host computer 2 has 64 MB of high speed memory and operates on a 32-bit processor bus. There is also a 32 KB associated cache memory. To provide good performance there are hardware-implemented instructions for quad-precision floating point operations. Although not shown in the drawing, there are numerous terminals both local and remote which may access the host computer 2 by lines 10 to instruct processing and to make data enquiries. This processing is to control transactions such as cargo handling. For such a use, reliability of the host computer 2 is essential and to achieve this it has been found that the processing capacity must be utilised to the maximum efficiency so that at all times data corruption is unlikely to occur.
The flow charts of Fig. 2 and 3 show the technical operations which are carried out by the host computer system 1 to ensure processing efficiency.
Referring initially to Fig. 2, in step 21 data is received from a terminal via the data switch 4 and the lines 5 or the lines 10. The host computer in step 22 monitors the data to determine if it includes data relating to a pre-set parameter, in this case information regarding progress of a particular transaction. If so, the host computer writes this to a tracking record which is of variable length and is contained within a tracking file, also of variable length. The tracking record will be of 5 to 10 KB size by the end of a transaction.
The host computer automatically updates the tracking record whenever messages are received to provide more information about a particular transaction. Accordingly, on an on-going basis requests from terminals for data relating to the tracking record parameter (i.e. cargo progress) may be made efficiently because it is not necessary to read the transaction record.
If the received data is not an information message, the host computer "knows" that a certain amount of processing, even if very basic, is required. In step 24, the host computer checks the category of data and the transactions to which it relates and decides if on-host or off-host processing should take place. If off-host, the host computer transmits the data to the microcomputer 8 which acts as an off-host processor. The microcomputer 8 processes the data in order to generate data which either generates an output for the transaction or provides useful information for enquiries received. This processed data is then converted to the ASCII protocol for a remote computer system and is transmitted in step 27 via the modem 9.At regular intervals of 5 secs. the microcomputer 8 transmits a polling signal to the remote computer system to check for a response and in step 29 the response is received and is processed according to stored programs on the microcomputer 8. When processing is complete, the microcomputer 8 converts the processed data to the host computer proprietary protocol and transmits the data to the host computer 2. The host computer 2 on an on-going basis monitors the input ports for data being received via the lines 5, as indicated by the step 31.
If, however, the received data is required to be processed on the host computer 2, in step 32 this processing takes place under the control of programs retrieved from the fixed disk drives 3. In step 33, the host computer 2 increments the size of a transaction record which is used for all data relating to the particular transaction. This is not to be confused with the tracking record which stores information relating to a particular parameter of the transaction, in this case transport progress. For example, in van imports and exports of cargo, the tracking record stores data relating to present location and expected arrival time of cargo being handled.
The transaction record on the other hand stores all data relating to that cargo such as customs and tax data. In step 34, the host computer decides whether or not the action represented by the processed data is required for the tracking record, and if so it in parallel writes the data to the transaction record in step 35 and to the tracking record in step 36. If writing to the tracking record is not required, it only writes the data to the transaction record in step 35.
At any time after an occurrence of steps 35 and 36, in step 37, the host computer provides the option of carrying out batch processing under instructions from a user. If no such instruction is received, steps 21 to 36 are repeated for the next item of data which is received. When an instruction is received for the carrying out of a batch process, this is carried out in step 38, which is illustrated in detail in Fig.
3.
In step 41, the host computer monitors whether or not a flag file which has previously been generated is in sequence. Each flag of this file is related to a record. In general, for records of one particular type such as van import or export records for one particular customer, there will be a single flag file containing a flag for each of these records. The flag file indicates the parameter of the record.
An example of a parameter is whether or not there is a balance outstanding on invoices stored in the record.
If the flag file is out of sequence, in step 42 the host computer reads the first record and sets a flag value in step 43 according to the relevant parameter value. As determined by step 44 this is repeated for each record of that particular category until the flag file has been generated with all flags having a correct value and being in sequence with records.
The flag file only contains flags and these are stored in the same sequence as the records in the record file. Thus, there is no need for a cross reference in the flag file to the record file. For example, the flag stored 10th in sequence in the flag file corresponds to the 10th record in the record file.
When the flag file has been generated and is in correct sequence, in step 45 the host computer loads into memory an index file for the set of records. Subsequently, in a single processing cycle it reads the first flag in the flag file in step 46. The record which is loaded may be a data record or alternatively an index record providing a reference to a set of data records. In step 47 the host computer determines the flag value and if high, no action is taken, the processing cycle is complete and step 46 is repeated for the next record.
However, if the flag value is low, in step 49 the host computer retrieves the record index having the same sequential occurrence as the flag. In step 50, the relevant record is loaded into memory and processes according to the relevant program. It is not until this record has been processed that the processing cycle is complete. In carrying out these operations, the host processor operates according to processing cycles and at any one time there is a particular index file loaded into the memory, together with a flag. It will be appreciated that because it is only necessary to read the flag value in most cycles, a considerable amount of processing time is saved as the alternative would be to not only load, but to read each record in turn to determine whether or not processing of the particular data value is required. It is considerably faster to simply check a flag value to determine whether or not the record should be processed. It will be appreciated that if such a batch process is carried out at the same time as general transaction processing, there will be very small chance of delays or interruption occurring in the transaction processing.
It will be appreciated that the invention provides for efficient use of host computer processing capacity by simple use of off-host processors and by use of a tracking record and the manner in which this is used. Further, the processing of a flag file saves considerable processing time for batch processing.
The invention is not limited to the embodiments hereinbefore described, but may be varied in construction and detail.

Claims (3)

1. A computer system comprising a host computer connected to a storage device which is connected to a multi protocol data switch which is in turn connected to at least one microcomputer and to a plurality of data communications controllers, wherein the host computer comprises the following processing circuits to allow efficient transaction processing; means for generating a transaction record in the storage device for each transaction, the transaction record being of variable length; means for generating a tracking record in the storage device, the tracking record being of variable length; means for monitoring incoming data for a particular parameter value to determine if its contents may be immediately written to the tracking record; means for monitoring incoming data to determine if on-host or off-host processing may be carried out;; means for carrying out on-host processing according to programs stored on the storage device; an updating circuit for incrementing the transaction record size and up-dating the transaction record with data which has been processed on-host or offhost; means for determining if the processed data should be written to the tracking record; means for updating the tracking record; an on-host communications controller for transmitting data to the off-host processor; means in the off-host processor for processing the data and converting its protocol and subsequently transmitting the data to a remote computer system; means in the off-host processor for repeatedly polling the remote system for a response; and means in the off-host processor for receiving a response from the remote computer system and processing the received data and for subsequently converting the protocol to the original protocol and transmitting the data to the host computer via the data switch.
2. An computer system as claimed in claim 1, further comprising: means for generating a flag file having a flag value stored in sequence according to records within a record file; means for loading an index file into a memory circuit; means for reading flags of the flag file; means for retrieving a record index corresponding in sequential order to a flag if the flag has a pre-set value; and means for processing the record for which the index has been retrieved.
3. A computer system substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
GB9221496A 1992-09-18 1992-10-13 Efficient computer system processing operations Expired - Fee Related GB2271652B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
BE9200819A BE1004539A6 (en) 1992-09-18 1992-09-18 Operations effective treatment by a computer system.
GB9221496A GB2271652B (en) 1992-09-18 1992-10-13 Efficient computer system processing operations

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
BE9200819A BE1004539A6 (en) 1992-09-18 1992-09-18 Operations effective treatment by a computer system.
GB9221496A GB2271652B (en) 1992-09-18 1992-10-13 Efficient computer system processing operations

Publications (3)

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GB9221496D0 GB9221496D0 (en) 1992-11-25
GB2271652A true GB2271652A (en) 1994-04-20
GB2271652B GB2271652B (en) 1996-02-21

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GB9221496A Expired - Fee Related GB2271652B (en) 1992-09-18 1992-10-13 Efficient computer system processing operations

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GB9221496D0 (en) 1992-11-25
BE1004539A6 (en) 1992-12-08
GB2271652B (en) 1996-02-21

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Effective date: 19991013