GB2271639A - Eliminating periodic interference from measurement signals - Google Patents

Abstract

Periodic (eg mains) interference is eliminated from a periodic data-carrying signal which is derived from an excitation signal as in an electromagnetic flowmeter, by selecting the frequency of the excitation signal such that ite = 2nti where te is the period of the excitation signal, ti is the period of the interference, i is an odd integer and n is an integer, delaying at least one half-cycle of the data signal by a time nti relative to the next succeeding half-cycle of the data signal and processing the said data signal half-cycles in combination to eliminate the periodic interference therefrom. As shown, pulse drive electromagnetic flowmeter 18 excited by pulses of period te, is subject to interference of period ti. te is made to equal 4t, ie i=1 and n=2. The sensor output is passed through two delays 42, 48 each of 2ti. Signals A and C are passed directly to summing circuit 40 and signal B is inverted and amplified by amplifier 46 with gain -2 before reaching the summing circuit, the output of which is fed to switched demodulator 52. The demodulator output is free from both interference and baseline drift. <IMAGE>

Description

Method and Apparatus for Interference Reduction This invention relates to a method and apparatus for reduction of periodic interference in data-carrying signals produced from or otherwise dependent upon a periodic energising or excitation signal.

The invention is particularly but not exclusively applicable to electromagnetic flow meters, and will be described in that context.

Pulsed drive electromagnetic flow meters rely upon Faraday's law, i.e. the voltage induced across a conductor as it moves at right angles through an electromagnetic field will be proportional to the velocity of that conductor. In the case of an electromagnetic flowmeter the conductor is the fluid and its velocity is inferred from the voltage induced across the flowing fluid.

With a pulse drive electromagnetic flowmeter the designer has control over the energisation of the electromagnetic field. Usually the energising coils are driven at a constant current with alternating polarities, the frequency of which is under control of the designer.

The signal levels from the flowing fluid are normally very low, ranging from nanovolts to a few millivolts, and consequently interference rejection is very important. It is the rejection of periodic interference, such as mains power related interference, which is the subject of this invention.

Mains frequency interference may arise for example from pump or other machinery drives in the vicinity of the flow meter, and thus is likely to be a problem in many industrial environments in which such flow meters may be installed.

The invention also addresses the problem of the so-called "wandering baseline". This problem arises due to the unpredictable generation of DC voltages across the sensing electrodes of the flowmeter. These voltages may be caused for example by electrostatic charges developing in the fluid as a result of impurities (eg. chalk in water) and discharging to the electrodes. They also may be produced electrolytically when the flow of an ionic fluid is being measured.

Recalibration or compensation of the flowmeter thus may be necessary.

According to the invention, there is provided a method of eliminating periodic interference from a periodic data-carrying signal which is derived from an excitation signal comprising selecting the frequency of the excitation signal such that ite = 2nti where te is the period of the excitation signal, ti is the period of the interference, i is an odd integer and n is an integer, delaying at least one half-cycle of the data signal (as herein defined) by a time nti relative to the next succeeding half-cycle of the data signal and processing the said data signal half-cycles in combination to eliminate the periodic interference therefrom.

The term "half-cycle of the data signal" includes not only the complete half-cycle of the data signal but also a sample of that half-cycle or any other signal derived from and representative of that half-cycle. References to succeeding, preceding or adjacent half-cycles of the date signal include corresponding samples and derived signals obtained from those half-cycles.

In said signal processing, successive half-cycles of the data signal of one polarity may be subtracted from successive half-cycles of the data signal of opposite polarity.

It will be understood that the term "polarity" is used with reference to a baseline which due to DC offset may not be zero. Thus half-cycles of the data signal whilst alternately positive-going and negative-going relative to the baseline (and thus of opposite polarity relative thereto) may not be of opposite polarity in absolute terms.

Fewer half-cycles of one polarity may be processed than half-cycles of the other polarity, the signal processing then including weighting the half-cycles so that said subtraction is performed using quantities representative of an equal number of half-cycles.

One embodiment includes subtracting one said half-cycle from the immediately adjacent (in time) half-cycle of the data signal.

In another embodiment the subtraction is performed between the sum of two successive half-cycles of one polarity and twice the intervening half-cycle of opposite polarity.

Each of the at least two half-cycles may be sampled such that each sample has the same phase relationship to the half-cycle in which it occurs as does a corresponding sample taken in another half-cycle.

A plurality of samples may be taken from each of the at least two successive half-cycles.

Samples taken during the rise or fall times of the data signals may be weighted.

Preferably the value of i is 9 or less.

Preferably the value of n is 10 or less.

The invention also provides apparatus for eliminating periodic interference from a periodic data-carrying signal which is derived from an excitation signal comprising means for generating the excitation signal at a frequency such that ite = 2nti where te is the period of the excitation signal, ti is the period of the interference, i is an odd integer and n is an integer, means for delaying at least one half-cycle of the data signal by a time nti relative to the next succeeding half-cycle of the data signal, and means for processing the data signal half-cycles in combination to eliminate the periodic interference therefrom.

The invention now will be described merely by way of example with reference to the accompanying drawings, wherein: Figure 1 is a diagrammatic cross-section of a typical electromagnetic flow meter.

Figure 2 shows an data signal waveform of a conventional flow meter.

Figure 3 illustrates the principle of wandering baseline rejection.

Figure 4 illustrates the principle of the present invention.

Figure 5 shows apparatus in accordance with one embodiment of the invention.

Figures 6 and 7 show apparatus according to further embodiments of the invention, and Figure 8 illustrates a further aspect of the data signal processing.

Referring to Figure 1, a pipe 10 contains flowing fluid and has positioned around it a flowmeter head consisting of coils 12 and a ferromagnetic core 14. When a periodic excitation signal is applied to the coils 12 a magnetic field 16 is generated through the fluid. The direction of the field reverses each time the polarity of the excitation signal changes. The movement of the fluid through the magnetic field generates a voltage between sensor electrodes 18, the polarity of which also changes with that of the excitation signal. The electrodes also pick-up interference signals and parasitic voltages as already described.

Referring to Figure 2, a diagrammatic output of the electrodes 18 consists of an amplitude-modulated alternating signal 20 ideally approximating to a square wave with rises and falls 24,26 relatively short compared to the period of the signal. The amplitude of the signal 20 is a function of the velocity of the fluid through the pipe 10.

Typically the excitation signal and the resulting data-carrying (flow velocity) signal 20 have a frequency fe of a few cycles to a few tens of cycles per second.

Superimposed on the signal 20 is mains frequency interference 28 which conventionally is removed by integrating samples of the signal 20 over a period equal to one or more complete cycles of interference, thereby reducing the DC value of the interference to zero. The minimum integration period is thus 20ms for for 50Hz interference and 16.67ms for 60Hz. Commonly, integration is performed over a lOOms period thereby rejecting both 50Hz and 60Hz. The sampling and integration periods, although of constant duration from half-cycle to half-cycle of the data signal bear no constant phase relationship thereto, as shown to an exaggerated extent in Figure 2.

To remove spurious DC voltages it is also known to combine the samples of the data signal from two or preferably three consecutive half-cycles A, B, C of the data signal 20. Then, subtracting samples from two consecutive half-cycles, SA - SB - (1) will remove a constant DC bias but not a ramp; referring to Figure 3, a weighted combination SA - 25B + Sc - (2) will remove also a linear DC ramp from a data signal 20 derived from excitation signal 30.

These known methods however have the disadvantage of requiring long integration periods and consequently low excitation frequencies, which worsens the effects of wandering baseline. Also, it will be appreciated that the rises and falls 24, 26 of the data signal 20 may be exponential rather than linear, and depend on the inductive time constant of the apparatus. It is necessary to delay sampling the signal 20 for perhaps ten time constants in order to avoid the temperature-sensitive rises and falls and achieve a steady state signal to within 0.1%. This further limits the freedom to use relatively high excitation frequencies in known devices.

Referring to Figure 4, an embodiment of the present invention has the frequency fe of excitation signal 30 chosen relative to the frequency fi of interference signal 28 such that i/fe = 2n/fi or since t = i/f ite = 2nti - (3) where i and n are integers, i being odd, and te and ti are the cyclic periods of the excitation and interference signals. In this example i = 1 and n = 2.

If the data signal is passed through a series of nti delays then equation (3) ensures that implementing equation (2) will cancel all periodic interference of frequency fi and its harmonics, and will also remove "wandering baseline".

There is considerable freedom in the choice of sampling rate, which need bear no relationship to the interference frequency. For example, the sampling rate may be of the order of 1 KHz The method may equally be applied with low sampling rates. It is preferable that the samples should be taken from the same point in each half cycle of the drive signal so as to have the same phase relationship thereto. In a simple analogue embodiment, if some temperature dependence in the output can be tolerated each half-cycle of the data signal 20 may be measured continuously throughout its duration.

The method is not dependent upon equation (2); it may be applied using equation (1), and will remove a constant DC offset but will not reject a linear DC ramp on the signal 20. Nevertheless, because the frequency of the data signal 20 is effectively higher than in known techniques, the effect of DC baseline drift from half-cycle to half-cycle is reduced.

Referring to Figure 5, in a continuous measurement analogue apparatus according to the invention an excitation signal generator 31 produces the excitation signal 30 which drives the flow meter sensor 18 of Figure 1. The output from sensor 18 (amplitude-modulated data signal 20 including interference 28) is passed continuously via line 39 to a summing circuit 40 and also to a delay 42, which imposes a delay of nti, equal to ite/2, i in this case being unity. The output of delay 42 is passed to the summing circuit 40 via line 44 and an inverting amplifier 46 with a gain of -2. The output also is fed to a further nti delay 48, the output of which is fed to the summing circuit 40 via line 50.The delays 42 and 48 by each delaying the data signal 20 by half a cycle of the signal 20 result in the inputs on lines 39, 44 and 50 being respectively representative of the successive half-cycles A, B and C of Figure 4. The inputs to the summing circuit 40 are thus SA-2 Sg + Sc, implementing equation (2) above.

The output of the summing circuit has a frequency fe. It is fed to a switched demodulator 52 directly and via an inverting amplifier 53.

The demodulator, clocked by the excitation signal 30 via line 54, demodulates (rectifies) the summing circuit output and (after smoothing if necessary) provides a DC signal indicative of the flow velocity.

Figure 6 shows a modification of the apparatus of Figure 5.

Corresponding features have the same reference numerals. In this embodiment there are three cascaded ite delays 42, 48, 60, the outputs of the first and third delays 42, 60 being fed via inverters 64, 66 to the summing circuit 40, the undelayed signal 20 and the output of delay 48 passing without inversion to the summing circuit 40. The input to the circuit 40 is then SA - Sg + So - SD, where A, B, C and D are consecutive half-cycles of the data signal 20.

The number of delays can be further expanded if desired, the outputs of alternate delays being inverted. If the number of delays is such that there are an odd number of inputs to the summing circuit 40, one of those inputs is amplified by a factor of 2 (eg as in inverting amplifier 46 of Figure 5) so that the weighted sum of inverted and uninverted inputs is equal.

Figure 7 shows a further modification of the Figure 5 apparatus, the same reference numerals again being used for corresponding features.

In this embodiment, the data signal 20 is sampled at a suitable rate (eg. 100-200 Hz) in each half-cycle and digitised by analogue-to-digital converter 68. The digital samples are fed to summing circuit 40 and to a parallel shift register 70 which imposes a delay nti. The delayed samples pass to the summing circuit 40 either via inverting x2 multiplier 46 or via a further nti-delaying parallel shift register 72. The inputs to summing circuit 40 thus again implement equation (2).

The output of the summing circuit which alternates between + and values at frequency fe passes to a multiplier 74 which also receives a +1 signal representative of the excitation signal. The multiplier output thus provides a single-signed digital output representative of the flow velocity which can be converted to an analogue signal by digital-to-analogue converter 76 or utilised in its digital form.

As described the Figure 7 embodiment is asynchronous; the A/D converter 68 and the shift registers 70, 72 may be phase-locked to the excitation signal generator 30 by controlling them all from a common clock 78.

The following table shows suitable excitation frequencies rejecting 50Hz interference (ti = 20ms) for 1 s n S 5 and 1 S i S 7. Selecting n = 5 and i = 1 or 3 has been found particularly convenient.

n 1 2 3 4 5 fe te fe te fe te fe te fe te 1 25 40 12.5 80 8 120 6.25 160 5 200 3 75 13.3 37.5 26.7 25 40 18.8 53.3 15 66.7 5 125 8 62.5 16 41.7 24 31.25 32 25 40 7 175 5.7 87.5 11.4 58.5 17.1 43.7 22.9 35 28.6 It will be seen that for some combinations of i and n, the excitation frequency is greater than the interference frequency. This enables the flowmeter to operate faster (especially on small pipes of lower inductance) and take advantage of modern signal processing techniques. However even with low inductance pipes high excitation frequencies result in the exponential rises and falls of the data signal occupying much of each cycle. If the data signal is subject to discrete sampling during a substantial proportion of each half-cycle as shown at 80, 82 in Figure 8, those samples 84 taken from rising or falling parts of the signal (which hitherto would have been discarded) may have digital processing applied to them to perform advanced signal recovery and compensation. For example they may be weighted to normalise them with those taken from mature portions of the cycle.

Claims (19)

1. A method of eliminating periodic interference from a periodic data-carrying signal which is derived from an excitation signal comprising selecting the frequency of the excitation signal such that ite = 2nti where te is the period of the excitation signal, ti is the period of the interference, i is an odd integer and n is an integer, delaying at least one half-cycle of the data signal (as herein defined) by a time nti relative to the next succeeding half-cycle of the data signal and processing the said data signal half-cycles in combination to eliminate the periodic interference therefrom.

2. A method as claimed in Claim 1, wherein in said signal processing, successive half-cycles of the data signal of one polarity are subtracted from successive half-cycles of the data signal of opposite polarity.

3. A method as claimed in Claim 2, wherein fewer half-cycles of one polarity are processed than half-cycles of the other polarity, the signal processing including weighting the half-cycles so that said subtraction is performed using quantities representative of an equal number of half-cycles.

4. A method as claimed in Claim 1, including subtracting one said half-cycle from the immediately adjacent (in time) half-cycle of the data signal.

5. A method as claimed in Claim 3, wherein subtraction is performed between the sum of two successive half-cycles of one polarity and twice the intervening half-cycle of opposite polarity.

6. A method as claimed in any preceding claim, wherein each of the at least two successive half-cycles are sampled such that each sample has the same phase relationship to the half-cycle in which it occurs as does a corresponding sample taken in another half-cycle.

7. A method as claimed in any preceding claim, wherein a plurality of samples are taken from each of the at least two successive half-cycles.

8. A method as claimed in any preceding claim, wherein i is 9 or less.

9. A method as claimed in any preceding claim wherein n is 10 or less.

10. Apparatus for eliminating periodic interference from a periodic data-carrying signal which is derived from an excitation signal comprising means for generating the excitation signal at a frequency such that ite = 2nti where te is the period of the excitation signal, ti is the period of the interference, i is an odd interger and n is an integer, means for delaying at least one half-cycle of the data signal by a time nti relative to the next succeeding half-cycle of the data signal, and means for processing the data signal half-cycles in combination to eliminate the periodic interference therefrom.

11. A method of or apparatus for eliminating periodic interference from a data-carrying signal substantially as herein described with reference to Figures 4 to 8 of the accompanying drawings.

Amendments to the claims have been filed as follows 11. Apparatus as claimed in Claim 10, wherein the data signal processing means is arranged to subtract successive half-cycles of the data signal of one polarity from sucessive half-cycles of the data signal of opposite polarity.

12. Apparatus as claimed in Claim 11, wherein the data signal processing means is arranged to process fewer half-cycles of one polarity than half-cycles of the other polarity, and to weight the half-cycles so that said subtraction is performed using quantities representative of an equal number of half-cycles.

13. Apparatus as claimed in Claim 10, wherein data processing means is arranged to subtract one said half-cycle from the immediately adjacent (in time) half-cycle of the data signal.

14. Apparatus as claimed in Claim 12, wherein the data signal processing menas is arranged to perform subtraction between the sum of two successive half-cycles of one polarity and twice the intervening half-cycle of opposite polarity.

15. Apparatus as claimed in any of Claims 10 to 14, comprising means for sampling each of the at least two successive half-cycles such that each sample has the same phase relationship to the half-cycle in which it occurs as does a corresponding sample taken in another half-cycle.

16. Apparatus as claimed in any preceding claim, wherein the sampling means takes a plurality of samples from each of the at least two successive half-cycles.

17. Apparatus as claimed in any of Claims 10 to 16, wherein i is 9 or less.

18. Apparatus as claimed in any of Claims 10 to 17, wherein n is 10 or less.

19. A method of or apparatus for eliminating periodic interference from a data-carrying signal substantially as herein described with reference to Figures 4 to 8 of the accompanying drawings.