GB2270795A

GB2270795A - Trimming integrated circuits

Info

Publication number: GB2270795A
Application number: GB9219833A
Authority: GB
Inventors: David William Eddowes
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1992-09-18
Filing date: 1992-09-18
Publication date: 1994-03-23
Anticipated expiration: 2012-09-18
Also published as: GB2270795B; GB9219833D0

Abstract

A method for trimming an integrated circuit employs an enhancement mode MOS field effect transistor 8 having its gate connected to its source. As fabricated the source to drain resistance of the transistor is high. A setting voltage, higher than that normally applied to the transistor, can be applied to the drain of the transistor via a terminal 5 to rupture the gate oxide between the drain and the gate so that the source to drain resistance becomes low. The change from high to low resistance of the transistor is used to effect the trimming. A diode or a bipolar transistor 10 may be provided in the connection from the drain of the MOS transistor to the other parts of the circuit in order to block the setting voltage and prevent it from damaging those other parts. <IMAGE>

Description

IMPROVEMENTS IN OR RELATING TO THE TRIMMING OF INTEGRATED CIRCUITS The present invention relates to the trimming of integrated circuits and in particular to the permanent adjustment of one or more values, for example of voltages or resistances, in such a circuit by selectively altering the impedances of devices in the circuit.

Previously a device used in trimming integrated circuits was a zener diode. Such a device normally has a high impedance under certain circuit conditions but on the application of a sufficiently large electrical signal can be made to be permanently short circuited, that is to say damaged by the signal so that the impedance of the device is greatly reduced under those certain circuit conditions.

This approach has two main advantages. First, the damage to the zener diode takes place below the surface of the semiconductor substrate and is irreversible and therefore may be carried out after further layers, for example of passivation, have been added to the integrated circuit.

Indeed a zener diode can be blown after the integrated circuit has been encapsulated in its package. Secondly, the fact that zener diodes have initially a high impedance and are blown to a low impedance has the advantage that the result of blowing the diode to its low impedance form can be simulated by temporarily short circuiting the device, which might be achieved conveniently by making a link externally to the integrated circuit. The circuit will then function as if the diode were blown. If the required condition is obtained the short circuit can be made permanent by blowing the zener diode.

Unfortunately zener diode trimming is not suitable for application to integrated circuits constructed by MOS technology as further process steps, additional to those needed for the MOS transistors, would be required to fabricate the diodes. Because of that disadvantage, MOS integrated circuits usually employ polysilicon fuses for trimming purposes. These do not have either of the advantages of zener diodes mentioned above. Polysilicon fuses initially have a low impedance and can be blown open circuit by the application of a sufficiently large electrical signal, which melts the polysilicon. To ensure a break in the polysilicon between the terminals of the fuse the material must be allowed to disperse when the fuse is blown otherwise it may reform to provide again a conductive path. between the terminals of the fuse.

Dispersal is facilitated by opening windows in the layer(s) above the fuse, including the passivation layer. Such windows in the passivation layer must be filled in afterwards if the chip is to be fully protected, and as a consequence such polysilicon fuses cannot be blown after the integrated circuit has been encapsulated in its package. It follows, therefore, that trimming of an integrated circuit by means of polysilicon fuses must be done during manufacture of the integrated circuit and cannot take into account any alteration of its characteristics arising from its packaging.

Since polysilicon fuses are blown from a low impedance condition to a high impedance condition rather than from a high impedance condition to a low impedance condition, there is no simple method of simulating the effect of blowing a fuse as there is with zener diodes as mentioned above.

It is an object of the present invention to enable the trimming of an integrated circuit which provides the advantages of blowing from a high impedance condition to a low impedance condition, of requiring no additional process steps in the manufacture of the integrated circuit constructed by an MOS fabrication process, and of allowing the trimming to be done after the integrated circuit has been encapsulated.

According to one aspect of the present invention there is provided a trimming circuit for an integrated circuit including first and second conductors respectively carrying first and second voltages, an enhancement mode MOS transistor having a source and a gate connected to the second conductor and a drain connected to the first voltage conductor through an impedance, the first voltage being different from the second voltage, and means for selectively applying to the drain of the MOS transistor a setting voltage which is sufficiently large relative to the second voltage to rupture the gate oxide of the transistor so as to connect the drain to the gate through a low impedance, the circuit being such that if the setting voltage has not been applied to the drain of the transistor then the drain is at a voltage close to the first voltage, and if the setting voltage has been applied to the drain of the transistor then, after the setting voltage has been removed, the drain is at a voltage close to the second voltage.

The trimming circuit may include a protection circuit connected between the drain and the impedance, the protection circuit serving to block the setting voltage from reaching the impedance and other components to which the trimming circuit is connected. The protection circuit may include a diode or a bipolar transistor.

The trimming circuit may include an inverting buffer stage receiving its input either directly from the drain of the MOS or from that drain through the protection circuit.

According to a second aspect of the invention there is provided a method of trimming an integrated circuit including providing in the integrated circuit an enhancement mode MOS transistor having a drain connected to a first voltage through an impedance and a source and a gate connected to a second voltage, the second voltage being different from the first voltage, and selectively applying to the drain of the MOS transistor a setting voltage sufficiently large relative to the second voltage to rupture the gate oxide of the transistor so as to connect the drain to the gate through a low impedance, so that if the setting voltage has not been applied to the drain of the transistor then the drain is at a voltage close to the first voltage, and if the setting voltage has been applied to the drain of the transistor then after the removal of the setting voltage the drain is at a voltage close to the second voltage.

A trimming circuit for an integrated circuit will now be described, by way of example only, with reference to the accompanying drawings, of which: FIGURE 1 is a circuit diagram of a trimming circuit according to the present invention; and FIGURE 2 is a circuit diagram of a trimming circuit which is a modification of that of Figure 1, The circuit of Figure 1 comprises two power supply conductors 1,2, two bias terminals 3,4, a rupture supply terminal 5, two enhancement mode pMOS transistors 6,7, two enhancement mode nMOS transistors 8,9, a two-collector lateral pnp bipolar transistor 10 and an output terminal 11, which are connected together as follows: The source and substrate terminals of the first pMOS transistor 6 are connected to the first supply conductor 1; its gate is connected to the first bias terminal 3 and its drain to a first node 12. The first node 12 is also connected to the emitter of the pnp transistor 10. The base and the first collector of the pnp transistor 10 are both connected to a second node 13, and its second collector is connected to the second power supply conductor 2. The drain of the first nMOS transistor 8 is connected to the second node 13; its gate, source and substrate terminal are all connected to the second power supply conductor 2. The rupture supply terminal 5 is connected to the second node 13.

The second pMOS transistor 7 has its source and substrate terminal connected to the first power supply conductor 1, its gate to the first node 12 and its drain to a third node 14. The second nMOS transistor 9 has its drain connected to the third node 14, its source and substrate terminal to the second power supply conductor 2 and its gate to the second bias terminal 4. The output terminal 11 is also connected to the third node 14.

The circuit of Figure 1, when supplied with a suitable voltage across the supply conductors 1,2, with suitable bias voltages to the bias terminals 3,4 and when there is no connection made to the rupture terminal 5, will, depending on whether or not the first nMOS transistor 8 has been ruptured, respectively give a "high" output on the terminal 11 substantially equal to the voltage on the supply conductor 1 or a "low" output substantially equal to the voltage on conductor 2. A suitable voltage across the power supply conductors 1,2 is that normally used for CMOS circuits, namely 5 volts, with conductor 1 being more positive than conductor 2. Hereinafter voltages substantially equal to that on the first power supply conductor 1 and that on the second power supply conductor 2 will be known as "high" and "low" respectively.

When the circuit is first constructed the gate oxide of the first nMOS transistor 8 is complete so that its gate is isolated from its channel. Because the gate is connected to the same voltage as the source and substrate of the (enhancement mode) transistor 8, that of the power supply conductor 2, the transistor 8 is not conducting, with the result that it appears as a high impedance from its drain, connected to the node 13. As a consequence of the high impedance of the transistor 8 very little current will tend to flow through the bipolar transistor 10, which as connected operates as a diode. The pMOS transistor 6, on the other hand, is conducting because the bias voltage on the terminal 3 which is connected to the gate of the transistor 6 is so chosen that the transistor 6 conducts.

Under the conditions just described the voltage at the node 12 is "high", being substantially equal to that on the conductor 1.

Rupture of the first nMOS transistor 8 is effected by applying a relatively large setting voltage, positive with respect to that present at terminal 2 to the rupture terminal 5. As mentioned above, the channel of the transistor 8 is not conductive and so the setting voltage applied to the terminal 5 will appear between the drain and the gate of the transistor 8, that is to say across the gate oxide. The gate oxide is made to be thin so that the MOS transistors have high gain and because it is thin it can be broken down and permanently ruptured by a setting voltage which can be as low as only 20 volts.Here, because the channel of the transistor 8 is not conductive, the greatest voltage difference across the gate oxide will occur between the gate and the drain end of the channel, with the result that the oxide will rupture there when the setting voltage is applied to provide a permanently conducting path between the drain and the gate and therefore between the second node 13 and the second power supply terminal 2.

The pnp transistor 10, connected as shown in Figure 1, acts as a diode, allowing current to flow from the first node 12 to the second node 13 but not in the reverse direction. That blockage of the current flow protects the rest of the trimming circuit and any circuit to which it is connected from the setting voltage which could otherwise cause damage. The transistor 10 should, of course, be constructed to withstand the setting voltage as a reverse voltage across its emitter-base junction.

The rupture procedure as described above may be carried out with or without the circuit being powered up.

Because a window is not required in any layers above the transistor 8 for the rupture of the gate oxide to be effective as described above, the procedure can be carried out after the integrated circuit has been encapsulated in its package. That enables offsets due to stresses caused by the packaging to be compensated.

To ensure that the circuit of Figure 1 gives a "high" or "low" output voltage depending on whether or not the first nMOS transistor 8 is ruptured, the voltages applied to the bias terminals 3,4 have to be of selected values.

The bias applied to the terminal 3 and the gate of the first pMOS transistor 6 should be such that depending on whether the gate oxide of the first nMOS transistor 8 is unruptured or ruptured the pMOS transistor 6 is more or less conductive than the nMOS transistor 8 with the result that the voltage at the first node 12 is either "high" or "low". Typically, the bias voltage applied to the terminal 3 should be about one volt negative of the voltage on the conductor 1.

The second pMOS transistor 7 and the second nMOS transistor 9 act as an inverting buffer stage providing at the output terminal 11 a "high" voltage when the voltage at the first node 12 is "low". In order to ensure that, the bias voltage on the gate of the second nMOS transistor 9, applied to it from the second bias terminal 4, should be such that when the voltage at the first node 12 is "low", and consequently the second pMOS transistor 7 is in a conductive state, the second nMOS transistor 9 is much less conductive than the pMOS transistor 7, resulting in a "high" output at the terminal 11.Similarly, the bias voltage on the terminal 4 should also be such that the second nMOS transistor 9 is more conductive than the second pMOS transistor 7 when the voltage at the first node 12 is high and the second pMOS transistor 7 is in a high resistance state ensuring that the voltage at the output terminal 11 is "low". Typically the bias voltage on the terminal 4 should be about one volt positive of the voltage on the conductor 2.

As mentioned above, the bipolar transistor 10 acts as a diode in the circuit of Figure 1; it therefore could be replaced by a diode. Figure 2 shows the circuit of Figure 1 with the bipolar transistor 10 replaced by a diode 15 connected to allow current to flow from the first node 12 to the second node 15 but not in the reverse direction.

The operation of the circuit of Figure 2 is the same as that of Figure 1 described above.

A plurality of circuits of the type shown in Figure 1 or Figure 2 could be used in an integrated circuit to provide programmable read-only memory for a plurality of bits. The memory could be programmed as late as when the integrated circuit in its package has been mounted on a printed circuit board in an application circuit. For example, the serial number of the printed circuit board could be permanently programmed into the integrated circuit without the need for area consuming and insecure links on the printed circuit board.

Alternatively one or more circuits as shown in Figure 1 or Figure 2 could be used permanently to select the options of a general purpose integrated circuit again without the need for links external to the integrated circuit.

The circuit could also be used to trim bias voltages and reference voltages, or otherwise to remove offsets in an analogue integrated circuit. Using the method of rupturing the gate oxide of an MOS transistor allows the adjustment to be done after the integrated circuit has been packaged, thus enabling offsets induced by packaging stresses to be trimmed.

Trimming of an impedance in an integrated circuit can be effected by using the output of the circuit described above to select whether a small or large impedance is connected in circuit either as the total impedance or in series or parallel with another part of the impedance.

Claims

CLAIMS:

1. A trimming circuit for an integrated circuit including first and second conductors respectively carrying first and second voltages, an enhancement mode MOS transistor having a source and a gate connected to the second conductor and a drain connected to the first conductor through an impedance, the first voltage being different from the second voltage, and means for selectively applying to the drain of the MOS transistor a setting voltage which is sufficiently large relative to the second voltage to rupture the gate oxide of the transistor so as to connect the drain to the gate through a low impedance, the circuit being such that if the setting voltage has not been applied to the drain of the transistor then the drain is at a voltage close to the first voltage, and if the setting voltage has been applied to the drain of the transistor then, after the setting voltage has been removed, the drain is at a voltage close to the second voltage.

2. A trimming circuit according to claim 1 including a protection circuit connected between the drain and the impedance, the protection circuit being such as to prevent the setting voltage if it is applied to the drain from also being applied to the impedance, and to present only a small impedance to any current flowing between the first and second conductors when the setting voltage is not being applied.

3. A trimming circuit according to claim 2 wherein the protection circuit includes a diode.

4. A trimming circuit according to claim 2 wherein the protection circuit includes a bipolar transistor.

5. A trimming circuit according to claim 1 further including an inverting buffer stage having its input connected to the drain of the MOS transistor and being arranged to produce at its output a voltage close to the second voltage if the setting voltage has not been applied to the drain of the MOS transistor and a voltage close to the first voltage if that setting voltage has been applied.

6. A trimming circuit according to claim 2, 3 or 4 further including an inverting buffer stage having its input connected to the junction of the protection circuit and the impedance and being arranged to produce at its output a voltage close to the second voltage if the setting voltage has not been applied to the drain of the MOS transistor and a voltage close to the first voltage if that setting voltage has been so applied.

7. A trimming circuit for an integrated circuit substantially as described herein and as illustrated by Figure 1 or Figure 2 of the accompanying drawings.

8. A method of trimming an integrated circuit including providing in the integrated circuit an enhancement mode MOS transistor having a drain connected to a first voltage through an impedance and a source and a gate connected to a second voltage, the second voltage being different from the first voltage, and selectively applying to the drain of the MOS transistor a setting voltage sufficiently large relative to the second voltage to rupture the gate oxide of the transistor so as to connect the drain to the gate through a low impedance, so that if the setting voltage has not been applied to the drain of the transistor then the drain is at a voltage close to the first voltage, and if the setting voltage has been applied to the drain of the transistor then after the removal of the setting voltage the drain is at a voltage close to the second voltage.

9. A method of trimming an integrated circuit substantially as described herein and as illustrated by Figure 1 or Figure 2 of the accompanying drawings.