GB2269502A - Bias circuit for changing bias in part of multistage amplifier - Google Patents

Abstract

A bias circuit for a multi-stage amplifier comprises a first subcircuit that provides bias that varies as a result of a variable external bias, and a second subcircuit that provides bias that is invariant when the external bias reaches a threshold level, wherein the first and second subcircuits also supply substantially no bias when the external bias is approximately zero. In fig. 1 the first subcircuit biases stage 1 and the second subcircuit stages 2 and 3. <IMAGE>

Description

A BIAS CIRCUS FOR A MULTI-STAGE AMPLIFIER FIELD OF THE INVENTION This invention generally relates to bias circuits for multistage amplifiers.

BACKGROUND OF THE INVENTION Without limiting the scope of the invention, its background is described in connection with bipolar transistors, as an example.

Heretofore in this field, high frequency amplifiers have been used in a wide variety of applications. Increasingly, these amplifiers are being used in products such as cellular telephones and remote pagers that are required to operate for long periods from a battery power supply. This demands that the amplifiers used in such products be as efficient as possible. One of the factors influencing the efficiency of an amplifier is the circuitry through which DC power is routed to the transistors that act as amplifying elements. This circuitry must necessarily be low loss in nature while also performing functions such as acting as an on/off switch, providing variable current for gain control of the amplifier, and keeping the transistor amplifying elements optimally biased.It is also desirable that this bias circuitry be integrable on the same semiconductor die with the rf circuitry comprising the amplifier. Past solutions to the design of bias circuitry for multi-stage amplifiers have been relatively inefficient and generally lack the variety of functions listed above. Any solutions that overcome this inefficiency while providing all of the control functions necessary in an amplifier would be desirable.

SUMMARY OF THE INVENTION Radio frequency power amplifiers are generally designed to provide a required amount of power as efficiently as possible. Additionally, the performance required of an amplifier often dictates that multiple stages of amplification be used in the amplifier.

Each stage generally is designed to perform with specific characteristics in order to achieve the desired performance at the amplifier's output. For example, if the amplifier is required to deliver a number of different power levels, gain control is required and is usually performed using the first stage of the amplifier. Later stages in the amplifier are generally designed to produce power as efficiently as possible. The varying requirements of individual stages in an amplifier place a high demand on the circuitry designed to provide DC bias to the amplifier stages. This circuitry must be able to set the output stages of an amplifier at the most efficient bias conditions possible, while simultaneously providing the capability of gain control to the first stage.Additionally, the demands of systems powered by batteries or small power supplies often requires a bias circuit to eliminate such functions as power supply switching where losses that were traditionally acceptable have become an obstacle in reaching the efficiencies demanded by the system in which the amplifier is used. The circuitry disclosed herein is intended to address these requirements.

It is herein recognized that a need exists for a radio frequency amplifier with bias circuitry that is low-loss in nature while providing functions which include: acting as an off/on switch, providing variable currents for gain control, and keeping the transistor amplifying elements optimally biased.

Generally, and in one form of the invention, a bias circuit for a multi-stage amplifier comprising a first subcircuit that provides bias that varies as a result of a variable external bias, and a second subcircuit that provides bias that is invariant when the external bias reaches a threshold level, and wherein the first and second subcircuits also supply substantially no bias when the external bias is approximately zero is disclosed.

One advantage of the invention is that it is integrable on the semiconductor die on which the high frequency amplifier is fabricated. This lowers the cost of the amplifier product by reducing component count. Another advantage is that the need for external bias switching of the amplifier is not required. This eliminates the lossy switches used in the past to turn power supplies on and off. Still another advantage is that gain control of the amplifier is accomplished using much less bias current than has been possible with past solutions. This directly impacts the overall efficiency of the amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 is a schematic diagram of a first preferred embodiment of the invention; Figure 2 is a schematic diagram of a second preferred embodiment of the invention.

Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS A first preferred embodiment of the invention is shown in Figure 1. It is designed to be the bias network of a three-stage amplifier fabricated on GaAs, for example, using heterojunction bipolar transistors (HBTs) as the amplifying elements. Resistors R2, R3, and R4, diodes D1 and D2, and transistor Q2 are the components that set the constant operating point on the second and third stages of the amplifier for class C operation.

Class C has been shown to be a particularly efficient operating mode for power amplifiers. When the voltage, VPC, rises above 2.5 V, the two series connected diodes D1 and D2 turn on and develop a reference voltage, Vref, at the base of transistor Q2 that is substantially independent of further increases in VPC (VPC is a variable voltage input obtained by sensing the output power of the amplifier with a detector diode).

Transistor Q2 acts as both a level shifter and as an emitter-follower voltage buffer. The quiescent bias point of the second and third stages is set by the difference of Vref and the DC level shift voltage across the base-emitter junction of transistor Q2. Because this DC level shift is independent of VPC, the quiescent bias point of the second and third stages is also substantially independent of VPC once the diodes are switched on (VPC greater than 2.5 V).

In Figure 1, the two diodes Dl and D2 create a Vref that results in zero quiescent current (Vref is less than the sum of VBE(Q2) and VBE(second or third stage)) and hence ensures a class C operating point in the second and third stages of the amplifier as VPC varies. Hence, the circuit provides the desired function of holding the second and third stages of the amplifier at a bias point characteristic of Class C operation. This is achieved by using base-collector junction type p-n junctions for the diodes D1 and D2 (these have lower turn-on voltages than the base-emitter heterojunctions usually characteristic of heterojunction bipolar transistors).An alternative solution is to use base-emitter heterojunction type diodes that have a larger area and hence lower turn-on voltages than the base-emitter heterojunctions used in the HBTs in transistor Q2 and the second and third stages. When a radio frequency (rf) signal is applied to the amplifier, extra DC base current is induced in the second and third stages. The emitter-follower buffer action of transistor Q2 ensures that the circuit can supply this extra current but still maintain the correct voltage (Vref - VBE(Q2)) at the emitter of Q2.

It has been determined empirically that it is the operating point as defined by the average DC voltage at the base of an amplifying stage, when rf is applied, that determines the efficiency of operation. For GaAs HBTs, the optimum average DC base voltage (under rf drive) occurs at approximately 1.0 V. However, a 100 mV change to 1.1 V can result in a 5% degradation in efficiency.

The base feed resistors R3 and R4 are included to help ensure that the second and third stages of the amplifier do not present a short circuit impedance on their bases at any frequency. This has been found, empirically, to be important to ensure rf stability of a bipolar large signal amplifying stage.

Although R3 and R4 are small, the extra rf-induced base current in the second and third stages results in a small (approximately 200 - 300 mV) voltage drop across these two base fecd resistors. Hence, the values of R3 and R4 must be chosen carefully so that the average DC voltage at the bases of the second and third stages meets the 1.0 V optimum value under rf drive conditions.

Different combinations of Vref (and hence quiescent current) and R3 and R4 could be used to set the 1.0 V operating point. If base feed resistors are present, the quiescent current alone is not enough to determine the operating point and hence efficiency under rf drive. For example a larger Vref could be used, but would require larger R3 and R4 to drop the voltage back to 1.0 V.

This would have improved rf stability margin for the second and third stages, but the disadvantage of this approach is that the average DC voltage at the bases of the second and third stages becomes heavily dependent on the current gain (beta) of these stages, because for a single stage producing a given rf output power, the base current under rf drive (and hence the voltage drop across the base feed resistor R3 or R4) will vary in inverse proportion to beta. Beta generally is not well controlled in production, so this approach may have unacceptable yield risk.

Conversely, if the reference voltage of 1.0V +VBE(Q2) is chosen, then R3 and R4 should be reduced to zero. However, as described above this would result in rf instability in the second and third stages. Hence, the compromise is to choose enough base feed resistance (R3 and R4) to ensure RF stability but little enough to introduce acceptable beta dependence on the operating point of the second and third stages. Once R3 and R4 are chosen, the Vref is set to the correct value by choosing the appropriate type and/or sizes of diodes D1 and D2. In the first preferred embodiment circuit R3 is approximately 240 ohms and R4 is approximately 11 ohms. The junction area of D1 is approximately 200 square microns and the area of D2 is approximately 11250 square microns.

The resistor R2 is chosen to be large enough to limit the current that is drawn by the VPC pin, when at the maximum voltage of 4.5 V, to less than 3 mA. Transistor Q1 and R1 are used to achieve the If gain control in the first stage mentioned above as a desirable function of the bias circuitry for this type of amplifier. The value of R2 in the first preferred embodiment circuit is approximately 1000 ohms.

Transistor Q1 acts as a level shifter in that the first stage is turned on only after the second and third stages are tumed on at VPC = 2.5 V. For 2.5 V < VPC < 4.5 V, the quiescent current and hence gain in the first stage increases, whilst the gain and quiescent bias voltages in the second and third stage remain constant. This ensures that the drive level and base bias requirements for high efficiency operation in the second and third stages will be simultaneously met at one or more output power levels. The power at which this peak efficiency occurs is determined by the tuning of the third stage output matching network. For other power levels in the gain control range, the efficiency is maintained as close as possible to the peak value because the base bias voltage of the second and third stage is held at around 1.0 V as described above.

When VPC is at zero volts, the quiescent currents in all three stages are reduced to approximately zero by setting the base voltages to zero. Hence the VPC control also functions as an on/off switch. Also, when the amplifier is switched off in this way, there is approximately 40 dB of rf isolation between the rf input and rf output for input levels to the amplifier of less than 0 dBm. This function in prior art solutions is accomplished using switches external to the amplifier circuit. These switches are generally lossy and therefore adversely impact the efficiency of the amplifier.

The value of R1 is chosen to set the value of the maximum quiescent current and hence gain of the first stage when the maximum VPC voltage of 4.5 V is applied. In this case R1 is approximately 1000 ohms. R5, R6, R7 and R8, are small damping resistors to ensure that transistors Q1 and Q2 are rf stable. They do not appreciably alter the main operation of the circuit. Capacitors C2 and C3 also help rf stability in the rf stages and also help ensure that the base feeds to all three stages act as good rf chokes so that the bias circuit does not interfere with the rf matching networks between the three stages.

Figure 2 shows a second preferred embodiment of the circuit in which the transistor combination Q2 and Q3 replaces the function of Q2, D1 and D2 in the first preferred embodiment circuit shown in Figure 1. In this case the voltage generated at the emitter of Q2 is large enough to induce a small quiescent current in the second and third stages. The quiescent current is set by a ratioed current mirror from Q3 to the rf stage.

For example, the quiescent current in the third stage is substantially set by the ratio of the emitter areas of Q3 and the third stage transistor, multiplied by the collector current in Q3. Because the second and third stages have a larger DC base bias voltage, larger values of R3 and R4 are needed to recover the Vbase (DC average under rf drive) = 1.0 V operating point In other words, this implementation has a different compromise between the rf stabilising base resistor value and operating point beta sensitivity, as discussed above. The circuit could be used for an amplifier that had lower beta variations but higher rf stage instability when presented with a low base impedance, compared to that for the circuit in Figure 1.

A few preferred embodiments have been described in detail hereinabove. It is to be understood that the scope of the invention also comprehends embodiments different from those described, yet within the scope of the claims.

Internal and external connections can be ohmic, capacitive, direct or indirect, via intervening circuits or otherwise . Implementation is contemplated in discrete components or fully integrated circuits in silicon, gallium arsenide, or other electronic materials families, as well as in optical-based or other technology-based forms and embodiments.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense.

Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the- description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims (14)

WHAT IS CLAIMED IS:

1. A bias circuit for a multi-stage amplifier comprising: a first subcircuit that provides bias that varies as a result of a variable external bias; and a second subcircuit that provides bias that is invariant when said external bias reaches a threshold level, and wherein said first and second subcircuits also supply substantially no bias when said external bias is approximately zero.

2. The bias circuit of Claim 1 wherein said first subcircuit is used to control gain in a first stage of said amplifier.

3. The bias circuit of Claim 1 wherein said second subcircuit is used to bias an output stage of said amplifier for class C operation.

4. The bias circuit of Claim 1 wherein said threshold level is determined by a junction voltage of a junction diode.

5. The bias circuit of Claim 1 wherein said first subcircuit comprises a transistor and a resistor.

6. The bias circuit of Claim 1 wherein said second subcircuit comprises a transistor, a first diode, and a second diode.

7) The bias circuit of Claim 1 wherein said second subcircuit comprises two transistors.

8. The bias circuit of Claim 5 or Claim 6 or Claim 7 wherein said transistors are heterojunction bipolar transistors.

9. The bias circuit of Claim 6 wherein said first and second diodes comprise a homojunction between a p type doped region and an n type doped region.

10. The bias circuit of Claim 6 wherein said first and second diodes comprise a heterojunction between an n type doped region and a p type doped region.

11. A bias circuit substantially as herein described with reference to the drawings.

12. An integrated circuit including a bias circuit as claimed in any preceding claim.

13. The integrated circuit of Claim 12 wherein said circuit is fabricated on a GaAs substrate.

14. A telephone including a circuit as claimed in any preceding claim.