GB2265053A

GB2265053A - Digital signal receiver and signal processor.

Info

Publication number: GB2265053A
Application number: GB9205218A
Authority: GB
Inventors: Michael Colin Wells
Original assignee: Roke Manor Research Ltd
Current assignee: Roke Manor Research Ltd
Priority date: 1992-03-11
Filing date: 1992-03-11
Publication date: 1993-09-15
Anticipated expiration: 2012-03-11
Also published as: GB2265053B; GB9205218D0

Abstract

A digital signal receiver provided with a beam forming array of antennas (a1...an) utilises a discriminator vector d to calculate a weighting distribution applied via respective multipliers m1...mn to the output of buffers (b1...bn) containing digitised values of the received waveforms. The sequences of digitised waveform samples stored in the buffers each include a sequence which ideally corresponds to a known sequence which is stored in a signal component store (6). The discriminator vector d initially consists of this known sequence and is subsequently refined by including the remaining samples derived from the combined and demodulated output signal by means of a modulator (3), the discriminator vector is then reconstructed (5), and the thus-modified discriminator is then used to refine the weighting distribution calculated by a digital processor (8). Further iterations may be performed if required. This arrangement is applicable to a frequency- hopping communications system for example. <IMAGE>

Description

DIGITAL SIGNAL RECEIVER AND COMMUNICATIONS SYSTEM The present invention relates to a digital signal receiver and to a communications system incorporating such a receiver. The invention relates particularly but not exclusively to a digital signal receiver comprising an array of beam-forming antennas provided with respective analog to digital convertors and means for combining the received digitised wave forms from the respective antennas.

In general, any digital signal receiver arranged to combine a plurality of input signals (e.g. from an antenna array) will apply a weighting distribution to the input signals and it is desirable to optimise the weighting distribution so as to maximise the desired signal reception while cancelling interfering signals and noise. In particular, when the input signals are derived from an array of receiving antennas, the received signals will be subject to multipath distortion.

If the desired output signal were known, then it could be used as a discriminant to modify the weighting distribution and provide optimum rejection of interference and noise. However in practice the received signal is known only partially and the performance of any system utilising this partial knowledge of the desired signal is inherently limited.

In certain circumstances, an alternative discriminant that can be used is the detected (rather than the desired) data. However, if the detected data incorporates too many errors, then it will be ineffective as a discriminant.

A more sophisticated discriminant has now been found which enables a digital signal receiver to perform almost as well as if the desired signal were known completely.

Accordingly the invention provides a digital signal receiver comprising weighting means for applying a weighting distribution to a plurality of input signals, means for combining the weighted input signals to produce a digital output signal and digital processing means which is responsive both to said output signal and to a known signal pattern which is common to said input signals to modify said weighting distribution so as to discriminate against undesired input signal components.

Typically the digital signal receiver will be provided with an array of receiving antennas each arranged to feed multi-bit digital waveform samples to said weighting means.

The invention also provides a digital communications system comprising a digital signal receiver as defined above and a transmitter arranged to transmit signals to said receiver which include said known signal pattern.

A preferred embodiment of the invention is described below by way of example only with reference to the accompanying drawing, in which; Figure 1, shows the receiver in block diagrammatic form.

The arrangement shown in Figure 1 is arranged to receive microwave signals or radio signals from a frequency-hopping transmitter, and is provided with a beam-forming array of n antennas al, a2 an. The signals from the antennas are converted to multi-bit digital form (by means not shown) and successive samples from the antennas are read synchronously into respective buffers bl, b2 bn under the control of an iteration controller 7. It is assumed that the frequency-hopping transmitter transmits a signal from which 295 samples can be derived before it hops to the next frequency. Each buffer is arranged to store 295 successive multi-bit samples from its associated antenna and accordingly these samples represent one "burst" of the received signal. When the transmitter hops to the next frequency, the buffers are re-filled with a further set of 295 samples.

The stored multi-bit samples in each of buffers bl to bn include a known sequence of 32 values which can be recognised at the receiver. This known sequence can for example be generated by a pseudo-random number generator at the transmitter and the receiver is provided with a complementary processor (not shown) which can recognise the pseudo-random pattern. However for the sake of simplicity, in the present description it will be assumed that a sequence of the first 32 samples in each buffer is known by the receiver. The utilisation of this known sequence will be described below.

A digital processor 8 is provided which applies weighting factors to the respective values which are read out from the buffers.

Accordingly, each buffer output is multiplied by an appropriate weighting factor in one of multipliers ml, m2...... m2 mn and the sum of the weighted values is derived by means of an adder 1.

The output of this adder 1 is a serial stream of multi-bit values which nominally represent successive samples of the wave form received by the antenna array. In practice however this output signal will be corrupted by noise and multipath and other interference. This output signal is demodulated by a demodulator 2 and the resulting output is essentially free of noise but in practice is liable to include errors due to the above-mentioned interference.

The digital processor 8 adjusts the weighting distribution applied to the output of buffers bl to bn in accordance with the invention so as to minimise such errors. To do this it utilises a discriminator vector d which is a single column, 295 row matrix, of which the first 32 rows are filled with multi-bit values corresponding to the known sequence nominally stored in each of the buffers bl to bn and the remaining values are initially set to 0:

The discriminator vector d is stored in this form in a signal component store 6 and is read into the processor 8 by means of a selector 9 under the control of iteration controller 7.It should be noted that, due to interference and noise, there will in general be some discrepancy between the sequences of 32 known symbols stored in the buffers and the known sequence of 32 values nl to n32 stored in a signal component store 6. As will be described in more detail below, the processor 8 utilises the discriminator vector d to discriminate against those buffer signals whose first 32 samples differ from the known sequence stored in the signal component store 6.

Accordingly the processor 8 modifies the weighting distribution applied via multipliers ml to mn and the resulting output signal from the demodulator 2 is improved, i.e. some but not all errors are eliminated.

In order to provide further improvement, the output from the demodulator 2 is remodulated by a modulator 3 which generates a serial output stream of multi-bit values similar to that output by adder 1, but with most of the noise removed. Accordingly the 33rd to 295th values required for the discriminator vector d are derived in block 4 and a complete discriminator vector d is re-derived by combining these values with the 32 values of the known sequence which are again read out from the signal component store 6.This rederived discriminator vector d is read out from block 5 and is selected by a selector 9 under the control of iteration controller 7 to enable the digital processor 8 to recalculate the weighting distribution applied via multipliers ml to mn. As a result, the weighting distribution is optimised further and most, if not all errors are eliminated from the output of the demodulator 2. However if desired the new output of the demodulator 2 can be remodulated to derive a new discriminator vector d in the manner described above and this new discriminator vector can be fed into the digital processor 8 from the block 5 and the selector 9 under the control of the iteration controller 7. The iteration controller 7 may be arranged to perform any suitable number of iterations and to read out the contents of the buffers to the multipliers ml, to mn at an appropriate multiple of the rate at which incoming samples from the antennas al, to an are read into the buffers.

The digital processor 8 derives from the outputs of buffers bl to bn and n-column 295 row matrix X wherein each column represents the burst of 295 multi-bit values stored in a respective buffer bl to bn. The processor also derives a co-variance matrix M and derives a weighting distribution matrix W as a single column n row matrix containing the weighting factors applied by multipliers ml to mn. The weighting distribution is derived as follows: W = M-ir where M=XHX and r =XHd XH is the Hermition of X The solution of these matrix equations is within the capability of persons skilled in the art and is covered for example in Monzingo and Miller "Introduction to Adaptive Arrays" Wiley - Interscience 1980 and by J E Hudson in "Adaptive Array Principles", IEE Electromagnetic wave series II, Peter Peregrinns, 1981.

Claims

CLAIMS:

1. A digital signal receiver comprising weighting means for applying a weighting distribution to a plurality of input signals, means for combining the weighted input signals to produce a digital output signal and digital processing means which is responsive both to said output signal and to a known signal pattern which is common to said input signals to modify said weighting distribution so as to discriminate against undesired input signal components.

2. A digital signal receiver according to claim 1, provided with an array of receiving antennas each arranged to feed multi-bit digital waveform samples to said weighting means.

3. A digital signal receiver according to claim 1 or claim 2 wherein said processing means is arranged to generate an initial weighting distribution from said known signal pattern and subsequently to generate a weighting distribution from said output signal as derived from said initial weighting distribution.

4. A digital signal receiver according to claim 3 wherein said processing means is arranged to modify said weighting distribution in an iterative fashion in response to the output signal generated in response to the previous iteration of the weighting distribution.

5. A digital signal receiver according to claim 3 or claim 4 comprising a plurality of buffers each arranged to store a succession of multi-bit values, control means arranged synchronously to read out the contents of respective buffers to said weighting means, a demodulator arranged to demodulate said output signal, and means for constructing a discriminator vector d which vector comprises a single column array of multi-bit values approximating to the desired output of said combining means, said constructing means comprising a modulator arranged to remodulate said digital output signal, said digital processing means being responsive to said discriminator vector and to a discriminator vector derived from said known signal pattern and stored in memory.

6. A digital signal receiver according to claim 5 wherein said processing means is arranged to generate a weighting distribution matrix W comprising a column of weighting factors applied to the respective input signals by the operations: W = M-1r M=XHX r =XHd wherein M is a co-variance matrix; X is a matrix of multi-bit values read out from the buffers, each column thereof comprising successive multi-bit values from a respective one of the buffers; XH is the Hermitian of X, r is the product of XH and d and d is said discriminator vector.

7. A digital communications system comprising a digital signal receiver according to any preceding claim and a transmitter arranged to transmit signals to said receiver which include said known signal pattern.

8. A digital communications system according to claim 7 which is a frequency-hopping communications system.

9. A digital signal receiver substantially as described hereinabove with reference to Figure 1 in the accompanying drawing.