GB2263579A - An integrated circuit with intermingled electrodes - Google Patents

An integrated circuit with intermingled electrodes Download PDF

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Publication number
GB2263579A
GB2263579A GB9201820A GB9201820A GB2263579A GB 2263579 A GB2263579 A GB 2263579A GB 9201820 A GB9201820 A GB 9201820A GB 9201820 A GB9201820 A GB 9201820A GB 2263579 A GB2263579 A GB 2263579A
Authority
GB
United Kingdom
Prior art keywords
face
integrated circuit
electrode
semiconductor block
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9201820A
Other versions
GB9201820D0 (en
Inventor
Stephen Wilton Byatt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Ltd filed Critical Texas Instruments Ltd
Priority to GB9201820A priority Critical patent/GB2263579A/en
Publication of GB9201820D0 publication Critical patent/GB9201820D0/en
Priority to US07/966,932 priority patent/US5359210A/en
Priority to EP93300298A priority patent/EP0552905A1/en
Priority to JP5007475A priority patent/JPH05267648A/en
Publication of GB2263579A publication Critical patent/GB2263579A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/747—Bidirectional devices, e.g. triacs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes

Description

226357,9 1 - An Inteqrated Circuit The present invention relates to an
integrated circuit which includes two devices formed in a semiconductor block.
The present invention provides an integrated circuit including a first device having respective input and output electrodes at opposed first and second faces of a semiconductor block in which the device is formed, and a second device, formed in the semiconductor block, having its respective input and output electrodes at the first face and at the second face of the semiconductor block, the electrodes at the first face of the semiconductor block inter-mingling with each other.
is The electrode of the first device at the first face may, for example, include a plurality of discrete contact areas at respective positions corresponding to the dark areas on a chess board, with the electrode of the second device at the first face including contact areas occupy- ing the positions corresponding to the white areas on the chess board.
The intermingling of the electrodes contrasts with the known arrangement of having each electrode concentrated in a respective part of the the first face of the semiconductor block.
Preferably, the electrode of the first device at the first face of the semiconductor block includes a - 2 plurality of discrete contact areas distributed over substantially all of the first face of the semiconductor block, and the electrode of the second device at the first face of the semiconductor block includes a contact area lying between the discrete contact areas of the electrode of the first device.
Preferably, the electrodes at the first face of the semiconductor block have a common surface within the semiconductor block, and the electrode of the first device at the first face has a plurality of projections which extend through the electrode of the second device at the first face and terminate at the surface of the first face.
Preferably, the electrodes at the second face of the semiconductor block intermingle with each other.
Preferably, the contact areas at the second face of the semiconductor block are similar in shape to the respective contact areas at the first face.
Preferably, the input electrode of the first device and the output electrode of the second device lie at the first face of the semiconductor block.
Preferably, the first device includes an intermediate electrode, which sets its breakdown voltage, between its input and output electrodes, and that intermediate electrode has a form similar to the form of the electrode of the first device at the first face of the semiconductor block.
- 3 is Preferably, the second device includes an intermediate electrode, which sets its breakdown voltage, between its input and output electrodes, and that intermediate electrode has a form similar to the form of the electrode of the second device at the first face of the semiconductor block.
Preferably, the first device is a PNPN device and, preferably, the second device is a PNPN device, and the input electrode of the first device and the output electrode of the second device lie at the first face of the semiconductor block.
An integrated circuit in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings in which:
Fig. 1 shows a perspective view of the internal structure of a first example of the integrated circuit, Fig. 2 shows one electrical contact surface of a second example of the integrated circuit, Fig. 3 shows the electrical contact surface corresponding to that shown in Fig. 2 for a third example of the integrated circuit and Fig. 4 shows the electrical contact surface corresponding to that shown in Fig. 2 for a fourth example of the integrated circuit.
In the following description the terms "upper" and "lower" refer to the device as viewed in the accompanying drawings.
Referring to Fig. 1 of the accompanying drawings, the first example of the integrated circuit includes an inner N-type semiconductor body 1 having substantially rectangular upper and lower faces. An inner P-type semiconductor body 2 has a lower face in contact with the upper face of the inner N-type body 1, and an upper face which is in contact with a first outer N-type semiconductor body 4. The first outer N-type semiconductor body 4 consists of a plurality of longitudinal and transverse bars of N-type semiconductor material which form a grid, and each of the bars has an exposed upper face. The inner, P-type body 2 extends upwards into the gaps between the bars which form the first outer N-type body 4 and consequently, the upper face of the inner P-type body 2 consists of a plurality of substantially rectangular areas which are separated by the bars forming the first outer N-type body 4.
The lower face of the inner N-type body 1 has the upper face of an outer P-type body 3 adjacent to it. A second outer N-type body 7 lies in the lower surface of the outer P-type body 3; the second outer N-type body 7 consists of a plurality of substantially rectangular blocks. The blocks are separated from one another by a plurality of longitudinal and transverse bars 31 on the lower face of the outer P-type body 3 and those bars form a grid which has the same pitch as the grid formed by the bars which make up the first outer N-type body 4.
Also, the relative positions and shapes of the blocks are substantially the same as the relative positions and shapes of those regions of the inner P-type body 2 which extend into the gaps between the bars forming the first outer N-type body 4.
The inner N-type body 1 has a first additional Ntype formation 5 consisting of a plurality of longitudinal and transverse bars at relative positions and of sizes substantially the same as the relative positions and sizes of the bars of the first outer N-type body 4. The formation 5 is of N-type semiconductor.material of higher conductivity than that of the inner Ntype body 1 and is located at the upper face of the inner N- type body 1. In addition, the inner N-type body 1 has a second additional formation 6 consisting of a plurality of substantially rectangular blocks at substantially the same relative positions and of substantially the same shape as the blocks of the second outer N-type body 7. The second additional formation 6 is of N-type semicon ductor material of higher conductivity than that of the inner N-type body 2 and is located at the lower face of the inner N-type body 1.
The inner P-type body 2, the inner N-type body 1, the outer P-type body 3, and the second outer N-type body 7 form a first PNPN device which has the second additional formation 6 at the junction of the inner Ntype body 1 and the outer P-type body 3.
The outer P-type body 3, the inner N-type body 1, the inner P-type body 2, and the first outer N-type body 4, form a second PNPN device, facing opposite to the first PNPN device, which has the first additional formation 5 at the junction of the inner N-type body 1 and the inner Ptype body 2.
The inner P-type body 2 and the second outer N-type body 7 are the inout and output electrodes of the first PNPN device, while the outer P-type body 3 and the first outer N-type body 4 are the input and output electrodes of the second PNPN device. The inner P-type body 2 and 4 are connected together by means of a metal layer (not shown) formed on the common surface of those two bodies, and the second N-type body 7 and the outer P-type body 3 are connected together by means of another metal layer (not shown) formed on the common surface of those two bodies, providing two PNPN devices connected in parallel in opposite senses.
In the operation of the integrated circuit, current flow occurs from the top surface to the bottom surface of the semiconductor block through the first PNPN device, and current flow in the opposite sense occurs through the second PNPN device. Current flow through the first PNPN device is concentrated in columns having the areas 21 of the inner P-type body 2 and the areas 71 of the second outer N-type body 7 as their upper and lower faces. Those columns of current are distributed over the the first outer N-type body 7 - is semiconductor block in accordance with the distribution of the areas 21 and 71 over the semiconductor block, and as a result of the distribution of the current columns, the heating effect of the current through the first PNPN device is distributed substantially throughout the semiconductor block. The current through the second PNPN device flows in the semiconductor material between the columns defined by the areas 31 and 4 and the heating effect of that current is also distributed substantially throughout the semiconductor block.
Referring to Fig. 1, the integrated circuit is a two-terminal device. For clarity, terminals are not shown, but consist of a conductive layer on its upper surface and a conductive layer on its lower surface. The provision of a single conductive upper layer and a single conductive lower layer results in an integrated circuit consisting of two devices which are connected in parallel with each other and conductive in opposite senses.
Alternatively, it would be possible to provide separate terminals for the two devices which make up the integrated circuit; that is, the integrated circuit may be a four-terminal device.
The integrated circuit shown in Fig. 1, when provided with a single upper and single lower conductive layer, consists of two substantially identical PNPN devices connected in parallel in opposite senses. The body 5 sets the breakdown voltage of the first device, - 8 is and the body 6 sets the breakdown voltage of the second device. The width of the grid is such that it provides an effect equivalent to shorting dots used in conventional devices.
The integrated circuit shown in Fig. 1, when provided with only two terminals, can be used as a bidirectional transient voltage suppressor. Since the current for each device is dispersed through the semiconductor bulk, the heat generated by each device is spread over the volume of the semiconductor bulk and the resulting temperature rise is less than that for the conventional arrangement of the bidirectional device, having the PNPN devices side-by-side. It would be the case that, in the use of the integrated circuit as a transient voltage suppressor, one of the two PNPN devices is activated more often than the other, and the temperature rise of the integrated circuit is substantially less than it would be for a conventional device with side-byside PNPN devices. The integrated circuit with inter- mingled electrodes provides a transient voltage suppressor with a higher surge current rating than a conventional side-by-side device having the same volume.
Fig. 2 shows a first alternative arrangement of the upper surfaces of the inner P-type body 2 and the first outer N-type body 4 of the integrated circuit, as seen from directly above. As shown in Fig. 2, the upper surface of the inner P-type body 2 consists of a plurality of rectangular areas and each corner of each rectangular area touches a respective corner of the immediately adjacent rectangular areas as do the dark and light areas of a chess-board. The surface of the first outer N-type body 4 consists also of a plurality of rectangular areas and occupy the spaces among the rectangular areas of the inner P-type body 2. The lower surface of the outer Ptype body 3 is substantially the same as the upper surface of the first outer N-type body 4, and the lower surface of the N-type body 7 is substantially the same as the upper surface of the inner P-type body 2.
Fig. 3 shows a second alternative arrangement of the upper surfaces of the inner P-type body 2 and the first outer N-type body 4 of the integrated circuit, as seen from directly above. As shown in Fig. 3, the upper surface of the inner P-type body 2 consists of a plurality of circular areas which are separated from one another by the material of the first outer N-type body 4. The circular areas are set out with their centres on a regular rectangular grid.
Fig. 4 shows a variation of the second alternative arrangement of the upper surfaces of the inner P-type body 2. In the variation of the alternative arrangement, the centres of the circular areas are set out with their centres on a regular rhomboid grid.
Further alternatives for the electrical contact - 10 surfaces of the inner P-type body 2 and the first outer N-type body 4 are spiral, interdigitated and annular shapes. The same alternatives exist for the shapes of the regions making up the lower surface of the device.
The integrated circuit described above is capable of performing the functions of a transient voltage suppressor for a single pair of lines which are connected to respective ones of its faces, and protection for a plurality of pairs of lines may be provided by means of a semiconductor block into which are integrated a plurality of substantially identical circuits. Also, transient voltage suppressors can include a plurality of the semiconductor blocks in one package and those semiconductor blocks may each comprise a single circuit as described above or a plurality of those circuits.

Claims (17)

  1. CLAIMS:
    is An integrated circuit including a first device having respective input and output electrodes at opposed first and second faces of a semiconductor block in which the device is formed, and a second device, formed in the semiconductor block, having its respective input and output electrodes at the first face and at the second face of the semiconductor block, the electrodes at the first face of the semiconductor block intermingling with each other.
  2. 2. An integrated circuit as claimed in claim 1, wherein the electrode of the first device at the first face of the semiconductor block includes a plurality of discrete contact areas distributed over substantially all of the first face of the semiconductor block, and the electrode of the second device at the first face of the semiconductor block includes a contact area lying between the discrete contact areas of the electrode of the first device.
  3. 3. An integrated circuit as claimed in claim 2, wherein the electrodes at the first face of the semiconductor block have a common surface within the semiconductor block, and the electrode of the first device at the first face has a plurality of projections which extend through the electrode of the second device at the first face and terminate at the surface of the first face.
  4. 4. An integrated circuit as claimed in any one of claims 1 to 3, wherein the electrodes at the second face of the semiconductor block intermingle with each other.
  5. 5. An integrated circuit as claimed in claim 4, wherein the contact areas of the electrodes at the second face of the semiconductor block are similar in shape to the respective contact areas of the electrodes at the first face.
  6. 6. An integrated circuit as claimed in any one of claims 1 to 5, wherein the input electrode of the first device and the outout electrode of the second device lie at the first face of the semiconductor block.
  7. 7. An integrated circuit as claimed in any one of claims 1 to 6, wherein the the first device includes an intermediate electrode, which sets its breakdown voltage, between its input and output electrodes, and that intermediate electrode has a form similar to the form of the electrode of the first device at the first face of the semiconductor block.
  8. 8. An integrated circuit as claimed in any one of claims 1 to 7, wherein the second device includes an intermediate electrode, which sets its breakdown voltage, between its input and output electrodes, and that intermediate electrode has a form similar to the form of the electrode of the second device at the first face of the semiconductor block.
  9. 9. An integrated circuit as claimed in any one of claims 1 to 8, wherein the first device is a PNPN device.
  10. 10. An integrated circuit as claimed in claim 9, wherein the second device is a PNPN device, the input electrode of the first device and the output electrode of the second device lying at the first face of the semiconductor block.
  11. 11. An integrated circuit substantially as described herein with reference to, and as shown by, Fig. 1 of the accompanying drawings.
  12. 12. An integrated circuit substantially as described herein with reference to, and as shown by, Fig. 2 of the accompanying drawing.
  13. 13. An integrated circuit substantially as described herein with reference to, and as shown by, Fig. 3 of the - 14 accompanying drawings.
  14. 14. An integrated circuit substantially as described herein with reference to, and as shown by, Fig. 4 of the accompanying drawings.
  15. 15. A semiconductor block including a plurality of integrated circuits as claimed in any one of claims 1 to
  16. 16. A transient voltage suppressor including an integrated circuit as claimed in any one of claims 1 to 14, in a package.
  17. 17. A transient voltage suppressor including a semicon ductor block as claimed in claim 17, in a package.
GB9201820A 1992-01-24 1992-01-24 An integrated circuit with intermingled electrodes Withdrawn GB2263579A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB9201820A GB2263579A (en) 1992-01-24 1992-01-24 An integrated circuit with intermingled electrodes
US07/966,932 US5359210A (en) 1992-01-24 1992-10-27 Integrated circuit
EP93300298A EP0552905A1 (en) 1992-01-24 1993-01-18 Triac
JP5007475A JPH05267648A (en) 1992-01-24 1993-01-20 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9201820A GB2263579A (en) 1992-01-24 1992-01-24 An integrated circuit with intermingled electrodes

Publications (2)

Publication Number Publication Date
GB9201820D0 GB9201820D0 (en) 1992-03-11
GB2263579A true GB2263579A (en) 1993-07-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB9201820A Withdrawn GB2263579A (en) 1992-01-24 1992-01-24 An integrated circuit with intermingled electrodes

Country Status (4)

Country Link
US (1) US5359210A (en)
EP (1) EP0552905A1 (en)
JP (1) JPH05267648A (en)
GB (1) GB2263579A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2293484A (en) * 1994-09-08 1996-03-27 Texas Instruments Ltd Lightning overvoltage protector

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US5479031A (en) * 1993-09-10 1995-12-26 Teccor Electronics, Inc. Four layer overvoltage protection device having buried regions aligned with shorting dots to increase the accuracy of overshoot voltage value
GB9417393D0 (en) * 1994-08-30 1994-10-19 Texas Instruments Ltd A four-region (pnpn) semiconductor device
FR2969823B1 (en) * 2010-12-23 2013-09-20 St Microelectronics Tours Sas BIDIRECTIONAL SHOCKLEY DIODE TYPE MESA
FR2969825B1 (en) * 2010-12-23 2013-07-12 St Microelectronics Tours Sas BIDIRECTIONAL DOUBLE-SIDING VERTICAL COMPONENT
FR2969824B1 (en) * 2010-12-23 2013-09-20 St Microelectronics Tours Sas BIDIRECTIONAL SHOCKLEY DIODE IN MESA PROLONGED
CN109360823B (en) * 2018-10-08 2020-08-28 南京溧水高新创业投资管理有限公司 Groove type transient voltage suppressor and manufacturing method thereof

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GB2184884A (en) * 1985-12-20 1987-07-01 Philips Electronic Associated Bipolar semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2293484A (en) * 1994-09-08 1996-03-27 Texas Instruments Ltd Lightning overvoltage protector
GB2293484B (en) * 1994-09-08 1998-08-19 Texas Instruments Ltd Improved lightning overvoltage protector

Also Published As

Publication number Publication date
EP0552905A1 (en) 1993-07-28
JPH05267648A (en) 1993-10-15
US5359210A (en) 1994-10-25
GB9201820D0 (en) 1992-03-11

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