GB2263002B - A parallel binary adder - Google Patents

A parallel binary adder

Info

Publication number
GB2263002B
GB2263002B GB9227180A GB9227180A GB2263002B GB 2263002 B GB2263002 B GB 2263002B GB 9227180 A GB9227180 A GB 9227180A GB 9227180 A GB9227180 A GB 9227180A GB 2263002 B GB2263002 B GB 2263002B
Authority
GB
United Kingdom
Prior art keywords
binary adder
parallel binary
parallel
adder
binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9227180A
Other versions
GB2263002A (en
GB9227180D0 (en
Inventor
Jack T Poon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB9227180D0 publication Critical patent/GB9227180D0/en
Publication of GB2263002A publication Critical patent/GB2263002A/en
Application granted granted Critical
Publication of GB2263002B publication Critical patent/GB2263002B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder
GB9227180A 1992-01-06 1992-12-31 A parallel binary adder Expired - Fee Related GB2263002B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US82030492A 1992-01-06 1992-01-06

Publications (3)

Publication Number Publication Date
GB9227180D0 GB9227180D0 (en) 1993-02-24
GB2263002A GB2263002A (en) 1993-07-07
GB2263002B true GB2263002B (en) 1995-08-30

Family

ID=25230433

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9227180A Expired - Fee Related GB2263002B (en) 1992-01-06 1992-12-31 A parallel binary adder

Country Status (2)

Country Link
JP (1) JPH06236255A (en)
GB (1) GB2263002B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000054275A (en) * 2000-05-30 2000-09-05 장주욱 A high speed parallel adder which reconfigures itself for fast processing of input
GB2365636B (en) 2000-08-04 2005-01-05 Automatic Parallel Designs Ltd A parallel counter and a multiplication logic circuit
GB2373602B (en) 2001-03-22 2004-11-17 Automatic Parallel Designs Ltd A multiplication logic circuit
GB2373883A (en) * 2001-03-27 2002-10-02 Automatic Parallel Designs Ltd Logic circuit for performing binary addition or subtraction
EP1296223A3 (en) * 2001-09-24 2005-09-14 Broadcom Corporation Adder incrementer circuit
US7260595B2 (en) 2002-12-23 2007-08-21 Arithmatica Limited Logic circuit and method for carry and sum generation and method of designing such a logic circuit
US7042246B2 (en) 2003-02-11 2006-05-09 Arithmatica Limited Logic circuits for performing threshold functions
US7308471B2 (en) 2003-03-28 2007-12-11 Arithmatica Limited Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding
US7170317B2 (en) 2003-05-23 2007-01-30 Arithmatica Limited Sum bit generation circuit
US7313586B2 (en) 2004-03-05 2007-12-25 Broadcom Corporation Adder-subtracter circuit
US10691772B2 (en) * 2018-04-20 2020-06-23 Advanced Micro Devices, Inc. High-performance sparse triangular solve on graphics processing units

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993891A (en) * 1975-07-03 1976-11-23 Burroughs Corporation High speed parallel digital adder employing conditional and look-ahead approaches
GB2226165A (en) * 1988-12-14 1990-06-20 Sun Microsystems Inc Parallel carry generation adder
EP0508627A2 (en) * 1991-04-08 1992-10-14 Sun Microsystems, Inc. Method and apparatus for generating carry out signals

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993891A (en) * 1975-07-03 1976-11-23 Burroughs Corporation High speed parallel digital adder employing conditional and look-ahead approaches
GB2226165A (en) * 1988-12-14 1990-06-20 Sun Microsystems Inc Parallel carry generation adder
EP0508627A2 (en) * 1991-04-08 1992-10-14 Sun Microsystems, Inc. Method and apparatus for generating carry out signals

Also Published As

Publication number Publication date
JPH06236255A (en) 1994-08-23
GB2263002A (en) 1993-07-07
GB9227180D0 (en) 1993-02-24

Similar Documents

Publication Publication Date Title
GB2288586B (en) A palletiser
GB9415835D0 (en) A bicycle
GB9306248D0 (en) A handsafe arrangement
GB2244572B (en) Parallel binary multiplier
GB2263002B (en) A parallel binary adder
GB9300450D0 (en) A carrier structure
AU111846S (en) A snowmobile
DE69312281D1 (en) A/d wandler
GB2282260B (en) A Piezo-Resonator
GB9400105D0 (en) A body-harness
GB9303684D0 (en) A cinerarium
KR0139872B1 (en) A full adder circuit
GB9322000D0 (en) A bicycle
GB2268013B (en) Binary modulator
GB2266626B (en) A magnetiser
GB2264127B (en) A bombardment-inhibiting facing
GB9312194D0 (en) A velociped
GB2263971B (en) A downlighter
LTIP570A (en) A worm-greenhouse
GB9312470D0 (en) A bicycle improvement
GB9201770D0 (en) A lagara
AU115297S (en) A birdbath
AU115559S (en) A jerrican
GB9205367D0 (en) A cinerarium
GB9224185D0 (en) A bagit

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20101231