GB2262169A - Storage and retrieval of information in electronic memory - Google Patents

Abstract

A system for storage and retrieval of data, for example. digitised audio signals. is disclosed in which data is handled in a plurality of independent channels D1 - D3. A large electronic storage memory 10 is divided into blocks M1 ... Mn. Prior to the storage of data in the memory a number of blocks sufficient to hold the data are allocated to the channel from which the data is to originate. Once the data is no longer required, each block may be deal located and. in due course, reallocated to a channel to receive another set of data. Each block may be allocated and deallocated independently of other blocks. Allocation and deallocation of blocks for a channel may take place during input, storage or output of data (at O1 - O3) in any other channel, and are controlled by a microcomputer 19. Each channel comprises an input circuit I1 - I3 paired with an output circuit O1 - O3. <IMAGE>

Description

STORAGE ALjD RETRIEVAL OF INFORMATION IN ELECTRONIC MEMORY The present invention relates to storage and retrieval of information in electronic memory.

As is well known, there has been a trend in recent years to handle information, which has been traditionally recorded as analogue signals, in digital form. A particular example of this is the storage of music. Traditionally music has been stored as analogue magnetic signals on magnetic tape or as physical modulation of a groove in a record. However, digital storage systems such a compact disc (CD) or digital audio tape (DAT) are becoming increasingly popular music storage media for both professional and domestic use.

A particular example of the movement to digital technology within the music industry relates to the duplication of a musical programme onto pre-recorded cassette tapes. For many years this was achieved by copying the master recording onto a length of high quality, typically one inch, tape, which was then spliced to form an endless loop. The loop of tape was stored in apparatus known as an endless-loop bin which allowed the tape to be continuously played at high speed, say 64 times its recording speed. Signals reproduced from the tape loop were then recorded onto large reels of tape, suitable for incorporation with a cassette.

There are several distinct disadvantages to this system which arise from the extreme mechanical conditions to which the tape loop s subjected. The tape loop tends to wear by depositing oxide particles onto the tape heads. The heads themselves also wear.

A fold or crease can arise in the tape which, at high speeds, can quickly destroy the tape. Many tapes are also damaged during loading into the bins and so are never used at all.

These disadvantages led to the development of the "digital bin". In such an apparatus, the audio signals from the master tape are converted to digital signals and stored in a solid-state electronic memory. (Even if the master recording is itself digital, it will normally be first converted to analogue for processing, such as Dolby (RTM) encoding, and then converted back to digital for loading into the digital bin.) The digital bin apparatus then "replays" the information in its memory to create a digital output stream which is then converted back to analogue for recording onto cassette tape.

Most known digital bins have a large memory block into which one programme may be loaded. If the programme is shorter than the total capacity of the memory then the spare memory is unused. This is a very significant disadvantage. The majority of the cost of a digital bin is in the memory chips. Six minutes 20 seconds of a single track of a stereo programme requires 32 M bytes. Therefore, a typical C100 (that is, fifty minutes per side in stereo) cassette requires 32 x 2 x16 M bytes or 1024 M bytes. Such memory, at todays prices, could cost 30,000.Therefore, when a cassette manufacturer specifies the size of a machine there is often a trade off between specifying a small memory so as not to have expensive memory sitting idle when a short programme is being stored and specifying a large enough memory for the machine to be able to handle the majorfity of programmes handled by that manufacturer.

One known way of reducing this problem is to provide a reasonably large memory capacity, say enough for C120 and divide this into two equal partitions. If a first programme is loaded into the memory, and fits entirely into one partition, then the second partition may be loaded at the same time as signals are being reproduced from the first. However, if one programme is longer, by however short a time, than the memory available in one partition then other partition cannot be used to receive a second programme, even if it is largely empty. Furthermore, such digital bins cannot reproduce information from more than one programme simultaneously.

From a first aspect, the present invention provides apparatus for storage and retrieval of digital information comprising an electronic memory, a plurality of input circuits for receiving digital information and storing it in the electronic memory, a plurality of output circuits for retrieving information from the electronic memory and outputting it, each one of the input circuits being associated with one of the output circuits to form an input ! output channel, wherein each channel can operate independently of the other channels, and the electronic memory being divided into a plurality of blocks, each of which may be allocated to one of the channels or deallocated and each of which operates independently of any other block.

The present invention can make optimum use of its memory. While data is being loaded in one channel, data may be being output run another. Furthermore, any memory block which is de-allocated is available for immediate allocation to a channel, ready to receive data.

Each channel is preferably provided with its own data bus and address bus through which the channel's input and output circuits access memory allocated to that channel.

Each input circuit and each output circuit may be permanently associated with one of the channels.

Alternatively, the input and/or the output circuits could be selectively allocated to one of the channels in a manner similar to the allocation of memory blocks to a channel. The latter arrangement is to be preferred because it allows greater flexibility in the use of the input and/or output circuits. More preferably the input and/or output circuits may be re-allocated independently of the memory blocks. This allows, for instance, an input circuit to be re-allocated for use on another channel once input to a first channel is complete.

The apparatus may further comprise a central controller to control allocation and de-allocation of memory blocks to the channels. In a preferred embodiment, each memory block has its own address decoding circuitry which is programmed by the central controller. The controller may send signals to the memory block to tell the circuitry to which channel (if any) the block is allocated and the address of the memory in the block. Preferably, after having been programmed, the memory block can continue to operate independently of the central controller until such time as the block is to be reallocated.

Preferably each block, or a small number of blocks, is mounted on its own circuit board. In this way, a circuit failure is limited in its effect to the small amount of memory contained on one board. The central controller may recognise that the board is faulty and that it should not be allocated. Similarly, the busses for each channel are preferably separate so that in the event that a bus fails only the channel associated with that bus is affected.

In one embodiment, memory is pre-allocated to a channel prior to loading the data. The central controller may keep a table of allocations of all memory blocks and when an operator requests allocation of memory to a channel prior to loading data, the controller searches the table for unallocated blocks which it then allocates to the channel. Preferably, the circuits within each block may be programmed to respond to any address so that a continuous logical memory map may be formed from physically discontiguous blocks.

In a typical embodiment, the output circuit will incorporate a digital-to-analogue converter and the input circuit will incorporate an analogue-to-digital converter. These converters may operate at audio frequencies.

Each channel may be able to handle several signals simultaneously. For example, in audio applications it is convenient to handle a stereo pair of signals, together or even two stereo pairs, one reversed in sequence, so that all four tracks (that is, two for each side) can be output to e.g. a tape recorder simultaneously.

Preferably, when de-allocated, a block remains connected to a dummy channel which has address lines (which may mimic the signals of a true channel) but no data lines. This minimises the likelihood of spurious signals being generated when a block is allocated or de-allocated.

The electronic memory may be dynamic RAM.

Refreshing of the memory is preferably carried out by independent circuitry for each channel. Each channel may be provided with its own clock signal, which may run at a different frequency from any other channel, so that the clock frequency may be adjusted in accordance with the data input or output rate of its channel.

From a second aspect, the present invention provides a method of storing data in an apparatus in accordance with the first aspect of the invention comprising calculating the memory capacity required to store the data, allocating sufficient blocks of memory to a channel of the apparatus and loading the data into the apparatus through the input circuit associated with the channel.

If the data is analogue data then it is converted to digital form prior to being stored in the memory of the apparatus.

The data may represent audio signals.

From a third aspect, the invention provides a method of duplicating data comprising storing data according to the second aspect of the invention, outputting data stored in the electronic memory to one or more aata recording devices, and de-allocating memory allocated to the channel once output is complete. The data may be output a plurality of times prior to de-allocation.

If the data is to be recorded in analogue form it may be converted from digital to analogue from prior to being output to the recording devices.

The recording devices may be magnetic tape recorders.

A fourth aspect of the invention provides, an electronic memory system comprising a set of electronic memory, a plurality of address busses, and a corresponding plurality of data busses, the set of memory being selectively partitioned such that each partition is connected to one of the address busses and a corresponding data bus, the set of memory being divided into a plurality of blocks, each of which may be allocated to a selected partition so as to function independently of blocks allocated to another partition, and remain so allocated until de-allocated. The allocation and de-allocation of the blocks is preferably controlled by a common controller.

In a fifth aspect, the invention provides a memory block for use in a memory system according to the fourth aspect of the invention.

An embodiment of the invention will now be described in detail by way of example with reference to the accompanying drawings in which: Figure 1 is a schematic block diagram of one channel of a tape duplicating "digital bin" embodying the invention; Figure 2 is a schematic block diagram of a memory block for use with the digital bin of Figure 1; Figure 3 is a schematic block diagram of a modification by which output devices may be selectively allocated to a channel; and Figure 4 is a diagram of a switching array by which input devices may be selectively allocated to a channel.

The Apparatus In a practical digital bin, four audio signals are processed simultaneously - two stereo pairs, one for each playing side of the tape. The embodiment will be described with reference to a single signal only, but in practice, each signal is processed similarly.

The digital bin, as shown in Figure 1, has a main storage memory 10. The storage memory 10 comprises a plurality of blocks, the first four of which Mot M1, M2, M3 are shown. In this example, the bin has three input/output channels. To give an average programme time of 25 minutes per signal (the length of one side of a typical music cassette) a total memory of 75 minutes per signal is chosen. The capacity of the whole machine would thus be 150 stereo minutes (CISO).

This memory is divided into a total of 12 blocks M0-M11. The total memory capacity of the bin is 1 G Bytes; 12 blocks, each containing four units of 32 M Bytes to store 4 signals of 6 mins 20 seconds in length. In fact, the machine has capacity to address 16 blocks but, for most purposes, this amount of memory would be excessive for a three-channel machine.

Each memory block is connected to three sets of busses. Each set comprises an address, control and timing bus A1, A2, A3 and a data bus D1, D2, D3.

Signals to be sent to the memory blocks are placed on the address, control and timing busses A1, A2, A3 by bus drivers BD1, BD2, BD3 each of which includes an address sequencer, a multiplexer, and a top-address latch. The data buses D1, D2, D3 are bi-directional, and handle incoming signals to be stored as well as outgoing signals received from the memory blocks MO-M3~ Incoming signals to be stored in the memory 10 are placed on the data busses by serial-to-parallel interfaces Spl, SP2, SP3. The inputs to these interfaces are connected to the digital signal inputs I1, 12, 13 of the digital bin.A digital-to-analogue interface DA1, DA2, DA3, is connected to each data bus D1, D2, D3 to receive signals placed onto a data bus by a memory block Mo-M3. The outputs of the digital-to analogue interfaces DA1, DA2, DA3, are connected to analogue outputs Oi, 02, 03 of the digital bin.

Each channel has a bus control microcomputer C1, C2, C3 The microcomputers C1, C2, c3 are connected to interfaces IF1, IF2, IF3 which have control outputs 12, including a clock line, connected to the bus drivers BD1, BD2 BD3 and control outputs 14 connected to the serial-to-parallel interfaces SP1, Sup2, SP, and to the digital-to-analogue interfaces DA1, DA2, DA3.

The microcomputers C1, C2, C3 receive derived word clock inputs 15 from the serial-to-parallel interfaces SPI1, SPI2, SPI3.

A crystal clock source 18 is connected to the interfaces IF1, IF2, IF3 by a read clock bus 16, a range of clock speeds being provided on the bus by the crystal clock source 18 corresponding to different output speeds. The interfaces IF1, IF2, IF3 incorporates a clock switch so that any one clock signal from the bus 16 or derived word clock signal 15 can be selected as the clock signal to be placed on the clock line of the control outputs 12 for operation of a channel.

The whole system is controlled by a central control microcomputer 19. This microcomputer 19 is connected by a common board address and bus allocation bus 17 to all of the memory blocks M0-M3.

Furthermore, each memory block is connected to the microcomputer 19 by its own latch line LLo-LL3.

A user-input device 21 such as an alphanumeric keyboard is connected to the central control microcomputer so that the operator of the system can enter data to control the operation of the system.

Internally, the central control microcomputer 19 maintains a table of the present allocation status of each memory block M0-M3.

Operation: Allocation of memory In operation, prior to storing data in the memory 10 blocks in which the data will be stored must first be allocated. Allocation is controlled by the central microcomputer 19.

In order to allocate the required memory blocks, the operator of the system first selects which channel (1,2 or 3) is to be used to store the data and enters the selection via the user input device 21.

Then, the operator must enter the quantity of data that is to be stored. For example, it will be assured that channel number m has been selected Having received this information the central control microcomputer 19 then attempts to allocate memory blocks to the channel.

First, the central control microcomputer 19 calculates the total number of memory blocks required to hold the data.

Then, the central control microcomputer 19 looks through the entries in its allocation table in turn until it finds an un-allocated block which it then allocates to the channel.

To allocate a block, for example, block number n the central control microcomputer 19 places the channel number together with a sequence number (explained below) onto the board address and bus allocation bus 17 and places a latching signal onto the latch line LL n of the memory block. When the memory block Mn receives a latching signal it reads the channel and sequence data from the board address and bus allocation bus 17 and stores them internally. The central control microcomputer 19 then updates its allocation table to record the allocation of the memory block and repeats the allocation process until the required number of blocks have been allocated.

The sequence number is used to order the memory blocks allocated to a channel. The sequence number is 0 for the first block allocated and is incremented for each successive block. The memory block uses its sequence number to decode the higher order lines of the address bus as will be described with reference to Figure 2.

Reading in data Once all of the required memory blocks have been allocated, data may be read into the memory. Data in the form of a bit stream from e.g. a DAT player or an analogue-to-digital converter is fed into the input Im for the allocated channel. Data from the input is fed to the corresponding serial-to-parallel interface SPIm which frames the bit stream into data words. The serial-to-parallel interface SPIm generates a clock signal synchronous with the framing operation. This signal is placed on the derived word clock input of the corresponding interface and the control microcomputer Cm instructs the interface IFm clock switch to use that signal as the clock signal for the channel. With a DAT source, the derived word clock signal may be the word synch signal from the DAT machine.

Each framed word is latched onto the corresponding data bus Dm by the serial-to-parallel interface SPI . On receipt of the derived word clock signal, the corresponding interface sends a signal via its control outputs 12 to its bus driver ED to set m up the busses to allow the data on the data bus D to m be written into memory.

The bus driver ED reads its address sequencer m (which is set to zero prior to the start of the read operation) and places the address on the corresponding address bus Am The address value in the sequencer is then incremented. A memory write signal is also placed on the control lines of the address bus Am.

The memory blocks receive these signals and decode the address. The memory block M0-M3 in which the particular address falls then reads the data from the data bus D and stores it in the appropriate memory m location. The entire reading process is repeated word by word, until all data has been stored, whereupon the address in the address sequencer is latched into the address latch of the bus driver BDm.

In storing music signals to be recorded onto a cassette tape, a pair of data streams representing a stereo pair of signals will be stored simultaneously, the above description representing one signal of such a pair, the other signal being stored in an identical manner in a duplicate storage system controlled by the same central control microprocessor 19. Subsequently or simultaneously a second stereo pair of signals, representing the second playing side of the final tape, is stored in a similar manner.

Operation: Output from memory After all of the data is stored it may then be read from the memory 10, as many times as is required, to generate an output signal. Again, the operation of a single signal channel only will be described.

The operator, by means of the user input device 21, instructs the central control microprocessor 19 that output is required. The operator must specify the rate at which the data is to be output. (For tape duplication, the output rate will typically be around 64 times normal speed while data input will generally be at normal speed from a DAT or CD source.) This information is then passed to the control microcomputer Cm for the particular channel.

The control computer Cm then instructs the interface IF clock switch to select the clock signal m from the read clock bus 16 appropriate to the output rate. Once this has been done, a signal is sent to the bus driver BDm to begin the output procedure.

In a manner similar to the storage of data, the address sequencer of the bus driver BDm is initially set to zero. At each clock signal, the address in the sequencer is placed on the address bus A together m with a memory read signal. The appropriate memory block then places the value stored in the address onto the data bus Dm.

A clock signal is also sent to the appropriate digital-to-analogue interface DAIm which on receipt of the signal reads the data bus D and generates an m analogue output signal from the data thereon. The analogue signal is then fed to the corresponding output m and thence to recording apparatus.

Output of four signals for two stereo pairs takes place simultaneously. This requires two of the signals to be reversed in sequence since a cassette tape has a pair of stereo signals on each of two playing sides, the direction of tape travel being reversed in changing from one side to the other. In order to achieve this, the address sequencer responsible for controlling the reversed outputs are initially loaded with the top address stored in the address latch, and the sequencer decrements the address after each byte is read from memory. The central control microcomputer 19 delays the start of output of the reversed signals, if necessary, to ensure that output of the reversed signals does not finish before output of the forward signals as this would lead to an un-recorded portion at the start of one playing side of the cassette.

After all of the programme has been output, the output operation is repeated until the required number of duplicates has been made and the output process is interrupted by the operator.

Operation: De-allocation of memory After all output from a channel has been completed, its memory must be de-allocated. To de-allocate the memory, the central control microcomputer 19 examines each item in its allocation table in turn. When it finds and entry for a block allocated to the channel in question, it re-allocates that block to channel 0, and updates the allocation table to record the block as unallocated. Channel O is a dummy channel which shares an address and control bus A1 with channel 1, but has no data bus. Thus an unallocated memory block continues to receive timing and control signals from the address and control bus A1 but does not affect the data on any data bus.

Description of a Memory Block A memory block M will now be described with n reference to Figure 2.

The memory block M contains a set of electronic memory 20. The electronic memory 20 is typically dynamic RAM which is preferred for its high access speed, small size, and low power consumption, but any other type of memory could be used, particularly as technological advances may make higher performance memory available.

Inputs from the address, control and timing buses A1-A3 and from the data busses D1-D3 are received into individual buffers AB1, to AB3 and DB1 to DB3 in the memory block. The outputs from the address bus buffers AB1 AB3 are connected to a common internal address bus 22 and the outputs from the data bus buffers DB1-DB3 are connected to a common internal data bus 24. The buffers AB1-AB3, DB1-DB3 are normally disconnected from the internal busses 22,24. Each buffer AB1-AB3, DB1-DB3 has at least one enabling input line to which signal can be to cause the buffer to connect itself to an internal bus 22,24.

Input from the board and bus allocation bus 17 is fed to a latch 26. The latch 26 has an input connected to the latch line LL n for the particular memory block Mn When a signal is received on the latch line LLn, data is copied from the block allocation and bus address bus 17, into the latch 26.

The latch 26 has two output busses: a bus allocation bus 28 and a board address bus 32. The part of the latched data which corresponds to the board address, as determined by the central control microcomputer 19, is output onto the bus allocation bus 28 while the sequence data is output onto the board address bus 32. The output remains constant until another signal is received on the latch line LLn, generally this will be when the memory block M is n re-allocated.

A decoder 30 receives signals from the bus allocation bus 28. In response to these signals it generates an output signal on one of four output lines ENO to EN3. The lines EN1 to EN3 are connected to the enabling input lines of the corresponding data buffers and address buffers AB1 to AB3 and DB1 to DB3. Thus, a signal on line EN2 enables buffers AB2 and DB, so connecting the memory block Mn to address and control bus A2 and data bus D2. Line EN, is connected to the enabling line of address buffer BA1 only. A signal on this line ENO thus puts the memory block Mn into a de-allocated state.

A comparator 34 receives input signals from the board address bus 32 and from the internal address bus 22. Whenever the high-order bits of the address on the internal address bus 22 equal those on the board address bus 32, the comparator generates and output signal on an equal-signal line 36. A board-on latch 38 has the equal-signal line 36 as its data input and its latch line 40 is connected to the clock signal. Thus, at each clock pulse, the signal on the equal-signal line 36 is latched onto the output of the latch 38.

The output of the latch 38 constitutes a memory enable line 42 which is connected to the electronic memory 20. When the electronic memory 20 receives an enabling signal on the enable line 42 it reads the address on the internal address bus 20, and copies data between the memory word with that address and the internal data bus 24, the nature of the operation (read or write) being determined by the control signals on the internal address bus 22.

Allocation of Input and Output Devices Figure 3 shows a modification by which output circuits may be selectively allocated to a channel. By way of example, three output circuits are shown, 0'1, 0'2, 0'3. In applying the modification, each output circuit 0'1 - 0'3 replaces a digital-to-analogue interface DAl1-DAI3 and an input 01#0 3 as described with reference to Figure 1. The output circuits could incorporate a digital-to-analogue interface for generating analogue signals for recording on cassette tape, a digital interface for generating output for DAT or the forthcoming Digital Compact Cassette, or any other interface suitable for generating signals acceptable to any other type of recording equipment whether already known or as yet to be developed. It will be appreciated that any number of output circuits may be provided, appropriate to the particular application.

Each output circuit Oil - O' is connected to 3 the data busses D1 -D3, to the bus allocation lines 17'of the board address and bus allocation bus 17. Each output circuit also has a latch line LL'1-LL'3 connected to the central control microcomputer 19.

Internally, each output circuit 0'1 '3 has a latch, a bus allocation bus, a decoder, and data buffers which receive signals from the bus allocation lines 17' and the latch lines LL'1#LL'3 and operate to allocate the output circuit 0'1 '3 to a channel as do the corresponding components in a memory block, as described above.

The interface circuits of the output circuits 0'1- 0'3 then read data from the data bus D'1-D'3 3 to which they are allocated and generate output signals accordingly.

Input circuits may be allocated to channels in a manner similar to the above. Alternatively a simple cross-point switching array, as illustrated in Figure 4, could be used to connect any one of a number of input lines IA-IE to the inputs I1- I3. The switching array would be controlled by the central control microcomputer 19.

Claims (16)

1. Apparatus for storage and retrieval of digital information comprising an electronic memory, a plurality of input circuits for receiving digital information and storing it in the electronic memory, a plurality of output circuits for retrieving information from the electronic memory and outputting it, each one of the input circuits being associated with one of the output circuits to form an input/output channel, wherein each channel can operate independently of the other channels, and the electronic memory being divided into a plurality of blocks, each of which may be allocated to one of the channels or de-allocated and each of which operates independently of any other block.

2. Apparatus according to claim 1 in which each channel is provided with its own data bus and address bus through which the channel's input and output circuits access memory allocated to that channel.

3. Apparatus according to claim 1 or claim 2 in which the input and/or the output circuits may be selectively allocated to one of the channels.

4. Apparatus according to claim 3 in which the input and/or the output circuits may be re-allocated to a channel independently of the memory blocks.

5. Apparatus according to any preceding claim which further comprises a central controller to control allocation and de-allocation of memory blocks to the channels.

6. Apparatus according to claim 5 in which each memory block comprises address decoding circuitry, to which the central controller sends signals to allocate the block to a channel.

7. Apparatus according to claim 5 or claim 6 in which each memory block can continue to operate independently of the central controller after having been allocated to a channel until such time as the block is re-allocated.

8. Apparatus according to any one of claims 5 to claim 7 in which memory is pre-allocated to a channel prior to loading the data, and in which the central controller keeps a table of allocations of all memory blocks, wherein when an operator requests allocation of memory to a channel prior to loading data, the controller searches the table for unallocated blocks which it then allocates to the channel.

9. Apparatus according to any preceding claim in which circuits within each block may be programmed to respond to any address so that a continuous logical memory map may be formed from physically discontigous blocks.

10. Apparatus according to any preceding claim in which the output circuits incorporate a digital-to-analogue converter and the input circuits incorporate an analogue-to-digital converter.

11. Apparatus according to any preceding claim in which the digital information represents audio signals.

12. Apparatus according to any preceding claim in which, when de-allocated, a block remains connected to a dummy channel which has address lines which mimic the signals of a true channel but no data lines.

13. Apparatus according to any preceding claim in which is provided with its own clock signal, which may run at a different frequency from any other channel, so that the clock frequency may be adjusted in accordance with the data input or output rate of its channel.

14. Apparatus for storage and retrieval of digital information substantially as described with reference to the accompanying drawings.

15. A method of storing data in an apparatus according to any preceding claim comprising calculating the memory capacity required to store the data, allocating sufficient blocks of memory to a channel of the apparatus and loading the data into the apparatus through the input circuit associated with the channel.

16. A method of duplicating data comprising storing data by a method according to claim 15, outputting data stored in the electronic memory to one or more data recording devices, and de-allocating memory allocated to the channel once output is complete.