GB2254211A

GB2254211A - Current mirrors

Info

Publication number: GB2254211A
Application number: GB9012734A
Authority: GB
Inventors: Andreas Rusznyak
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1990-06-07
Filing date: 1990-06-07
Publication date: 1992-09-30
Also published as: GB9012734D0

Abstract

A current mirror 20 includes a first MOS transistor Q3 and a second MOS transistor Q4. The arrangement includes switches 21, 22, 23 and 24 arranged into a crossover network 25 comprising two pairs of change over switches, respectively switch pair 21 and 24 and switch pair 22 and 23. The arrangement is such the drain of Q3 may be connected to the input (switch 21 closed, switch 24 open) or the output (switch 21 open, switch 24 closed) and that the same is true with respect to Q4 (in switches 22 and 23). When Q3 is connected to the input and Q4 to the output a current mirror is formed with Q3 as sense and Q4 as output transistor and when Q4 is connected to the input and Q3 to the output a current mirror is formed with Q4 as sense and Q3 as output transistor. <IMAGE>

Description

IMPROVEMENTS IN OR RELATING TO MOS CURRENT MTRRORS The present invention relates to Current Mirror arrangements formed in Metal Oxide Semi-conductor (MOS) technology.

In many MOS circuits, some analogue functionality is required, and a commonly encountered building block is the current mirror.

A current mirror circuit has the property of generating a current at an output which is equal to or in fixed proportion to a current received at an input. This property is useful for example in reference, comparator and digital to analogue converter circuits amongst many others. The property derives from circuit arrangements which exploit the close matching of the characteristics of structurally identical integrated devices. For good performance, the ratio of the generated output current to the input current has to be very accurate.

In practical use, however, in MOS technology there can be some dependence on fabrication processes which results in different characteristics for devices of nominally the same construction. In fact, MOS processes exhibit such tolerances and variations to a degree where in many situations circuits requiring absolute values or characteristics of components for accuracy are impractical.

Typically a current mirror circuit includes a sensing transistor and an output transistor. The sensing transistor serves to derive a control signal from the input current which is applied to the output transistor to drive the output to the required current. The design objective is that variations due to fabrication process tolerances arising in the sensing and output transistors are compensated. To this end, it is common practice to make the transistors of identical geometry, to place input and output transistors proximate in the integrated circuit so that they are subject to similar local effects, and to place one of the transistors to be matched between the other partitioned in two halves for example.

An improvement is always desirable, however, and to this end it has been suggested to utilize the well known storage capability of MOS transistors, that is used in sample and hold circuits for example, in a current mirror equivalent. The arrangement relies on the fact that MOS transistors require no current on the gate, on which voltage may temporarily be stored. In an arrangement published by G. Weggman and E.A. Vittoz (Very Accurate Dynamic Current Mirrors, Electronic Letters [Vol. 25(89), No. 10]), a transistor is used in a sampling phase to sense the input current, the sense value being stored as aforesaid to control one and the same transistor operating as the output transistor during a subsequent output phase. Since a current mirror must provide a continuous output, at least two such arrangements must be combined to form a single current mirror.

Drawbacks of the arrangement referenced above include the total vulnerability to degradation of the stored sample due to leakage currents and the parasitic coupling of extraneous signals to the floating gate controlling the output current.

In accordance with the present invention a current mirror for generating an output current mirroring an input current includes at least one pair of metal oxide semi-conductor transistors, each having a gate connected to an input current defined voltage, and switch means for selectively connecting either the drain of a first transistor of the pair to the input and the drain of the second transistor of the pair to the output or the drain of the second transistor to the input and the drain of the first transistor to the output.

Preferably the arrangement includes a clock signal input, the clock signal being arranged to alter said selection periodically.

Advantageously, the clock signal is of 50% duty cycle.

Advantageously said alternative connections are made by a cross coupling network which may include changeover switches.

In order that features and advantages of the present invention may be further appreciated, embodiments will now be described with reference to the accompanying diagrammatic drawings, of which: Fig 1 (a) and Fig l (b) represent prior art current mirrors, Fig 2 represents a current mirror in accordance with the present invention, Fig 3 represents a further embodiment of a current mirror in accordance with the present invention, Fig 4 represents a yet further embodiment of a current mirror in accordance with the present invention,and In a simple and classical two transistor current mirror 10 (Fig 1(a)) Ql acts as a sensing transistor and controls Q2 as output transistor.The drain current of an MOS transistor working in saturation is described to a good approximation by an expression of the form: I = K(VG - VT)2 where K is geometry and process dependent, VG is the gate to source control voltage and VT is threshold voltage of the transistor, also being process dependent.If the transistors Q1 and Q2 are characterized by values K1, VT1 and K2, VT2 respectively, then the output current (I2) for a given input I1 will be:

calculating the mirroring ratio error Ar = I2/Il-1 for mismatch of the value of K between devices (K1 = K + AK, K2 = K - AK) yields: = = K+AK 1 = 2AK ~ 2AK K-AK K-AK K Hence for a mismatch (AK/K) of 5%, the mirroring error would be about 10%.

Similarly, for threshold voltage mismatches (VT1 = VT + AVT, VT2 = VT - AVT) is:

For a typical value of (Ve - VT) = 250 mV a mismatch of AVT = l0mV would result in an error of about S%.

The equations presented above refer to the prior art current mirror arrangement shown in Fig 1(a), but also apply in principal to that shown in Fig 1(b), which will be recognised as the well known Wilson type current mirror which has improved mirroring characteristics by cancellation of the influence of the drain voltage of the output transistor on the output current.

A current mirror 20 in accordance with the present invention (Fig 2) includes a first MOS transistor Q3 and a second MOS transistor Q4. The arrangement includes switches 21, 22, 23 and 24 arranged into a network 25 comprising switch pair 21 and 24 and switch pair 22 and 23. The arrangement is such the drain of Q3 may be connected to the input 26 (switch 21 closed, switch 24 open) or to the output 27 (switch 21 open, switch 24 closed) and that the same is true with respect to Q4 ( switches 22 and 23). It will be appreciated that when Q3 is connected to the input and Q4 to the output a current mirror is formed with Q3 as sense and Q4 as output transistor and that when Q4 is connected to the input and Q3 to the output a current mirror is formed with Q4 as sense and Q3 as output transistor.

Hence the r6les of the transistors may be interchanged.

If this is done periodically then the average output current 14 for an input current 13 will be given by:

where notation common with that of equation (1) has been used.

As to current mirroring error,

yielding a value of about 0.25% for a 5% mismatch, and

giving an error of 0.16% for a l0mV mismatch and (VG - VT) of 250mV. Both error figures are a considerable improvement on the prior art mirror.

In the present embodiment it will be noted that the may be driven by complementary clock signals 4)1 and 2, generated to have a 50% duty cycle, switches 21 and 22 being closed when 4)1 is high and open when it is low and switch 23 and 24 being closed when 4)2 is high and open when it is low.

The required clock signals and accurate switches required to implement the embodiment are straightforwardly available in MOS technology. As switches for example the well known transmission gate arrangement of parallel connected n and p channel transistors controlled by complementary signals may be used.

As to the frequency of the interchange, since the present invention provides an output the average value of which is improved, the period of the switching waveform should be selected to be short compared with the time over which the output is to be stable. If such a selection is impractical, external integrating stabilisation may be applied to the output.

With respect to the embodiment of Fig 2, it will be recalled that transistors Q3 and Q4 alternately act as respectively sense and output transistors of a simple current mirror arrangement analogous to that of Fig l(a). Because the rules of the transistors are periodically interchanged, however, any error due to transistor mismatch are compensated.

In the embodiment of Fig 3, the concept is extended to the Wilson form of current mirror, equivalent to Fig 1(b), having compensating transistors Q5 and Q6 (equivalent to Qci and Qc2) In this embodiment transistors Q7 and Q8 alternately act as sense and output transistors. In the alternative embodiment of Fig 4, the roles of both the compensation transistors Q14 and Q15 and the sense and output transistors Q16 and Q17 are periodically interchanged.

It will be realised that a current mirror in accordance with the present invention not only reduces mirroring errors due to device mismatch but because the gates of the transistors are never left floating, no error due to parasitic coupling or charge leakage can occur.

It will be appreciated that the invention is equally applicable to other forms of current mirror. It will further be appreciated that because the input is continuously sensed and the output continuously driven, input changes are tracked any output changes at commutation are principally due to device mismatches rather than device mismatches and cumulative error since the last sample.

Hence step changes in the output are much reduced.

Claims

1. A current mirror for generating an output current mirroring an input current, including at least one pair of metal oxide semiconductor transistors, each having a gate connected to an input current defined voltage, and switch means for selectively connecting either the drain of a first transistor of the pair to the input and the drain of the second transistor of the pair to the output or the drain of the second transistor to the input and the drain of the first transistor to the output.

2. A current mirror as claimed in claim 1 and including a clock signal input, the clock signal being arranged to alter said selection periodically.

3. A current mirror as claimed in any preceding claim and wherein the first and second transistors respectively, when connected to the input act as a sense transistor and when connected to the output act as an output transistor.

4. A current mirror as claimed in any preceding claim and wherein the first and second transistors are compensation transistors.

5. A current mirror substantially as hereindescribed with reference to Figures 2 to 5 of the accompanying drawings.