GB2252224A - Providing an overlay e.g. a cursor, for a computer display - Google Patents

Abstract

The computer system has a frame buffer 31 and output apparatus 33 for utilizing an image in the frame buffer. A circuit for overlaying information on the computer image includes a line buffer 34 for storing overlay information of no more than a single scan line in length, apparatus for providing individual lines of overlay information from the frame buffer 31 to the line buffer 34, apparatus for determining when a scan line of information and an overlay coincide, and apparatus for using the overlay information to modify the output image at positions where an overlay and an image coincide. By storing overlay information in the frame buffer the invention dispenses with the relatively expensive overlay memory (14, fig 1). <IMAGE>

Description

CIRCUITRY FOR PROVIDING AN OVERLAY FOR A COMPUTER OUrPUT DISPLAY BACKGROUND OF THE INVENTION 1. Field of the Invention: This invention relates to computer circuitry and, more particularly, to apparatus for generating a cursor or other overlay to be displayed on a computer output display.

2. Ristory of the Prior Art: In order to facilitate the use of computers, a cursor is used to indicate precisely the position at which some operation is to take place. In order to cause a cursor to appear on the output display of a computer, it is necessary to place the image of the cursor in some form of memory so that it may be written to the display at the selected position. If the cursor image is placed in the frame buffer memory along with other information to be displayed, it is difficult to keep it from being overwritten. This is especially true in advanced systems which utilize multiple processors or DMS devices which may write to the frame buffer. Consequently, it is typical that the memory in which the cursor image is placed is a cursor memory separate from the frame buffer.For example, a small buffer memory just large enough to provide storage for the specific cursor overlay is often used; such a cursor overlay might store sixty-four by sixty-four pixels. However, it is typical for such a cursor memory to utilize much more expensive memory than the video random access memory of a frame buffer to store the cursor image. Because of the expense of this memory, usually only a few bits (e.g., two) are stored for each pixel position of the cursor overlay memory. Data defining the shape of the cursor is placed in the cursor memory by the central processing unit, and dedicated control hardware selects between the background pixels of the frame buffer image and the cursor image as the frame buffer image is scanned to the output display.

One difficulty with such a cursor memory is that it is generally constrained to be such a small amount of storage that it can be used only to display a very fe shades of color. A full range of color cannot be obtained for the cursor where only two bits per pixel of storage are provided.

The small amount of memory available for such a memory also means that the cursor memory cannot be used for more than the simple description of a cursor. That is, it does not provide sufficient storage that it may be used as a device for providing any form of generalized overlay that might be desired.

A typical frame buffer is designed with standard memory devices which are only available in discrete sizes such as one-quarter of a megabit and one megabit. Using these devices a frame buffer can be constructed of sizes such as one-quarter of a megabyte, one-half of a megabyte, or one megabyte. For this reason there is typically unused memory in the frame buffer when the number of pixels of the output display size does not match the number of pixels which can be stored in the frame buffer memory. For example, a standard display size of 640 X 480 pixels contains approximately 300,000 pi > ;els. If the frame buffer contains one-half a megabyte of storage and each pixel requires one byte, about 200,000 bytes of frame buffer memory remain unused.The extra memory can be used for secondary applications; but, in general, this is not a cost effective use of frame buffer memory.

One method of providing a general overlay is to utilize a separate frame buffer for the overlay and merge the outputs of the standard frame buffer and the overlay frame buffer on the output display. In general, this organization requires separate memory devices to store the background and overlay images which is more expensive and is an inefficient use of the memory devices for the reasons discussed above.

Furthermore, if the overlay can be restricted to a small portion of the output display, such as is the case for the 64 X 64 cursor application, almost all of the overlay memory remains unused.

SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide improved circuitry for presenting a cursor on a computer output display.

It is another object of the present invention to provide apparatus for generating cursors and other dynamic overlays for presentation with a background image on a computer output display utilizing the storage space in standard memory devices as efficiently as possible to store both the background and overlay images.

It is an additional object of the present invention to provide apparatus for presenting economically a full colored cursor on a computer output display which apparatus may conveniently be extended to present generalized overlays on the display.

These and other objects of the present invention are realized in a circuit for overlaying information on a computer image comprising means for storing overlay information of no more than a single scan line in length, means for providing individual lines of overlay information to the means for storing overlay information, means for determining when a scan line of information and an overlay coincide, and means for using the overlay information to modify the output image at positions where an overlay and an image coincide.

These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram illustrating a circuit constructed in accordance with the prior art.

Figure 2 is another block diagram illustrating a circuit in accordance with the invention.

Figure 3 is a more detailed block diagram illustrating a circuit in accordance with the invention.

NOTATION AND NOMENCLATURE Some portions of the detailed descriptions which follow are presented in terms of representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.

Further, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind. The present invention relates to apparatus for operating a computer in processing electrical or other (e.g.

mechanical, chemical) physical signals to generate other desired physical signals.

DETAILED DESCRIPTION OF THE INVENTION Referring now to Figure 1, there is shown a circuit 10 constructed in accordance with the prior art. The circuit 10 includes a frame buffer 12 which may be constructed of video random access memory in a manner well known to the prior art.

The circuit 10 also includes a second overlay memory circuit 14 which may be constructed from specialized static random access memory or dynamic random access memory. The frame buffer 12 contains memory space sufficient to store all of the background information which is to be transferred to an output display device in a single output frame. Typically, this may include extra memory because of the limited standard sizes of memory devices. The overlay memory circuit 14, on the other hand, contains memory space only sufficient to store all of the information which is necessary to describe a particular cursor overlay. For example, a cursor to be presented over the background information provided by the frame buffer 12 on an output display device may require thirty-two by thirty-two pixels each of which may store two bits of binary information.Typically, the cursor image in the overlay memory 14 is updated by the associated central processor when it is desired to change the cursor image.

The circuit 10 also includes circuitry 16 for merging information contained in the frame buffer 12 and the memory circuit 14 under control of information provided by control circuitry 15 to select whether background or overlay information is to be provided at any particular pixel position. Information transferred by the circuitry 16 is processed by a digital-to-analog converter 18 and transferred for display by an output display device 20.

The overlay memory 14, the digital-to-analog converter 18, and the multiplexor 16 may be built as an integrated part. However, due to the unique size and integration of the overlay memory 14, it is much more expensive per bit than is the standard memory used to construct the frame buffer 12.

Because it is so expensive, the number of bits allowed for each pixel position in the overlay memory 14 are often reduced to a minimum (e.g., one or two bits). For this reason, the overlay is typically limited to presenting only the cursor shape and does not include the full range of colors which are used in the frame buffer 12. Examples of application specific memories used to present cursors as described are a Monolithic CMOS 64-X 64 Pixel Cursor Generator, BT431, manufactured by Brooktree, San Diego, California, which provides one bit per pixel; and a Triple 8 Bit RamDac with On-Chip 64 X 64 Pixel Cursor, also manufactured by Brooktree, which provides two bits per pixel as well as integrating the multiplexor and digital to analog converter.

As will be appreciated by those skilled in the art, such a small amount of memory is unable to provide sufficient storage for matching the full color storage of a frame buffer which may store twenty-four bits of color information for each pixel. Moreover, such an overlay memory is unable to provide sufficient storage for providing any sort of general overlay with the background display. In order to accomplish the presentation of a general purpose overlay, it would be more typical to utilize a separate frame buffer for the overlay and merge the outputs of the standard frame buffer and the overlay frame buffer on the output display. However, as pointed out above, this requires separate memory devices for the background and overlay images, an inefficient use of the frame buffer memories.Moreover, it can be prohibitively expensive, for the cost of memory tends to be one of the single most expensive items in the manufacture of a computer output display system.

Figure 2 illustrates in block diagram a circuit 30 constructed in accordance with the present invention and adapted to more efficiently utilize the physical memory available while still presenting a cursor or a generalized overlay on an output display device. The circuit 30 includes a frame buffer 31 in which is stored the background image to the presented on an output display device 33. Also included in the circuit 30 is a scan line overlay memory 34 capable of containing a single display scan line (or less) of overlay information.

The frame buffer 31 contains sufficient memory space to store the normal display and, in addition, the information to be presented as an overlay to the background image. A frame buffer will typically contain some amount of unused memory which may be evenly distributed across each line of the display. This memory is typically skipped over during the horizontal refresh period but may be used to store overlay information. Thus, the frame buffer will contain for each line of the output display a first sequence of space sufficient to store the pixels to be overlaid followed by a second sequence of space to store a scan line of background pixels for the output display; this first and second sequence of memory repeats with each scan line.This presumes that the total amount of unused memory available, when evenly distributed across each scan line of the background display, provides sufficient storage on each instance for a single scan line of an overlay which is basically rectangular in aspect.

Alternatively, the frame buffer may be organized such that the scan lines of the background and overlay images are not interleaved , but are stored separately and sequentially in memory. This memory organization provides for a more efficient storage of the overlay image when the overlay is limited to a small number of scan lines. Discussion of this method is deferred due to the complications introduced by this optimization. The following discussion assumes the extra memory evenly distributed throughout the frame buffer memory as presented above.

Information to be displayed by the output display device 33 is stored in the frame buffer 31 in a conventional manner.

Information to be provided as a overlay is also stored in the frame buffer at positions which may be any of the empty spaces mentioned. Since each pixel position in the frame buffer 31 may be constructed to include thirty-two bits of data in order to provide a twenty-four bit color display, each unused pixel position offers this thirty-two bits of storage for storing overlay information. During the horizontal blanking period prior to displaying a scan line of the background image on the output display, the control circuit 35 determines if the overlay covers a portion of the scan line. If it is possible for the overlay to be displayed as part of the scan line, the circuit 35 causes the overlay information for that line to be transferred from the frame buffer 31 to the overlay memory 34.The transfer takes place during the horizontal refresh period in which background data is not being furnished to the display and the frame buffer 31 is typically idle. Then, as the raster scans information to the display 33, circuitry 36 selects the appropriate data to be presented on the output display device 33 from the information stored in the frame buffer memory 31 and the overlay memory 34.

It is possible to scan this overlay information from the frame buffer 31 into the memory 34 during the period of the horizontal retrace, a time during which no information is normally being transferred from the frame buffer 31 because of the retrace operation. In such a situation, when the control circuitry determines that the succeeding scan line to be displayed on the output display 33 may contain overlay information, it scans the first line of the overlay from the frame buffer 31 to the memory 34 during the horizontal blanking period prior to the active video. This information is available for merging with the background information stored in the frame buffer 31 during the next scan line. For example, the frame buffer may store the overlay information at the end of each line of background information.In that case, at the end of the line of background information which is displayed on the output device 33, the next line of the overlay information stored in the frame buffer 31 is scanned to the memory 34 during the horizontal blanking period so that it is available to be merged with the next line to be displayed. This process continues line by line for as long as the scan line traverses the overlay region.

It will be understood that if the arrangement is such that overlay information for each scan line may be stored at the end of the data describing the scan line just proceeding the line for which the information is to be used, then the operation may proceed at an optimum rate. This will occur because the addresses of the overlay data appear in sequential order immediately after the background for the preceding scan line. Thus, addressing the overlay information does not require access ofrentirely independent addresses within the frame buffer 31 as would be the case were the overlay information to be stored in some other block of free memory.

If the memory 34 is large enough to store a full scan line of information and if there is sufficient free space in the frame buffer 31,then it is possible-to define an overlay region which covers the entire face of the output display device 33. Typically, where the overlay is used for defining a cursor, the single line memory 34 need only include sufficient memory space to hold enough for the width of the cursor. For a larger overlay, additional space will be needed in the buffer 34.

However, if the overlay memory 34 can only be of a fixed size, dictated primarily by cost, the number of bits stored for each overlay pixel can be varied to increase or decrease the number of overlay pixels per scan line. For example, if there is sufficient memory to produce a single overlay line of thirty-two pixels each of thirty-two bits, it is also possible use this same storage space to provide 128 pixels each of eight bits or 1024 pixels each of one bit. In many cases, pixels of less than full color are sufficient and this much storage is adapted to provide an overlay of minimal color variation which covers the entire display. In order to accomplish this, a multiplexor 38 is illustrated in Figure 2.

The multiplexor receives control information from the circuit 35 as to the number of bits to be used for each pixel. By varying the number of bits chosen, the size of the overlay covered by the memory 34 may be varied.

Figure 3 illustrates in detail a circuit 40 for carrying out the invention. The circuit 40 comprises a frame buffer 41 constructed in accordance with the prior art but having sufficient storage space to include therein the information describing the overlay. The frame buffer 41 receives control information from a frame buffer address generation and control circuit 44 which accomplishes the presentation of the appropriate information to a digital-to-analog converter 50 for display on an output display device 52. Providing signals to the control circuit 44 are a screen refresh logic circuit 45 and an overlay refresh logic circuit 47.

A scan line overlay memory 42 is adapted to store information provided regarding no more than a single display scan line of the overlay to be presented. The overlay information is merged with the image scan line information held in the frame buffer 41 by a multiplexor 48 under control of the circuit 47. The determination at any particular pixel of the overlay whether the overlay or the background information is to be furnished is accomplished in a preferred embodiment by a mask stored with each pixel of the overlay.

For a simple determination that overlay or background is to be furnished at that pixel, a single bit will suffice to provide the control. However, since in a preferred embodiment each pixel position in the frame buffer 41 and the scan line overlay memory 42 may store thirty-two bits of information, a great deal of additional information for controlling merging or for providing additional overlay colors may be utilized in the overlay.More complicated overlays may be accomplished in the manner described in the copending patent application serial no. , entitled APPARATUS FOR GENFRATING A CURSOR OR OTHER OVERERY WHTCH CONTRP.STS ITH THE BACKGROUND ON A COMPUTER OUTPUT DTSPLAY, W Dawson et al, filed on even date herewith, and assigned to the assignee of this invention.

The circuit 45 includes the typical pixel clock 55 used to control the transfer of information from a frame buffer to an output display. The clock 55 generates a stream of clock pulses which are transferred to a screen pixel counter 56.

The counter 56 maintains a count corresponding to the pixel location of the raster refresh during each retrace of the display scan line. The total counted by the counter 56 is transferred to a pair of comparators 57 and 58. The comparator 58 also receives a signal B~ACTH which indicates the count value for the beginning of the active video display. The comparator 58 compares the pixel count to the B~ACTH count and when the value of the counts are equal, signals the circuit 44 so that the transfer of background display information may be begun for each scan line. The comparator 57 also receives a signal E~ACTH which indicates the end of the active video display.The comparator 57 compares the pixel count to the E~ACTH count and when the values of the counts are equal, signals the circuit 44 to initiate the horizontal blanking period which terminates the background display for each line and begins the transfer of the overlay information to be displayed on the next scan line. The comparator 57 also provides a reset pulse to reset the count held in the pixel counter 56 as each horizontal line (or row) of the image and overlay to be displayed is completed.

The reset pulse is also transferred as input to a screen line counter 59 so that the number of lines in the total height of the image may be counted. The screen line counter 59 furnishes an output count equal to the particular line of the display being traversed. This output is compared by a pair of comparators which receive, respectively, line begin signal B~ACTV and line end signal E~ACTV and thus provide to the control circuit 44 signals indicating the beginning of the first line and the end of the last line of the active display.

Thus, the screen refresh logic circuit 45 provides the information necessary for the control circuit 44 to control the refresh of the display 52. The circuit 47, on the other hand furnishes the information necessary to determine where the overlay data stored in the scan line overlay memory 42 is to appear on the display and indicates to the control circuit 44 when the scan line overlay memory 42 is to receive information from the frame buffer 41.

This is accomplished as follows. As each pixel of the scan line is counted, the output of the pixel counter 56 is transferred to first and second comparators 61 and 62 which compare the pixel position within the scan line with the horizontal start position and the horizontal end position of the overlay, respectively. These values may be furnished by the central processing unit and held in registers for use by the comparators 61 and 62 on each scan line. If the pixel position on the scan line lies within the beginning and ending values of the overlay, a horizontal control circuit 64 provides a horizontal enable signal to an AND gate 65 and to the overlay pixel counter 67 which may enable the multiplexor 48 to allow the transfer of the overlay information.The counter 67 provides address information to the scan line overlay memory 42 so that the appropriate pixel may be transferred to the multiplexor 48 and thence to the display 52.

As the last pixel of a line of the overlay arrives as signalled by the comparator 62, the horizontal control circuit 64 provides a reset pulse to an overlay pixel counter 67.

As pointed out, the screen line counter 59 which counts the number of scan lines which have been furnished in a particular frame furnishes this information to the control circuit 44 so that a control signal may be sent to initiate the vertical blanking and screen refresh. This signal is also transferred to a pair of comparators 70 and 71 which compare the values of the start and end of the vertical limits of the overlay with the scan line position. During a period in which the vertical position of the scan line lies within the vertical limits of the overlay, a vertical control circuit 73 provides a signal to the AND gate 65.

The vertical control circuit 73 also indicates to the control circuit 44 the period during which overlay information may be displayed on the screen so that overlay information may be transferred to refresh the overlay memory prior to the beginning of each horizontal line of the image.

Thus, during the period of the blanked horizontal retrace, if the line count for the current line is within the vertical overlay range, as defined by the V~STRT and V~END, overlay information is transferred from the frame buffer 41 to the scan line overlay memory 42.

The AND gate 65 is provided in order to allow selected portions of the overlay information stored in the memory 42 to be merged with the image information. The simultaneous application of the vertical and horizontal signals to the AND gate 65 allows the mask information stored with each pixel of the overlay in the overlay memory 42 to control the transfer of overlay or background information for display. Thus, where the mask information signals that the particular pixel of the overlay is to be displayed, this mask signal to the AND gate 65 causes the information from the memory 42 to be transferred to the converter 50 for display. When the mask information signal indicates that the overlay is transparent, the gate 65 allows the image information to be transferred to the display.In this manner, the transfer of overlay or background information is controlled within the overlay region of the display Obviously, other uses may be made of the overlay information than simply to furnish that information to the output display device. For example, circuitry described in co-pending patent application Serial No. , entitled APPARATUS FOR GENERATING A CURSOR OR OTHER OVERLAY WHICH CONTRASTS WITH THE EACKGROUND ON A COMPUTER OUTPUT DISPLAY, W. Dawson, filed on even date herewith, and assigned to the assignee of this invention describes circuitry which allows masking signals stored with each of the pixels of the overlay to provide for contrasting the information in the overlay and the image in order to provide enhanced definition and for providing the anti-aliasing of the edges of the overlay.

Thus, it will be appreciated that the present invention provides circuitry which allows a dynamic overlay to be presented on an output display device without the necessity of including a substantial amount of overlay memory circuitry. The present arrangement adds only sufficient specialized (expensive) memory for the storage of a single line or less of overlay. Moreover, the use of a single scan line memory which is filled from the frame buffer itself during a period in which the output from the frame buffer would otherwise be unused both increases the utilization of the actual memory space in the frame buffer and makes more efficient use of the frame buffer by utilizing its output during a greater part of the time the computer is operating.

The use of the frame buffer 41 to store the information used for the overlay until it is placed in the memory 42 allows a full range of color information to be used for the overlay in contrast to the prior art. Moreover, by judicious selection of the number of bits per pixel to be used in the overlay, even a small overlay memory may be made to provide an overlay for a very large region of the display.

Although the present invention has been described in terms of a preferred embodiment, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow.

Claims (9)

1. In a computer system having a frame buffer, and output means for utilizing an image in a frame buffer, the improvement comprising: a circuit for overlaying information on a computer image comprising means for storing overlay information of no more than a single scan line in length, means for providing individual lines of overlay information to the means for storing overlay information, means for determining when a scan line of the computer image and an overlay coincide, and means for using the overlay information to modify the output image at positions where an overlay and an image coincide.

2. Circuitry for providing an overlay for a background picture presented on an output display comprising a frame buffer for storing information describing a single frame of a background picture, means for storing in the frame buffer information describing an overlay to be presented in conjunction with the background picture, means for determining during each scan to an output display when a region covered by the overlay is being traversed, a buffer for holding a single line of overlay information, means for providing from the frame buffer each line of overlay information to the buffer for holding a single line of overlay information during a period in which image information is not being transferred from the frame buffer, and means for selecting information from the background information in the frame buffer and the overlay information in the buffer for holding a single line of overlay information at each overlay position for presentation on an output display.

3. Circuitry for providing an overlay for a background picture presented on an output display ars claimed in Claim 2 in which the means for determining during each scan to an output display when the a region covered by the overlay is being traversed comprises means for storing the position at which the overlay is to begin.

4. Circuitry for providing an overlay for a background picture presented on an output display as claimed in Claim 3 in which the means for storing a position at which the overlay is to begin comprises a register for storing a horizontal beginning position, and a register for storing a vertical beginning position.

5. Circuitry for providing an overlay for a background picture presented on an output display as claimed in Claim 4 in which the means for determining during each scan to an output display when the a region covered by the overlay is being traversed comprises means for comparing the position at which the scan is occurring to the position at which the overlay is to begin.

6. Circuitry for providing an overlay for a background picture presented on an output display as claimed in Claim 2 in which the means for selecting information from the background information in the frame buffer and the overlay information in the buffer for holding a single line of overlay information at each overlay position for presentation on an output display comprises means responsive to mask data stored with the overlay information.

7 Circuitry for providing an overlay for a background picture presented on an output display as claimed in Claim 6 in which the means responsive to mask data stored with the overlay information comprises an AND gate enabled to respond to the mask signal during a period in which the overlay is to be presented on the display.

8. Circuitry for providing an overlay for a background picture presented on an output display as claimed in Claim 2 in which the buffer for holding a single line of overlay information is capable of storing for each pixel position of the overlay the same number of bits as is the frame buffer.

9. Circuitry for providing an overlay for a background picture presented on an output display as claimed in Claim 2 in which the buffer for holding a single line of overlay information is capable of storing for each pixel position of the overlay up to the same number of bits as is the frame buffer, and further comprising means for selecting the number of bits used for each overlay pixel in order to vary the number of pixels stored in the overlay memory.

lO. A circuit for overlaying information on a computer image substantially as hereinbefore described with reference to the accompanying drawings.