GB2252213A

GB2252213A - TTL input buffer

Info

Publication number: GB2252213A
Application number: GB9118650A
Authority: GB
Inventors: Myoung-Ho Bae; Gye-Ho Ahn
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1991-01-22
Filing date: 1991-08-30
Publication date: 1992-07-29
Also published as: KR920015363A; DE4128736A1; CN1063588A; GB9118650D0; JPH04259993A

Abstract

A Transistor-Transistor-logic (TTL) input buffer is capable of stably sensing TTL level of input signals in a high-scale integrated semiconductor device, as well as preventing the phenomena of inflow to a data sensing circuit 200 of grounding noise generated by a driving circuit 210. The TTL input buffer is provided with a ground pad 25, a first ground line 26 connected between the data sensing circuit 200 and the ground pad 25 so as to supply a ground potential to the data sensing circuit, and a second ground line 27 connected between the driving circuit 210 and the ground pad 25 so as to supply the ground potential to the driving circuit 210. Ground noise produced by the driving circuit is blocked from flowing into the data sensing circuit 200, by use of the at least two ground lines 26, 27 independently coupled to each other. In an alternative embodiment (Fig 5) the two ground lines 26, 27 are separately connected to a first and a second ground pad (31, 32) respectively. <IMAGE>

Description

Tm INPUT BUFEER The present invention relates to a transistor-transistor-logic (TTL) input buffer, particularly although not exclusively for a high-scale integrated semiconductor memory device.

A known TTL input buffer circuit generally includes a data sensing circuit for sensing a state of input 1TL data, and a driver circuit for driving an output from the data sensing circuit. One example of such a construction is disclosed in Figure 1 of the accompanying drawings, wherein reference symbols M1-M2, M6, M8 and M10 each designate P-channel MOS transistors while M3, M4, M5, M7, M9 and Mli each designate N-channel MOS transistors.

Referring to Figure 1, the sensing circuit 100 includes MOS transistors M1 to M5, and the driver circuit 110 includes MOS transistor M6 to Mull.

Further, MOS transistors M1 and M2 are connected in series in between a power source input 4 and a first output node 2, MOS transistors M3 and M4 are connected in series in between the first output node 2 and a ground pad 5, and gates of MOS transistors M1 to M4 are coupled together to an input pad 1. MOS transistors M6 to M11 constitute a conventional inverter circuit, in which an output logic signal is provided at a second output node 3 depending upon an intermediate voltage level received at the first output node 2. MOS transistor M5 has its drain-source channel connected between respective sides of the MOS transistors M1 and M3, and its gate connected to the first output node 2.

Referring further to the circuit of Figure 1, a voltage level at the first output node 2 is determined, dependent upon the resistance ratio of MOS transistors M1 to M4 on the basis of a power source voltage Vcc applied through a supply node 4. Assuming that a full Vcc level of voltage (about 6 volts) other than a TIZ level is applied to the input pad 1, P-channel MOS transistors M1 and M2 turn off, while N-channel MOS transistors M3 and M4 turn on, so that the voltage level of the first output node 2 goes to ground level. Thus, this turns on MOS transistor M6, while turning off MOS transistor M7, to thereby make a first connection node N1 high level.In sequence, this high level signal at the node N1 turns off MOS transistor M8, while turning on MOS transistor M9, to thereby make a second connection node N2 low level. Likewise, at the second output node 3 there is eventually provided a high logic level of signal. When just turning on MOS transistor M9 by the high level voltage at the node N1, a current path is introduced between the second connection node N2 and the ground pad 5. In this occasion, ground noise is generated by this signal transition from high to low.

Hence, since gate-source voltages (VGS) of MOS transistors M3 and M4 are increased by such ground noise, a voltage level at the first output node 2 is also increased. In fact, however, as MOS transistors M1 and M2 are in an off state, this first output node 2 is kept at low level in spite of the occurrence of those ground noises.

In the meanwhile, in the case where the voltage level applied in the input pad 1 is at a TTL high level (at least 2.4 Volts), a voltage level of the first output node 2 depends upon the resistance ratio of the MOS transistor pairs M1 and M2, and M3 and M4. In a conventional MOS transistor having three electrodes, that is, a drain, a source and a gate, a channel is introduced between the source and the drain when a voltage larger than a threshold voltage (Vt) is applied to the gate. Therefore, the channel may be regarded a resistance that can be controlled by the input voltage applied to the gates of the MOS transistors M1 to M4. Thus, the voltage level at the first output node 2 is determined in dependence upon the resistance.For example, if the input pad 1 receives a TTL high level of voltage, then MOS transistors M3 and M4 are turned on, which in sequence introduce a current path between the first output node 2 and the ground pad 5, and make the electric potential at the first output node 2 at a low logic level, that is, the ground level. Likewise, at the second output node 3 there is provided a high logic level of voltage, as MOS transistor M10 turns on while MOS transistor Mli turns off due to a low level of voltage at the second connection node N2.Here, when a level of the first connection node N1 is changed from low to high, since MOS transistor M9 begins to conduct, a current path between the second connection node N2 and the ground pad 5 is introduced so that the high level potential at the node N2 flows into the ground pad 5, as is seen by the dotted curve (2d) of Figure 2 of the accompanying diagrammatic drawings of, which shows various waveforms for describing the operation of the Figure 1 circuit. Then, as the ground noises produced in the ground pad 5 are applied into a source of MOS transistor M4, the gate-source voltage VGS of MOS transistor M4 is increased.Thus, this causes a threshold voltage VT of MOS transistor M4 to increase, which in turn causes the gate-source voltage VGS of MOS transistor M3 to increase and also causes a potential level at the first output node 2 to increase, as is seen by the dotted curve (2a) of Figure 2. That is, once a Tit high level potential is applied into the input pad, as is seen by the solid line (2c) of Figure 2, the ground noise such as the dotted curve (2d), generated in the driver circuit 110, may flow into the sensing circuit 100, which increases the potential level at the first output node 2, as is seen by the dotted curve (2a). At this time, if the potential level at the first output node exceeds a given trip point level (2b) of MOS transistors M6 and M7, the ground noises cause the output logic level (2e) to change unexpectedly.This undesirable effect of logic level alteration can be often generated upon transition of an input logic signal from TTL low level to Tit high level and much more so with higher Vcc voltage level. Accordingly, since prior art Tit input buffers have not yet been well prepared for such ground noises, they are hardly able to sense a logic state of TTL input signal upon occurrence of the ground noise, which inevitably leads to malfunction of the entire circuitry or a long sensing time.

Preferred embodiments of the present invention aim to provide a TTL input buffer capable of stably sensing the TTL level of input signals in a highscale integrated semiconductor device.

Another aim is to provide a TTL input buffer capable of preventing the occurrence of inflow of the grounding noise produced by a driver circuit in a semiconductor device.

According to a first aspect of the present invention, there is provided a transistor-transistor-logic (TTL) input buffer having a first output node, a second output node, an input pad for receiving a Tit level of input signal, a data sensing circuit connected between the input pad and the first output node for sensing the Tit input level, a driving circuit connected between the first and second output nodes for driving an output logic level of the data sensing circuit, and at least one power supply terminal for the data sensing circuit and the driving circuit, said input buffer further comprising: a ground pad means; a first ground line means connectable between the data sensing circuit and the ground pad means, for supplying a ground potential to the data sensing circuit; and a second ground line means connectable between the driving circuit and the ground pad means, for supplying the ground potential to the driving circuit.

Preferably, said ground pad means comprises a first ground pad coupled with said first ground line means and a second ground pad coupled with said second ground line means, respectively.

The invention extends also to a semiconductor memory device provided with a Tit input buffer according to any of the foregoing aspects of the invention.

By applying at least two ground lines independently connected to each other, ground noise produced by the driving circuit may be blocked from flowing into the data sensing circuit.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 3 to 5 of the accompanying diagrammatic drawings, in which: Figure 3 is a circuit diagram of one example of a preferred embodiment of a Tit input buffer according to the present invention; Figure 4 is a waveform diagram illustrating operation of the circuit of Figure 3; and Figure 5 is a circuit diagram of another example of an embodiment of a TTL input buffer according to the present invention.

In the figures, like reference numerals denote like or corresponding parts.

Referring to Figure 3, the Tit input buffer is provided with a first output node 22, a second output node 23, an input pad 21 receiving TTL level of input signals, a data sensing circuit 200 connected between the input pad and the first and second output nodes for sensing the Tit input level, a driving circuit 210 connected between the first and second output nodes for driving an output logic level of the data sensing circuit 200, and a power supply terminal 24 for supplying a given source voltage to the data sensing circuit and the driving circuit.Further, there are provided a ground pad 25, a first ground line 26 connected between the data sensing circuit 200 and the ground pad 25 so as to supply a ground potential to the data sensing circuit, and a second ground line 27 connected between the driving circuit 210 and the ground pad 25 so as to supply the ground potential to the driving circuit 210.

The sensing circuit 200 includes four MOS transistors M21, M22, M23 and M24 which are coupled in series, via the first output node 22, between the power supply terminal 24 and the first ground line 26, and of which the gates are connected in common to the input pad 21. MOS transistor M25 whose gate is coupled to the first output node 22, is also included in the sensing circuit 200, as is seen in the drawing of Figure 3. The driving circuit 210 includes MOS transistors M26 to M3 1 which constitute a three-stage inverter, and drive an intermediate logic level from the first output node 22 to the second output node 23. MOS transistors M21, M22, M26, M28 and M30 are P-channel type, while MOS transistors M23, M24, M25, M27, M29 and M3 1 are N-channel type.

Figure 4 shows examples of various voltage waveforms in operation of the circuitry of Figure 3, wherein 4a represents a waveform at the first output node 22, 4b a trip point level of MOS transistors M26 and M27, 4c a waveform of a Tit high level input signal in the input pad 21, 4d a waveform of the ground noise generated on the first ground line 26, and 4e an output waveform at the second output node 23.

The resistance ratio of the MOS transistors M21 to M24 in the sensing circuit 200 is dependent upon a TTL input level, by which resistance ratio a potential level at the first output node 22 is determined. The potential level at the first output node 22 is inverted through the driving circuit 210 to be delivered to the second output node 23. Here, a grounding path for the sensing circuit 200 is arranged independently from the driving circuit 210 and other peripherals. That is, a source of MOS transistor M24 is connected to the ground pad 25 via the first ground line 26, while all sources of MOS transistors M27, M29 and M3 1 are connected together with the ground pad via the second ground line 27.

Assuming that an input voltage level is at a full Vcc level other than a TTL level, MOS transistors M21 and M22 are turned off, while MOS transistors M23 and M24 are turned on, thereby keeping the potential level of the first output node 22 at ground level. At this time, the inflow to the data sensing circuit 200 of ground noises produced from the driving circuit 210 is blocked.

Taking a further detailed description of the circuitry of Figure 3, if a Tit input level applied to the input pad 21 is low, then MOS transistors M21 and M22 turn on and MOS transistors M23 and M24 turn off, thereby passing to the first node 22 a Vcc power level applied to the power supply terminal 24, as is seen by the waveform 4a of Figure 4. Then, because MOS transistor M26 is turned off and MOS transistor M27 is turned on, the first connection node N21 goes to a low potential level. This low level signal turns on MOS transistor M28 and turns off MOS transistor M29, thereby making the logic level of the second connection node N22 high. Thus, MOS transistor M30 sequentially is turned off, while MOS transistor M3 1 is turned on, so that a logic low level of signal such as the waveform 4e is provided at the second output node 23.

In the case where the Tit potential level applied to the input pad 21 is transferred to high level from low level (t w tl in Figure 4), even though the potential level applied to gates of the MOS transistors M21 to M24 is changed, there is no change to the logic state of the transistors M21 to M24 and consequently no change to the potential level of the first output node 22 whilst the Tit level is rising, as seen in the waveform 4a. However, when the Tit potential level applied to the input pad 21 increases above a TIZ high level at about the timing point tl, MOS transistors M21 and M22 begin to turn off while MOS transistors M23 and M24 begin to turn on. Therefore, since the first output node 22 is connected to the ground pad 25 via the second ground line 26 to form a current path, its potential level begins to decrease, as is shown in the waveform 4a. However, until the potential level decreases to the trip point level 4b of MOS transistors M26 and M27, MOS transistors M26 and M27 do not change their original logic states. Hence, the output level at the second output node 23 is still kept at low level, as is seen in the waveform 4e.

Once the potential level of the first output node 22 goes below the trip point level 4b, MOS transistor M26 begins to turn on and MOS transistor M27 begins to turn off. Hence, the potential of the first connection node N21 begins to increase, and approaches the trip point of MOS transistors M28 and M29. By this, MOS transistor M28 begins to turn off and MOS transistor M29 begins to turn on. Thus, the potential level of the second connection node N22 decreases, and approaches the trip point level of MOS transistors M30 and M3 1. By this, the potential level of the second output node 23 also begins to change, as is shown in the waveform 4e. Once MOS transistor M29 begins to turn on as the potential level of the first connection node N21 increases, the ground noise begins to be generated onto the second ground line 27.However, since MOS transistors M27, M29 and M3 1 are separately connected to the ground pad 25 via the second ground line 27, such ground noise on the ground line does not affect the potential of the first output node 22. Thus, the first output node and the second output node are effectively separated from each other. Hence, the ground noise generated in the driving circuit 210 is not applied to the data sensing circuit 200, by which an input Tit level signal will be able to be correctly and precisely sensed by the data sensing circuit 200 to produce therefrom a stable TTL level output signal at the final output node 23.

In the alternative embodiment of Figure 5, the ground pad 25 of Figure 3 is substituted by a first ground pad 31 connected with the first ground line 26 and a second ground pad 32 connected with the second ground line 27.

Otherwise, the circuitry and construction of the embodiment of Figure 5 is similar to that of Figure 3. Therefore, the circuit operation of Figure 5 will be understood easily, as aforementioned with reference to Figures 3 and 4.

As is apparent from the foregoing description, a TTL input buffer as illustrated may provide a plurality of (at least two) ground paths each coupled to either one of a data sensing circuit, a driving circuit and other possible peripheral circuits, independently of each other circuit. As a result, the buffer may block the inflow of ground noise to the grounding path of the data sensing circuit, thereby preventing any undesired alteration of Tit input and output level in a TTL input buffer for high-scale integrated semiconductor devices. Further, such a buffer may provide the advantage of driving TTL input data to its output stage, stably and without error.

While the foregoing. provides a full and complete disclosure of preferred embodiments of the present invention, various modifications, alternate constructions and equivalents thereof may be employed without departing from the true spirit and scope of the invention. Therefore, the above description and illustration should not be construed as limiting the scope of the invention.

Whilst the term "ground potential" usually refers to zero potential, it will be understood by those skilled in the art that, within the context of this specification, it may refer also to other reference potential levels.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, arid the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

CLAIMS:

1. A transistor-transistor-logic (Tit) input buffer having a first output node, a second output node, an input pad for receiving a TTL level of input signal, a data sensing circuit connected between the input pad and the first output node for sensing the TTL input level, a driving circuit connected between the first and second output nodes for driving an output logic level of the data sensing circuit, and at least one power supply terminal for the data sensing circuit and the driving circuit, said input buffer further comprising: a ground pad means; a first ground line means connectable between the data sensing circuit and the ground pad means, for supplying a ground potential to the data sensing circuit; and a second ground line means connectable between the driving circuit and the ground pad means, for supplying the ground potential to the driving circuit.

2. A transistor-transistor-logic (Tit) input buffer according to Claim 1, wherein said ground pad means comprises a first ground pad coupled with said first ground line means and a second ground pad coupled with said second ground line means, respectively.

3. A TTL input buffer substantially as hereinbefore described with reference to Figure 3, Figures 3 and 4, Figure 5 or Figures 4 and 5, of the accompanying drawings.

4. A semiconductor memory device provided with a TTL input buffer according to claim 1, 2 or 3.