GB2178618A - Input buffer circuit for static ram - Google Patents

Abstract

An input buffer circuit for a CMOS static random access memory incorporates means for preventing excessive current drain when the circuit is driven at an incorrect level, e.g. from TTL circuitry. Typically the input stage of the circuit (TR11, TR21) includes means (TR51) whereby the source/drain voltage of one transistor (TR11) is limited thus restricting the current flow through that transistor. <IMAGE>

Description

SPECIFICATION Input buffer circuit for static ram This invention relates to input circuits for static random access memories.

Currently employed input circuits for static random access memories fabricated in CMOS technology suffer from a number of disadvantages. The major problem is that of large current flow when any CMOS gate is driven to a level other than a CMOS level. This occurs, for example, when the gate acts as an input buffer driven from a TTL logic circuit. A further disadvantage of conventional input circuits is associated with random access memories that use address transition assistance logic.

When biassed at the input threshold voltage such circuits can be triggered by noise thus giving false signals to the address transition detection logic.

A typical conventional input circuit is shown in Fig. 1 of the accompanying drawings. If this circuit is driven by a TTL ONE level, typically 2 volts, to the input I/P then, under this condition, transistor TR2 is held on and transistor TR1 is held partially on. This results in a current flow through these two series connected transistors. This current flow results in a voltage condition at the junction of TR1 and TR2 that causes a similar current drain through the series connected pair of output transistors TR3 and TR4.

The object of the present invention is to minimise or to overcome these disadvantages.

According to the invention there is provided an input buffer circuit for a static random access memory, the circuit including an input stage comprising a series connected pair of complementary field effect transistors, an output stage, and means for controlling the source/drain voltage of at least one member of the input transistor pair so as to restrict the current drain of that pair.

An embodiment of the invention will now be described with reference to Figs. 2 to 4 of the accompanying drawing in which: Figure 2 is a schematic diagram of a low current input circuitry for a memory; Figure 3 shows a modification of the circuit of Fig. 2, and Figure 4 shows the general circuit from which the circuit of Fig. 2 is derived.

Referring to Fig. 2, the circuit, which is fabricated in CMOS technology, includes a complementary pair input stage (TR11, TR2 1) and a complementary pair output stage (TR3 1, TR41). Application of a logic ONE or ZERO (CMOS level) to the circuit input I/P switches the corresponding input transistor TR11 or TR21 to its conductive state thus producing, via the output stage TR31, TR41 a corresponding ONE or ZERO at the circuit output.

This output is of course at one or other of the two standard CMOS levels.

If the circuit input is driven to a ONE or ZERO TTL level then the circuit operates in the following manner: TTL ONE level In response to this input transistor TR21 is driven partially on and transistor TR11 partially off. Howeverm transistor TAS 1 in the source circuit of transistor TR11 restricts the current flow through TR11 by reducing the source voltage of this transistor to a level at which the source current is insignificant. Consequently the potential at node 10 is sufficiently low that transistor TR41 is turned off and transistor TR31 is turned on. The output at O/P is thus at Vcc, i.e. at the CMOS ONE level, and transistor TR61 is off. Substantially no current flows the output transistor pair.

TTL ZERO level Under this condition the circuit input is driven to approximately 0.8 volts. In response to this input transistor TR21 is turned off or nearly off and transistor TR11 is turned on pulling node 10 to the voltage level set by node 20. This voltage is of course not a standard CMOS level. Excessive current drain under this condition through transistors TR31 and TR41 is prevented by transistor TR61.

This transistor together with transistors TR31 and TR41 forms a positive feedback path to pull node 10 towards Vcc. In this mode transistor TR31 is turned off so that again substantially no current flows through the output transistor pair. The output O/P is pulled down via transistor TR41 to the CMOS ZERO level.

The switching characteristic of the circuit of Fig. 2 may show a hysteresis effect. With the input at a logic ONE, transistor TR21 is turned on and transistor TR61 is off. If the input voltage is allowed to fall towards the ZERO level, a voltage V1 is reached at which the output of transistors TR11 and TR21 is equal to the threshold voltage V3 of the inverter stage comprising transistors TR31 and TR41.

Similarly, with an initially ZERO input rising towards the ONE level an input voltage V2 is reached at which the threshold voltage V3 is applied to the inverter stage. The effect of transistor TR61 is to ensure that V2 is greater than V thus providing the hysteresis effect.

A modification of this circuit is shown in Fig. 3. This circuit is designed for very low power consumption and is provided with a control input I/P 2 to which the memory chip select (CS or CS) signal is coupled. This signal is conventionally employed in a static memory circuit to place the circuit into a low power mode or standby condition to reduce the circuit power requirement. This signal is applied to the gates of n-channel transistor TR13 and p-channel transistor TR14. With this signal at a CMOS ONE level transistor TR13 is off removing the current path previously through transistors TR11, TR21. TR14 is on clamping node 20 to a CMOS zero. The operation of this circuit is otherwise similar to that of Fig.

2.

A general circuit from which the circuit of Fig. 2 is derived is shown in Fig. 4. In this arrangement the source voltages of each of the input transistors TR11 and TR21 is controlled by a further series connected transistor TR5, TRSa the gates of which are coupled to respective reference voltages V1 and V2. As before this substantially reduces the current drain of the input stage under adverse input conditions.

The circuits of Figs. 2 to 4 are applicable to p-well, n-well, or twin-well bulk CMOS processess. They can also be applied to the silicon on insulator CMOS processes. Generally these circuits will be employed on 5 volt CMOS, the primary role being the interfacing of 5 volt TTL to 5 volt CMOS. It will however be appreciated that these circuits can be adapted to accept a wide range of supply voltages and input high and low levels.

Claims (7)

1. An input buffer circuit for a static random access memory, the circuit including an input stage comprising a series connected pair of complementary field effect transistors, an output stage, and means for controlling the source/drain voltage of at least one member of the input transistor pair so as to restrict the current drain of that pair.

2. An input buffer circuit as claimed in claim 1, wherein said voltage control means comprises a further transistor the gate of which is coupled to a reference voltage source.

3. An input buffer circuit as claimed in claim 1 or 2, wherein said output stage comprises a second series connected complementary pair of transistors.

4. An input buffer circuit as claimed in claim 1, 2 or 3, wherein said output stage includes feedback means whereby the current drain of said second transistor pair is restricted.

5. An input buffer circuit as claimed in any one of claims 1 to 4, wherein said input stage has means for disabling the circuit in response to the memory chip select input signal.

6. An input buffer circuit from a static random access memory substantially as described herein with reference to Fig. 2, 3 or 4 of the accompanying drawings.

7. A static random access memory provided with one or more input buffer circuits as claimed in any one of claims 1 to 6.