GB2248362A - Multi-path digital video architecture - Google Patents

Abstract

Digital video data processing apparatus comprises five frame stores 13 to 17, ten video input/output slots 22 to 31, an arrangement of three multi-path data stream switches 37, 38 and 39 (which may be crossbar switches) each having sixteen input/output ports a controlling host processor 11, digital mixing units 33 and 34, and a run length encoded data expand or 35 consisting of a ramp signal generator 40 and two interpolator units 41 and 42. Four of the frames stores, 13 to 16, can be used to store live video or run length encoded luma and chroma data, or run length encoded matte data and run lengths. Run length encoded data can be expanded by the expander 35. Live video signals or live video and graphics can be mixed in the mixing units 33 and 34. The host processor 11 provides calculated run lengths and encoded data and controls the accessing of the frame stores 13 to 17 and the interconnections established for each field duration between the switches 37. 38 and 39. <IMAGE>

Description

MULTI-PATH DIGITAL VIDEO ARCHITECTURE This invention relates to a digital video effects apparatus which generates a multitude of special effects by using redefineable video paths between field-stores, mixers, video input, output and processing boards.

Devices are known for special effects and compositing which use fixed video data paths between the various video processing boards.

The present invention relates to the compositing and special effects of digital video data. These are achieved by apparatus able to transfer real-time digital video data simultaneously between field-stores, mixers, video input, output and processing boards during the current field time, while data from a host processor is loaded into other field-stores to be used in the next field. The digital video data paths between the different boards and processing elements may then be redefined via a set of crossbar switches to use the updated data during the next field of video.

In accordance with a preferred embodiment of the present invention there is disclosed a digital video production and post-production device comprising a crossbar switch matrix adapted to interconnect a plurality of dual-port field-stores with a plurality of video input/output processing slots, said processing slots being adapted to input new data into said device and/or augment data provided from said field-stores, an address buffer and a clock generator each controlled by a host processor or processors and adapted to provide control signals for the transfer of digital video data into, through and out of said field-stores, a run length expander connected to said matrix for expanding run length encoded matte and video data into full bandwidth matte and digital component luma and chroma signals.

and a video dissolver connected to the said matrix for mixing a number of digital video signals together under the control of one or more matte signals.

The principal components that make up this preferred device are: a) Crossbar Switch Matrix The crossbar matrix is made up of sixteen way non-blocking crossbar switches which connect the real-time digital video data streams from the ten field-stores to inputs, outputs and video processing elements. There are twenty-eight "externals connections to the crossbar switch matrix and simultaneous real-time video data transfer is possible between pairs of these connections. The crossbars may be redefined after every field of video by the host processor.

b) Video field-stores The ten dual port field-stores are all accessible simultaneously by streams of real-time data from the video port.

A host processor is able to write to the field-stores through the host port. All ten are identical except for two that have different access patterns from the crossbar switch matrix. These field-stores may contain component digital chroma and luma data, matte data as well as run length encoded data.

Video accesses through the video port of the ten field-stores may be offset from each other so that delay through processing elements may be taken into account. For every line of video, every field-store is supplied with its own set of starting row and column addresses from which to access a segment of video data. This enables segments of video along a line to come from or be written to different addresses in the field-store. The row and column addresses may also be interchanged so that a field of video may be rotated through ninety degrees.

c) Address buffer A set of video segment start addresses are worked out by the host processor for every line of video for the ten field-stores. These addresses for several fields of video are stored in the address buffer and loaded into FIFO's during the horizontal blanking period. The FIFO's store each field-store's set of video segment addresses for a line of video so that video port accesses to the field-stores may be asynchronous during each line of video.

d) Clock generator This is programmed by the host processor to generate the appropriate access strobes for each of the field-stores for achieving a particular effect. The addresses for these accesses are clocked in from the address FIFO's.

e) Video dissolver The dissolver mixes up to three digital video signals together controlled by two digital matte signals. These signals are routed to the inputs of the dissolver from the crossbar switch matrix, and can therefore come from any source.

f) Run length expander (RLE) The RLE expander expands RLE matte and video data into full bandwidth matte, and digital component luma and chroma signals.

g) Video Input/Output/Processing Slots The digital video inputZoutput/processing slots are connected to the crossbar switch matrix. As there are a total of ten connections to the crossbar, no more than ten video paths can be operational simultaneously. An input and output module cannot operate simultaneously if the input is driving the same channel as the output is receiving from. Thus there are certain restrictions to the placement of these modules; while all individual slots are equivalent, not all module orderings in those slots are equivalent. Any contention will usually be solved by reversing the order of the modules.

The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a block schematic diagram of an apparatus embodying the invention; Figure 2 is a diagram, on a larger scale, of part of the apparatus of Figure 1; Figure 3 is a schematic circuit diagram of a crossbar switch circuit used in the apparatus of Figure 1; Figure 4 is a diagram, on a larger scale, of a further part of the apparatus of Figure 1; Figure 5 is a schematic circuit diagram of memory circuitry used in the apparatus of Figure 1; Figures 6 and 7 are diagrams on a larger scale of further parts of the apparatus of Figure 1; Figures 8 and 9 are graphical illustrates of operations effected in a run length expander portion of the apparatus of Figure 1; and Figures 10 to 15 are illustrations of a number of operations carried out by the apparatus of Figure 1.

Figure 1 illustrates in block form an apparatus embodying the invention In the apparatus of Figure 1, a host processor 11 supplies control signals and, when required, run length encoded video data through a system bus 12. Five frame stores 13, 14, 15, 16 and 17 are coupled to the system bus by an address generator 18, a data interface 19, and a clock generator 20.

Each frame store consists of two field stores. A timing generator 21 is connected to the system bus 12, the address generator 18, and ten input/output unit slots 22 to 31. The timing generator 21 operates to ensure synchronization between the sync signals of input and output video data, the addressing of the frame stores 13 to 17, and the host control signals. One or more of the input/output unit slots 22 to 31 is equipped with an analog to digital converter, or a digital to analog converter, for conversion betweem 8 bit digital video signals processed by the apparatus, and analog video supplied to and or output by the apparatus.

In operation, one of the frame stores, namely the frame store 17, is loaded with menu data for viewing, on command, at a workstation 32 connected to the system bus 12.

The apparatus also includes two mixing units 33 and 34 connected in cascade, a run length encocded data expander 35, and a controlled switching arrangement 36 having three sixteen port switches 37, 38, and 39.

The cascaded mixing units 33 and 34 can be used to mix two or three video signals under the control of one or two matte signals.

The run length encoded data expander 35 includes a run length ramp signal generator 40 and two interpolator units, one such unit 41 being used to produce matte signals, and the other interpolator unit 42 being used to produce video signals.

The apparatus can be arranged to process, or to generate 8 bit video in 4:2:2 format PAL, i.e. two bytes per pixel at a pixel rate of 13.5 mega pixels per second, giving 27 mega bytes per second. For PAL video, there are 25 frames per second, 625 lines per frame, 15,625 lines per second, and 864 pixels per line. The two bytes per pixel are a luma byte followed by a chroma byte, with the chroma byte alternating between chroma B and chroma R from one pixel to the next. Of the 864 pixels per line, only 720 are picture data, and are referred to as active pixels. Also, of the 625 lines per frame, only 575 are picture data, and are referred to as active lines.

The 720 active pixels require 1440 bytes of data, and one field requires 1440 x 575 bytes of data 2 = 414,000 bytes.

The digital video channels between the digital video processing components of the apparatus of Figure 10 are 8 bit wide channels, so that the byte rate is 27 megahertz. The switches 37, 38 and 39 provide selected 8 bit wide connection channels between their respective ports.

Figure 2 shows, on a larger scale, the ten input/output unit slots 22 to 31 and their connections to the switch 39. Each slot is connected to two 8 bit channels, and each of these channels is arranged to serve as an input channel to one of the slots, and as an output channel from one of the slots, so that each channel is shared by two slots, but serves as an input to one and as an output from the other slot, so that there are only ten channels 51 to 60 connecting the slots 22 to 31 to the switch 39. This arrangement is organised as two groups of five slots as shown in Figure 2, the output channel 51 from slot 26 serving as the input channel 51 to slot 22, and the output channel 60 from slot 27 serving as the input channel 60 to slot 31.Where any slot is to serve as a source of digital video signals in the apparatus, an analog to digital converter that converts analog PAL into 4:2:2 digital video at 27 Megahertz is installed in that slot. Similarly, where any slot is to serve as an output of processed analog video signals from the apparatus, a digital to analog converter that converts 4:2:2 digital video at 27 Megahertz into analog PAL is installed in that slot. Connection between the converter and either the input or output channel at the slot is made as appropriate.

The switch 39 provides connections between those of the channels 51 to 60 which are in use, and selected ones of six further channels 61 to 66 at its six remaining ports.

Each of the switches 37, 38 and 39 is formed by two high speed digital crossbar switches of the type 74 AS 8840 manufactured by Texas Instruments, Incorporated, Dallas, Texas, United States of America. The 74 AS 8840 switch can switch from 1 to 16 nibbles, i.e. 4 to 64 bits, in one operation, havng 64 input/output pins arranged in 16 switchable nibbles. A single input nibble can be switched through to any one or more of the other 15 nibble outputs. A schematic diagram of the 74 AS 8840 switch is shown in Figure 3. Further details are given in the product leaflet entitled. "74 AS 8840 Innovation The new digital crossbar switch from Texas Instruments" published in 1988 by Texas Instruments, Incorporated. The two 74 AS 8840 switches are arranged to operate in parallel to provide the required 8 bit ports and internal channels of the switch 37 or 38 or 39.

Figure 4 shows the frame stores 13 to 17 in more detail.

Each frame store has a video RAM section (13a to 17a) and a multiplexer section (13b to 17b). The video RAM section of each frame store has a byte-wide parallel data input/output port which is connected to the data interface 19 through which the host processor can write to and read from any byte location in the video RAM section selected by the address generator 18, which operates under the control of the host processor 11. The video RAM section of each frame store also has two eight bit wide serial output ports each of which is connected to the respective multiplexer section (13b or 14b or 15b or 16b or 17b) which is connected through two eight bit wide channels to the switch 37.

The video RAM section and the multiplexer section, under the control of the clock generator 20, enable the frame store to be operated as two independent field stores whose respective inputs and outputs from and to the switch 37 are effected through the two eight bit wide channels. For example, the framestore 13 is operated as two field stores, one communicating with the switch 37 through an eight bit wide channel 71, and the other communicating with the switch 37 through an eight bit wide channel 72. Similarly, the frame stores 14 to 17 are operated as pairs of field stores with respective input/output channels 73 to 80. The field store input/output channels 79 and 80 of the frame store 17 are connected to respective ports of the switch 38, as shown in Figure 1.The frame store 17 is used to store menus loaded into the store 17 by the host processor 11, and viewable on the screen of the work station 32 when accessed at the store 17 from the work station 32.

The switch 37 can connect any one of the channels 71 to 78 with any one of the eight channels 81 to 85 and 61 to 63 at its other ports. Control codes for the interconnection or interconnections selected for the switch 37 are held in a latch 89 when loaded by the host processor 11. Further control signals are applied directly to the switch 37 from the system bus 12.

Figure 5 illustrates the arrangement of individual video RAM circuits forming the video RAM section such as section 13a, of one frame store. As shown, there are eight video RAM circuits 91 to 98. Each of the eight circuits 91 to 98 has nine address input pins connected to respective lines of a nine bit address bus 90 from the address generator 18. Only the connections for serial input and output from the circuits are shown in Figure 5.

Each circuit has a four bit serial input/output port. The serial ports of the circuits 91 and 92 are connected in parallel to a first four bit bus 101, the serial ports of the circuits 93 and 94 are connected in parallel to a second four bit bus 102, the serial ports of the circuits 95 and 96 are connected in parallel to a third four bit bus 103, and the serial ports of the circuits 97 and 98 are connected in parallel to a fourth four bit bus 104.

Each circuit has a row address strobe (RAS) signal input pin, and the address generator 18 provides four row address strobe signals RASP, RAS1, RAS2, and RAS3 which are applied as indicated to pairs of the circuits 91 to 98. Each of the circuits 91 to 98 has a RAM area of 262144 words, with each word being 4 bits, arranged as 512 rows of 512 words. Each of the circuits also has a 512 word serial access memory (SAM) into which and from which a complete row of words can be transferred from or to the RAM area.

The serial input/output port of the SAM serves as the serial input/output port of the circuit. To provide a complete byte of luma, or chroma, or other data, at any given location in the frame store, the circuits 91 to 98 are operated in pairs, these pairs being 91 and 93, 92 and 94, 95 and 97, and 96 and 98, and the respective four bit buses of the two circuits forming such a pair are combined to provide an eight bit channel to the respective multiplexer section of the frame store. Furthermore, since some of the pairs of circuits are always operated at different times, so far as their serial ports are concerned, two groups of two pairs are arranged to employ two common eight bit channels 105 and 106 as shown in Figure 5, The circuits 91 to 94 may be regarded as forming bank 0 of video RAM circuits, and the circuits 95 to 98 as forming bank 1 of video RAM circuits.

Each of the circuits 91 to 98 may be a Hitachi HM 534252 series l-M bit multiport video RAM.

Each line of active pixels constitutes 720 pixels and therefore 1440 bytes. Three passes are therefore used from the two banks of circuits, using 1440.3 = 480 words from each 512 word row from each circuit. The rows are accessed at times determined by the occurrences of the row address strobes RASO to 3, and at addresses determined by the prevailing addresses on the address bus 90. The row address strobes RASO to 3 are active in sequence, so that 960 bytes of each line of pixel data occurs on one of the channels 105 and 106, and the other 480 bytes occurs on the other of the channels 105 and 106.

The multiplexer section of the frame store, under the control of appropriate timing signals from the clock generator, switches the paths of the bytes so that those of one field all occur on one 8 bit channel between the frame store and the switch 37 or 38, and those of the other field all occur on the other 8 bit channel between the frame store and the switch 37 or 38. The multiplexer section is, of course, used in both reading data out of the frame store and writing data into the frame store through its serial ports.

The frame stores 13 to 16 can be used to store luma and chroma data, matte data, and run lengths and run length encoded luma, chroma, and matte data. The clock generator 20 operates to clock run length encoded luma, chroma, and matte data out of the SAM portions of the frame stores at the end of each run.

Serial address start positions are established by the address generator 18, so that a line of pixel data can be read or written with any horizontal offset. Thus delays in processing circuitry in the apparatus for line reads and writes can be compensated for by advancing or delaying the line in relation to events at different parts of the apparatus.

The data interface 19 acts as a buffer between the host processor 11 and the frame stores 13 to 17 so that the host processor 11 can load several bytes simultaneously into the interface 19 which will then supply that data one byte at a time to the selected frame store or stores.

Figure 6 shows the mixing units 33 and 34. Each mixing unit includes a latch 107 or 108 for holding control data supplied by the host processor 11 over the system bus 12, and a multiply/sum circuit 109 or 110. Each multiply/sum circuit has four 8 bit inputs A, B, C, D, and an 8 bit output S. Eight bit luma and chroma in 4:2:2 video format can be supplied as either or both inputs A and C. An 8 bit matte signal may be supplied as inputs B and D. Video data supplied as A or C passes through unchanged, to appear as output S: if there is no matte signal as B and D.

Each multiply/sum circuit is, in this example, a TMC 2249 CMOS digital mixer manufactured by TRW LSI Products Inc. of P.O.Box 2472, La Jolla, California 92038, United States of America. The TMC 2249 can operate at 30 Megahertz. Luma and chroma values are processed on alternate clocks. If chroma is stored in 2's complement form in the frame stores, it can be directly multiplied in a TMC 2249 if each chroma byte is correctly positioned in the 12 bit input field of the TMC 2249.

The matte signal is offset out of the sign region to ensure a signed by unsigned multiply operation.

Each multiply/sum circuit 109 or 110 internally converts the matte value (M) at input D into (l-M), so that the two multiplications carried out are AxM and Cx(l-M). The results of the two multiplications are summed to provide the output S.

Figure 7 shows the run length encoded data expander 35 and its connections to other components of the apparatus. The run length ramp signal generator 40 includes a ROM 111 containing a look-up table, a downcounter 112, and a latch 113. In operation, a run length is loaded into both the counter 112 and the latch 113, and the counter 112 is counted down from the run length to zero. The count in the counter 112 and the runlength in the latch 113 are applied as addresses to the ROM 111 which, in accordance with its look-up table, supplies as an output on an 8 bit channel 114 a value which is the result of the calculation 256 x Count Run length Figure 8 illustrates the output on channel 114 resulting from a series of runlengths.It will be seen that the ROM output ramps over the same range of values for every runlength, but that the time taken for the range to be covered is proportional to the run length. This output is supplied on channel 114 to both of the interpolator units 41 and 42 (Figure 7).

Each interpolator unit, 41 or 42, is supplied with a source value and a destination value. The source value is multiplied in the unit 41 or 42 by (1-r) where r is the current value of the ROM output, and the destination value is multiplied by r. The two product values that result are summed to provide an interpolation output value, which the unit 41 supplies on an 8 bit channel 86 to the switch 38, and the unit 42 supplies on an 8 bit channel 87 to the switch 38.

In the present example, each interpolator unit 41 or 42 is a TMC 2249 CMOS digital mixer circuit, as used for each multiply/sum circuit 109 or 110. However, the run length encoded values which are to be interpolated are supplied as inputs A and C to the units 41 and 42. In accordance with control signals supplied from the system bus 12 to a respective latch, each run length encoded value serves first as a destination value, then as a source value. The ROM output is supplied as inputs B and D to both units 41 and 42. It is arranged that the interpolator unit 41 processes only run length encoded matte values, and the interpolator unit 42 processes only run length encoded video (luma-chroma) values.

Figure 9 illustrates the output from the interpolator unit 41 for a series of run lengths corresponding to those shown in Figure 8. Successive destination values are indicated at 115, 116, 117, 118, and 119 respectively.

The output of the ROM 111 is an 8 bit number which rises as a ramp from the beginning of a run length to its end. The last value, when the count in counter 112 is zero, should be 256, which cannot be represented as an 8 bit number. However, since a new run length is loaded when the counter 112 reaches zero, the ROM output never becomes 256. Also, at this point, the source value at the interpolator unit 41 or 42 is replaced by the previous destination value, so that interpolation is continuous in time. A sudden change in value can be achieved by having a run length of 1.

Run length encoded matte data is stored in the same frame store as the run lengths. By comparison with the organisation for storage of video data, matte data is stored in the luma portion of the store, and run lengths are stored in the chroma portion of the store. Two frame stores are required for the storing of compressed colour information: one for the run length encoded luma and chroma, and the other for the run length encoded matte and the run lengths.

Figure 10 illustrates, in simplified form, the apparatus of Figure 1 during an even field time when the apparatus is mixing two video signal inputs under the control of host generated matte signals. The frame stores 13 to 17 are shown divided into two field stores, for explanatory purposes. Frame store 13 is divided into field stores 1 and 2, frame store 14 is divided into field stores 3 and 4, and on as shown. The two input video signals, input video 1 and input video 2, are received at input/output slots 22 and 23, indicated at I/O 1 and I/O 2 in Figure 10. These slots are equipped with analog to digital converters in this example, as explained hereinbefore.

During the even field time, the even field of input video 1 is written into field store 2, and the even field of input video 2 is written into field store 4. Field store 1 already holds the previous input video 1 odd field, which during this time is read out through channels 71, 84 and 122, via switches 37 and 38, to one input of mixing unit 33. Similarly, field store 3 holds the previous input video 2 odd field, which is now read out through channels 73, 85, and 121, via switches 37 and 38, to another input of mixing unit 33. Field store 5 holds odd field run length encoded matte data, together with the accompanying run lengths. This data is read out through channels 75 and 82 to the run length ramp signal generator 40 and the matte interpolator unit 41.Control signals supplied by the host processor 11 ensure that only the run lengths are loaded into the ramp signal generator 40, and only the matte data is loaded into the interpolator unit 41. The expanded matte signal resulting is supplied through channel 86, switch 38, and a channel 120 to the inputs B and D of the mixing unit 33. The mixed video signal output from the unit 33 passes without further change through the cascaded mixing unit 34 to the channel 81, and thence through switch 37 and channel 77 to field store 7, which thus stores the mixed odd field. Field store 8 holds the previous created mixed even field which is now read out through channel 78, switch 37, channel 63, switch 39, and channel 59 to I/09 (input/output slot 30) which comprises a digital to analog converter in this example, as explained hereinbefore.The host processor 11 calculates and writes into field store 6 the next even field run length encoded matte data and its accompanying run lengths.

Figure 11 illustrates similarly the apparatus of Figure 1 during an odd field time when the apparatus is mixing the two input video signals 1 and 2 from I/O1 and I/02. The input video 1 and input video 2 odd fields are written respectively into field stores 1 and 3. The stored input video 1 and input video 2 even fields in field stores 2 and 4 are read out to the mixing unit 33, and the even field run length encoded matte data and its run lengths are read out to the matte interpolator 41 and the ramp signal generator 40 to produce the matte signal for the mixing unit 33. The mixed video output is supplied through channel 81, the mixing unit 34 again making no change, and thence, via switch 37 and channel 78, to field store 8. The host processor 11 generates the next odd field run length encoded matte data and run lengths and writes them into field store 5.

The mixed video odd field stored in field store 7 is read out through channel 77, switch 37, channel 63, switch 39, and channel 59 to I/09.

Figure 12 illustrates an even field time during use of the apparatus of Figure 1 to create a two dimensional graphics video signal output from run length encoded data. Only I/09 is required to be active and is in this example equipped with a digital to analog converter to provide the final output video signal. The host processor 11 calculates the run length encoded luma and chroma data, and the accompanying run lengths. During an even field time, stored odd field run length encoded luma and chroma data is read out of field store 3 through channel 73, switch 37, and channel 83 to the luma-chroma interpolator 42.

The necessary odd field run lengths, stored in field store 5, are read out through channel 75, switch 37, and channel 82 to the ramp signal generator 40, which applies the resulting ramp signals to the luma-chroma interpolator 42. The expanded odd field video output from the interpolator 42 is supplied through channel 87, switch 38, a channel 124, the mixing unit 34, channel 81, switch 37, and channel 77 to field store 7. The mixing unit 34 leaves the expanded video signal unchanged. The previously generated even field expanded video output, stored in field store 8, is read out through channel 78, switch 37, channel 63, switch 39, and channel 59 to I/09. The host processor 11 calculates and writes into field store 6 the run lengths for the next even field1 and calculates and writes into field store 4 the next even field run length encoded luma and chroma data.

Figure 13 illustrates an odd field time during use of the apparatus to create a two dimensional graphics video output from run length encoded data. Stored even field run length encoded luma and chroma data is read out of field store 4 through channel 74, switch 37, and channel 83 to the luma-chroma interpolator 42.

The necessary even field run lengths, stored in field store 6, are read out through channel 76, switch 37, and channel 82 to the ramp signal generator 40. The interpolator 42 accordingly generates the even field expanded video output which is supplied through channel 87, switch 38, channel 124, mixing unit 34 (without change)1 channel 81, switch 37, and channel 78 to field store 78 for storage. The previously generated odd field expanded video output held in field store 7 is read out through channel 77, switch 37, channel 63, switch 39, and channel 59 to I/O9. The host processor generates and writes to field stores 3 and 5 respectively the next odd field run length encoded luma and chroma data, and the accompanying odd field run lengths.

Figure 14 illustrates an even field time during use of the apparatus of Figure 1 to apply run length encoded two dimensional graphics to a live video signal. A live video signal is supplied to I/01, which in this example is equipped with a suitable analog to digital converter. The apparatus supplies a digital mixed video, comprising the live video with applied graphics, to I/09, which in this example is equipped with a suitable digital to analog converter. During an even field time, an input live video even field is supplied from I/01 through channel 52, switch 39, channel 62, switch 37, and channel 72 to field store 2 for storage. The previously stored live input odd field, held in field store 1, is read out through channel 71, switch 37, channel 84, switch 38, and channel 122 to one input of the mixing unit 33.Run length encoded odd field luma and chroma data held in field store 3 is read out through channel 73, switch 37, and channel 83 to the luma-chroma interpolator 42. The accompanying graphics odd field run lengths are read out from field store 5 to the ramp signal generator 40 through switch 37. Field store 5 also holds the accompanying oddfield run length encoded matte data, which is read out through the same path to the matte interpolator 41. The matte interpolator 41 supplies the expanded matte signal to the mixing unit 33 through channel 86, switch 38, and channel 120, and the luma-chroma interpolator 42 supplies the expanded luma-chroma signal to the mixing unit 33 through channel 87, switch 38, and channel 121.The mixed video odd field output from the unit 33 passes unchanged through the cascaded mixing unit 34, the channel 81, switch 37, and channel 77 to field store 7 for storage. The host processor 11 calculates and writes into field stores 4 and 6 respectively the next even field run length encoded luma and chroma data, and the accompanying even field run length encoded matte data and the run lengths. The previously generated even field expanded mixed video data stored in field store 8 is read out through channel 78, switch 37, channel 63, switch 39, and channel 59 to I/09.

Figure 15 illustrates an odd field time during use of the apparatus to apply run length encoded two dimensional graphics to a live video signal from I/01. During an odd field time, the input live video odd field is supplied from I/01 through channel 52, switch 39, channel 62, switch 37, and channel 71 to field store 1 for storage. The previously stored live input even field, held in field store 2, is read out through channel 72, switch 37, channel 84, switch 38, and channel 122 to one input of the mixing unit 33. Run length encoded even field luma and chroma data held in field store 4 is read out through channel 74, switch 37, and channel 83 to the luma-chroma interpolator 42.

The accompanying graphics even field run lengths are read out from field store 6 through switch 37 to the ramp signal generator 40. Field store 6 also holds the accompanying even field run length encoded matte data, which is read out through the same path to the matte interpolator 41. The matte interpolator 41 supplies the expanded matte signal to the mixing unit 33 through channel 86, switch 38, and channel 120. The luma-chroma interpolator 42 supplies the expanded luma-chroma signal to the mixing unit 33 through channel 87, switch 38, and channel 121.

The mixed video even field output from the unit 33 passes unchanged through the cascaded mixing unit 34, channel 81, switch 37, and channel 78 to field store 8 for storage. The host processor 11 calculates and writes in field stores 3 and 5 respectively, the next odd field run length encoded luma and chroma data, and the accompanying odd field run length encoded matte data and the run lengths. The previously generated odd field expanded mixed video data stored in field store 7 is read out through channel 77, switch 37, channel 63, switch 39, and channel 59 to I/09.

It will be apparent that the apparatus of Figure 1 can be arranged to carry out other processing operations, some making full use of both mixing units, and further use of the input/output slots 22 to 31.

One of the slots, for example slot 31 (I/O 10) may be provided with a digital to analog converter connected through an analog video channel (not shown) to the work station 32 so that the contents of the framestore 17 can be read out through channels 79 and 80, switch 38, and channel 60 to I/O 10.

Claims (13)

CLAIMS:

1. Video data processing apparatus comprising control signal source means1 a plurality of video data input and output means, a plurality of means for storing video data, and switchable multi-path data stream routing means arranged to selectively provide interconnection routes between selected ones of the input and output means, selected ones of the storing means, controllable ratio video data mixing means, and means for decoding encoded video data, the control signal source means being coupled to the storing means, the routing means, the mixing means and the decoding means to control operation of the storing means, the routing means, the mixing means, and the decoding means

2. Apparatus according to claim 1, wherein the control signal means includes means for supplying video data to a selected one or more of the storing means.

3. Apparatus according to claim 2, wherein the control signal means includes processing means to supply encoded video data to the selected one or more storing means, each of the said storing means being capable of storing encoded video data.

4 Apparatus according to any preceding claim, wherein each of the said storing means is capable of storing video control data, and the control signal source means is coupled to the storing means to supply video control data to a selected one or more of the storing means.

5. Apparatus according to claim 4, wherein the control signal source means includes processing means to supply encoded video control data to the selected one or more storing means,-and the said decoding means includes means for decoding the encoded video control data.

6. Apparatus according to any preceding claim, wherein the mixing means includes means for mixing more than two stream of video data.

7. Apparatus according to any preceding claim, wherein the routing means comprises a plurality of crossbar switches.

8. Apparatus according to claim 7, wherein each crossbar switch has sixteen ports.

9. Apparatus according to claim 7 or 8, wherein each crossbar switch comprises a plurality of integrated circuit multi-path switches arranged to operate in parallel with each other.

10. Apparatus according to any one of claims 7 to 9, wherein there are three crossbar switches, one of which is arranged to selectively provide data stream paths to or from the input and output means and the other two of which are arranged to selectively provide data stream paths to and from the decoding means.

11. Apparatus according to any preceding claim, wherein the decoding means comprises means for expanding run length encoded data.

12. Apparatus according to claim 11, wherein the expanding means includes linear interpolation means arranged to interpolate linearly between adjacent run length encoding values.

13. Video data processing apparatus substantially as described hereinbefore with reference to Figure 1 of the accompanying drawings.