GB2247798A

GB2247798A - Optical receiver

Info

Publication number: GB2247798A
Application number: GB9019478A
Authority: GB
Inventors: Gath Goodchild; Pasqualino Michele Visocchi
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1990-09-06
Filing date: 1990-09-06
Publication date: 1992-03-11
Anticipated expiration: 2010-09-06
Also published as: GB9019478D0; GB2247798B

Abstract

An optical receiver with extended dynamic range includes an optical detector (3), a transimpedance amplifier (1, 2) and a variable impedance network (D, Tr1). The d.c. component of the detector output is employed to control the variable impedance such as to prevent overload of the detector and the transimpedance amplifier front end (1). The a.c. and d.c. components of the feedback signal are separated by a capacitor (C2) so that only the a.c. component is coupled to the front end. The voltage drop across resistor r due to the d.c. component of the detector output serves to switch on transistor Tr1 at high input light levels, a.c. components being removed by a filter network (R3, C3), and permit diode D to conduct excess current away from the detector and the front end. The FET first stage of the transimpedance amplifier is replaced by a bipolar device for bit rates in excess of 30 MBits/s. <IMAGE>

Description

OPTICAL RECEIVER This invention relates to optical receivers, such as for use with optical telecommunications systems, and in particular to extended dynamic range optical receivers.

Optical receivers are often designed to have very high sensitivity, enabling large section (fibre) lengths, often at the expense of poor dynamic range, thus reducing the flexibility of the system when used with short fibre spans.

Many techniques to extend the dynamic range of optical receivers have been reported. Often they are used with complex peak detection or AGCs to limit the current resulting from the incident optical power. A receiver using an AGC technique is described in US 4415803. This receiver comprises an optical detector serially connected to a transimpedance amplifier. The detector receives a variable power level and modulation bandwidth optical signal and generates from it a corresponding electrical current. The transimpedance amplifier produces a fixed amount of gain and converts the electrical current to an output voltage. An AGC circuit produces a control signal which varies in response to the amplitude of the output voltage. This control signal is applied to a variable impedance device, connected to the detector output to vary its impedance.

This mai-.tains the output volts at a amplitude over the modulation bandwidth without any reduction in receiver sensitivity. WO 8804867A also discloses an arrangement which generates a control current to control a variable impedance.

At low bit rates in particular, with a high value of feedback resistance (for low noise contribution) and an FET input stage, many non-linear circuits which use the input limiting referred to above to enhance dynamic range give a severe sensitivity penalty.

According to the present invention there is provided an optical receiver including an optical detector, a transimpedance amplifier whose input is connected to the detector output and a variable impedance connected to the detector output, and wherein the d.c.

component of the detector output is employed to control the variable impedance such as to prevent overload of the detector and the transimpedance amplifier front end.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which Fig l illustrates an optical receiver for a low bit rate system, and Fig 2 illustrates an optical receiver for a high bit rate system.

For low bit rate systems (lower than 30Mbit/s) where an FET is preferred at the first stage of an optical receiver, a wide dynamic range may be afforded with a low sensitivity penalty (only about 0.7dB), with the circuit shown in Fig 1. The FET 1 is in a self-bias conrigur clon with a source resister R5 and the gate of FET 1 is grounded via feedback resistor Rf and resistor r. The receiver's amplifier is a transimpedance amplifier with the FET 1 providing the first stage and amplifier 2 providing the second stage. Amplifier 2 is configured to have a low input impedance in order to minimise Miller multiplication of the FET input capacitance. The feedback resistor Rf is that for the overall transimpedance amplifier. The gain of the first stage of the amplifier, i.e.FET 1, is derived by the drain resistor Rd and the transconductance of the FET 1 (i.e. Gain = Rd. gm) The output of the first stage (FET 1) is a.c. coupled to the second stage (amplifier 2) by capacitance C1. The output of the second stage is a.c. coupled by capacitor 2 to feedback resistor Rf, allowing transimpedance operation. The p-i-n photodiode 3 is reverse biased and directly coupled to the gate of FET 1.

For high bit rate systems (greater than 30 Mbit/s) a bipolar transistor 4 is preferred at the first stage. The circuit configuration is similar to Fig 1 and is shown in Fig 2. The transistor 4 is biased with an emitter resistor Re while the base current is supplied from a voltage source via the feedback resistor R and resistor r. The gain of the first stage (transistor 4) is derived by the collector resister Rc and the transconductance of transistor 4 (i.e. gain = The output of transistor 4 is shown a.c. coupled via capacitor Cl, although alternatively it may be d.c.

coupled, to the second stage 2 which is configured to have a low input impedance for reducing Miller capacitance. The output of the second stage 2 is then a.c. coupled via capacitor C2 to the feedback resister Rf, allof; ns trar r arce operation. The p-i-n photodiode 3 is reverse biased and is directly coupled to the base of transistor 4.

In both the low and high bit rate optical receivers (Figs 1 and 2 respectively), the d.c. component of the current emanating from the photodiode 3 and representing the mean optical power, must have a path to ground and this is provided via Rf and r. The voltage produced across r results from both the a.c. and d.c.

currents flowing. The a.c. signal is removed (without interrupting the transimpedance action) by the filter network of C3 and R3.

At low optical power, the output of op. amp. 5 is low due to the voltage across r being less than Vref, causing transistor Trl to be switched off. This causes the diode D, which will be discussed hereinafter, to be reverse biased hence minimising its depletion capacitance and resulting in a minimum reduction in both the receivers figure of merit and the corresponding sensitivity penalty. The figure of merit for the FET 1 2 iS17gm/CT and for the bipolar transistor 4 is P /CUT, where CT is the total input node capacitance. Hence, compared with the p-i-n photodiode 3 the diode D must have a low capacitance (and low leakage current) and can be realised by a high-frequency transistor, such as a JFET, or a GaAs FET.

The voltage across r increases with incident optical power, causing the output of the op. amp. 5 to be high and thus switching on transistor Trl when the voltage is greater than V ref at high input light levels. The optical threshold of this clamping action is determined by g (d.c.) = Vref/Rr where ss (d.c.) is the mean optical input power, R is the photodiode responsivity, r is the resIstance of the sensing resistor (r) and Vref is the predetermined reference voltage.

When transistor Trl is switched on and diode D is then switched to ground, the voltage across Rf and r is clamped to the sum of the diode voltage VD and the saturation voltage of Trl. This allows the excess current generated by the p-i-n photodiode 3 to flow to ground via the diode D, resulting (Fig 1) in a constant gate voltage and allowing the FET 1 to operate within pinch-off mode. Furthermore, with this arrangement the p-i-n photodiode reverse bias is prevented from going too low, thus maintaining the pin photodiode's slew rate/bandwidth.

The clamping action is achieved without the use of peak detection and simply uses the d.c. component of the optical input signal to control a diode device D that prevents overload of the front-end (FET 1 or bipolar transistor 4) and p-i-n photodiode 3, with a minimum reduction of receiver sensitivity. For greater simplicity, albeit at the expense of flexibility, the op.amp 5 can be omitted, resulting in the reference voltage being set by Vbe and Trl. The described circuits separate the a.c and d.c. components of the feedback signal and use the d.c. component of the optical input signal to control a variable impedance network including diode D and transistor Trl, in fact the d.c.

voltage drop across part of the feedback resistor is used to control the impedance of the front end of the receiver. The receivers of Figs 1 and 2 have improved dynamic range in comparison with conventional circuits and this is achieved with minimal penalty to sensitivity.

Claims

1. An optical receiver including an optical detector, a transimpedance amplifier whose input is connected to the detector output and a variable impedance connected to the detector output, and wherein the d.c.

2. An optical receiver as claimed in claim 1 wherein the optical detector is a reverse biased p-i-n photodiode.

3. An optical receiver as claimed in claim 1 or claim 2, wherein a feedback path of the transimpedance amplifier includes a feedback resistor and a capacitor in series and disposed such that only the a.c. component of the feedback signal is coupled via the feedback resister to the front end, and wherein a further resistor is connected to a point between the feedback resistor and the capacitor.

4. An optical receiver as claimed in claim 3, wherein the variable impedance includes a diode, connected to the detector output, and a transistor, wherein the d.c. voltage across the further resistor serves to switch on the transistor when the optical power incident on the detector exceeds a predetermined level whereby to allow the diode to conduct excess current generated by the detector away from the front end.

5. An optical receiver as claimed in claim 3 or claim 4 wherein the further resistor is connected to ground.

6. An optical receiver as claimed in any one of claims 4 to 6 wherein the d.c. voltage across the further resistor is compared with a reference voltage by an operational amplifier which switches on the transistor when high light levels are incident on the detector.

8. An optical receiver as claimed in claim 4 as appendent to claim 2 wherein the diode has a low capacitance and low leakage current in comparison with the p-i-n photodiode optical detector.

9. An optical receiver as claimed in any one of the preceding claims and wherein the trans impedance amplifier has an FET front end.

10. An optical receiver as claimed in any one of claims 1 to 7 and wherein the transimpedance amplifier has a bipolar transistor front end.

11. An optical receiver substantially as herein described with reference to and as illustrated in Fig 1 or Fig 2 of the accompanying drawings.

12. An optical receiver including an optical detector, a transimpedance amplifier whose input is connected to the detector output and a variable impedance connected to the detector output, wherein the variable impedance includes a diode, with low capacitance in comparison with the optical detector, connected to the detector output, and a transistor, and wherein the d.c.

13. An optical receiver as claimed in claim 12, wherein the feedback path of the trans impedance amplifier includes a feedback resister and a capacitor in series and disposed such that only the a.c. component of the feedback signal is coupled via the feedback transistor to the front end, wherein a further resister is connected to a point between the feedback resister and the capacitor, and wherein the d.c. voltage across the further resister serves to switch on the transistor when the optical power incident on the detector exceeds a predetermined level, whereby to allow the diode to conduct excess current generated by the detector away from the front end.