GB2246252A - Rechargeable battery management modules - Google Patents

Abstract

Battery 6 is charged by constant current stage 5a, 5b until a counter 2, counting pulses from an astable 1, reaches a predetermined count. Initial connection of a supply VS provides a pulse via capacitor 9 to reset pin 8 of counter 2, and diodes 21, 22 ensure that a temporary disconnection and subsequent reconnection of the supply will not reset the counter 2 until it reaches the predetermined count, whereby charging can be suspended, eg overnight, and restarted without altering the total recharging time. A load connected to terminals B+2, B-1 can be energised via diode 26 from battery 6, or via diode 27 from supply VS when connected. A monitoring circuit activates a bleeper 36, and turns off an output limiter transistor 34, when the battery has discharged to a certain voltage. The blooper 36 is also operated when the counter 2 terminates charging and the load is OFF, in order to warn a user that the supply VS should be disconnected. The circuitry module may be incorporated with AA size cells in a PP3 sized housing (Figs 2, 3), or AA, C or D sized cells may be separately installed. <IMAGE>

Description

RECHARGEABLE BATTERY MANAGEMENT MODULES This invention relates to rechargeable battery management modules The original dry battery in equipment required mainly for portable use can often be replaced by a rechargeable battery eg a nickel-cadmium (Nicad). The dry battery may be either a PP9 type power pack or made up of individual R6(AA), RI4(C) or R2o(D) cells. Nicad cells, with their constant-current charger, are more expensive initially but offer a potential life of many years usa and soon prove cost-effective. One known problem concerns a frequent need to remove and replace the cells for a 15 hour recharge.Fast timed charging can halve this period, but to preserve their full capacity, the Nicad cells must be discharged to I.OV per cell before commencing their recharge.

Equipment operation can be greatly simplified, especially for visuallyhandicapped users with portable radios, by housing the Nicad battery in-situ together with a small automatic control circuit. In daily operation, this management circuit monitors the gradual discharge of battery voltage and at the l.OV per cell level, eg at 6,OV for a 6 cell Nicad battery, it generates warning bleeps alerting the user to connect the mains or IC power supply lead.

This autonatically produces not only a fast, timed constant-current Nicad recharge supply but also an isolated supply for maintaining moderate equipment operation throughout recharge Another novel feature enables the user to temporarily remove the external power supply and suspend the recharge, but with its progress memorized during one or more breaks, usually overnight, the accrued recharge period of 7* hours or the like is unchanged. Should the equipment not be in use at recharge temination, further bleeps can now remind the user to remove the recharge supply lead and return to portable operation.

According to the present invention there is provided a rechargeable battery management module comprising a control unit PCB assembly, either mounted on a box housing 6 Nicad AA cells to equal the overall size of a PP9 dry battery, or separately installed with 4 to 8 individual AA, C or D Nicad cells enabling replacement of either type of dry battery in-situ in portable equipment, wherein the control unit supervises the Nicad battery recharge and discharge cycling, the means for recharging being adapted from a known automatic timing circuit whereby an astable clock IC produces count pulses for a CMOS multistage binary counter IC controlling a PNP driver transistor, LED diode and a Darlington constant-current output stage feeding the Nicad negative pole, its positive pole being routed via a blocking diode, forward-biased in recharge, to the Vs+ rail of a DC voltage supply provided from either the equipment's mains PSU, r an external DC power supply, but since the counter's output stage had returned to logic high to turn-off the PNP driver and terninate the last recharge, a momentary positive-going pulse is now required to again reset all the counter binary stages to logic low to turn-on the PNP driver, restart the clock and commence the new recharge; the said reset pulse is derived from the known reset capacitor connected across the control unit Vs+ supply input with the capacitor upper plate at the V5 + rail and its lower plate coupled to the counter IC reset pin and via a timing resistor to the Vs- rail; when the user connects the external recharge power lead to switch on the V5+ supply, the lower plate of the initially discharged capacitor rises momentarily with the upper plate to the V5 + rail to generate the required positive-going reset pulse for the counter IC reset pin and commence a fast continuous recharge of 2 hours or the like; but since the known reset circuit offers little overcharge protection against a temporary loss of recharge power causing unwanted resets of the counter stages, and since the said resets can occur at both the disconnection and reconnection of recharge power, means are provided whereby the known reset circuit is adapted to include two extra diodes and a resistor to inhibit either cause of counter reset once recharge has commenced; the first diode is normally reverse-biased with its cathode coupled to the reset capacitor lower plate and anode to VS -, but becomes forward-biased to suppress and thereby inhibit a momentary negativergoing capacitor pulse noted at recharge power disconnection and found to cause a counter reset; the second diode, with anode coupled with the added resistor from the capacitor lower plate to the counter IC reset pin, is initially reverse-biased by its cathode at the counter output pin, logic high prior to recharge; this enables the initial positive-going pulse to reset the counter stages to logic low to start the recharge but the diode now becomes forward-biased to suppress and thereby inhibit any further counter resets related to positive-going pulses produced at recharge power reconnection after temporary breaks; by this means the user can safely suspend recharge for one or more convenient breaks, eg overnight, with its progress memorized by sourcing the CMOS counter Vcc supply voltage continuously from the Nicad battery to maintain the logic state of all the counter binary stages during the said breaks; after each break the astable clock pulses resume until reaching the total count required by the counter to terminate the delayed 7+ hour recharge or the like;. means are provided to ensure the PNP driver is turned fully off when the counter output rises to logic high to terminate recharge whereby a forward-biased diode is added in the driver emitter lead to offset the blocking diode voltage drop between V and the counter VDD pin fed via the Nicad B+ pole; means are provided whereby two extra diodes and two resistors form a currentdivider circuit enabling moderate equipment current during recharge effectively isolated from the Nicad constant-current supply wherein one forward-biased diode with cathode at Vs- feeds equipment current via a limiting resistor to the B-I output terminal; the second diode is initially reverse-biased with its cathode at Nicad B- pole and anode at B-I, with the Nicad B- standing voltage raised to about 2.5V w.r.t. V5-by.a series resistor fed from the Darlington stage during recharge; to normalize Nicad constant-current and offset power supply load changes, a 27V zener diode is added to assist the LED diode regulate the Darlington base voltage; when recharge ends, the Vsa supply continues to power equipment and the. Nicad remains blocked; upon removal ef the external power lead, the two current-divider diodes reverse state to enable the Nicad battery to power the equipment via the B+2, B-I output terminals; when the equipment ON/OFF power switch is fitted in its negative rail and switched ON, it provides an earth return to the control unit OV terminal to power the Nicad discharge \ monitoring circuit; means are thereby enabled for generating warning bleeps to remind the user to remove the etternal power lead if still in place when the equipment is OFF at recharge termination in which a zener diode, shunted by a high value resistor and located between OY and VS- rails, conducts when the VS supply voltage rises above its normal level when off-load and.energizes the monitor bleep generator IC; the automatic means for monitoring the gradual decrease of Nicad battery voltage from about I-4T per cell after recharge to the I-OV end-point level includes a known NPN emitter follower circuit working at constant current to provide a constant collector-emitter voltage drop, preset by adjusting the base voltage, enabling the decrease in Nicad positive voltage at the collector to be transferred to the emitter load resistor where the initially high output is adapted to turn tn NPN driver transistor hard on and its resultant very low collector voltage drives a PNP output limiter in the 3+2 output rail into full conduction and inhibits a two-input CMOS quad NAND gate bleep generator IC; sampling continues with the Nicad and emitter follower voltages slowly falling in step for many operating hours until the Nicad voltage nears I.QV per cell, at which point the emitter follower base preset has been adjusted to ensure the falling emitter output starts to turnoff the NPN driver and its collector voltage rises to activate the bleep generator and progressively reduce PNP limiter output until equipment operation ceases; the Nicad voltage stabilizes at IOV per cell and bleeps continue until the external power lead is connected to commence a recharge and restart operation or the equipment is switched OFF.

A specific embodiment of the invention will now be described by way of example with reference to the accompanying drawing in which : Figure I shows a simplified circuit diagram of the module, omitting the normal timing and decoupling components for clarity; Figure 2 shows a simplified plan view of the module PCB layout; Figure 3 shows the module PCB assembly mounted on a box containing 6 AA Nicad cells to equal with Figs. 2-4 the overall size of a PPq dry battery; Figure 4 shows a side view of the module, but where individual AA, C or D Nicad cells are used, the box is removed and the PCB unit mounted separately.

Referring to Fig. of the drawing, the components on the left and below the Nicad battery 6 provide for recharge, whilst those on the right monitor Nicad discharge, whereby the known recharge circuit includes IC astable I, CMOS IC multi-stage binary counter 2, PNP driver 3, LED diode 4 and the Darlington ecristant-current stages 5a,ib; to terminate a recharge, output 7 of counter 2 returns to logic high, therefore to start a new recharge a momentary positivegoing pulse is required at counter pin 8 to reset all its stages to logic low, and this pulse is provided by reset capacitor 9 with upper plate 9a connected from the Vs+ recharge supply via dropper resistor IO, and lower plate 9b linked via resistor II to counter reset pin 8; when the Vs supply is switched on by the user from the hoat equipment's mains PSU or eternal IC power supply both plates 9a,9b of the initially discharged capacitor 9 rise to the Vs+ rail to produce the required positive-going pulse at reset pin 8; with all counter stages now reset to logic low, PNP driver 3 turns hard-on and its collector voltage I2 rises to reset IC astable I via pin 13 to initiate clock pulses for IC counter 2 input I4, activate LED diode 4 and enable Darlington stages 5a,5b to commence a Nicad constantcurrent recharge at a rate controlled by LED 4 anode volts at base I5 of transistor 5a and emitter resistor I6 value, and with blocking diode 17 now forward-biased, the recharge proceeds normally; new assuming by way of example that astable I produces a count pulse every 3-3 8 for a CMOS I4-stage binary counter then after 8I92 counts all its stages complete their timing functions and output pin 7 returns to logic high to end a nominal 7+ h fast recharge, at a required rate of IOOmA for AA 015Ah Nicad cells, and 240mA for C and D I-2Ah Nicad cells, selected by emitter resistor I6.

This typical recharge circuit works well provided that recharge is continuous, but if interrupted,reset capacitor 9 operates to reset counter 2 stages again and unduly prolong the rechntge tizing program. However, it is of practical advantage,both for Nicad protection and for convenience,to enable suspension of recharge, especially with the module located in-situ in the equipment.

The known recharge circuit detailed above is therefore adapted to include six additional diodes, one being 2V7 zener diode I8 which with resistors I9,20 assists LED 4 to stabilize the constant-current rate against changes caused by equipment ON/OFF operation and mains fluctuations; two diodes 2I,22 and preferably Schottky, inhibit any counter 2 reset after a recharge commences, enabling the user to safely suspend recharge for any needful period by removing the external power supply, whereby diode 22, with its anode coupled to counter reset pin 8 and cathode to counter output 7, is reverse-biased before recharge commences since output 7 is logic high; this enables the initial positive pulse from capacitor plate 9b to reset all counter 2 stages to logic low when power is connected to start another recharge with counter output 7 now logic low, diode 22 becomes forward-biased to suppress, with resistor II, any subsequent reset pulses at counter pin 8 following a power reconnection after a recharge suspension; whilst diode 21, normally reverse-biased with its cathode coupled to capacitor plate 9b and anode to Vs-, becomes forward-biased to suppress a momentary negative-going pulse at plate 9b noted when power was disecnnecied to suspend a recharge, and thereby inhibit the resultant counter 2 reset when plate 9b discharged via resistor 23.

When the user disconnects external power to suspend a recharge, the VS supply is disabled to switch-off astable Driver 3,LED 4, Darlington stages 5a,5b and halt counter input pulses 14, but to sustain and memorize the logic state of all counter 2 binary stages, the counter VDDa pin 24 is supplied from the Nicad B+ pole throughout; when external power is reconnected to continue the recharge, counter pulses '14 resume until the delayed total count is reached and the recharge terminates after an accrued nominal period of 7 b or the like; to offset diode I7 voltage drop between the V5+rail and counter VDD pin 24, diode 25 is added in PNP driver 3 emitter lead to ensure that driver 3 fully turns-off Darlington stages 5a,5b when the recharge terminates. Two Schottky diodes 26,27 form a current-divider circuit during recharge to isolate Nicad constant current from equipment operating current provided from the VS - rail via diode 27 and resistor 28 to output terminal B- I.Resistor 29 is added between Darlington collectors 5a,5b and the Nicad B- pole to raise the B- pole standing voltage to about +2-5T w.r.t. Vs- to ensure that diode 26 cathode remains reverse-biased w.rt. its anode at about I-75V via output terminal B-I When a recharge terminates, the equipment continues to draw power from the Vs+ supply until the external power lead is removed; diodes 26 and 27 then reverse state to enable the Nicad battery to power equipment via diode 26.

To provide warning bleeps to remind the user to remove the external power lead when a recharge terminates and the equipment is not in use requires that the equipment ON/OF switch can isolate the B-I output from the OV earth return in its negative rail when switched OFF; this enables zener diode 30, connected with high value resistor 31 between the OV and VS- rails, to be selected to conduct only near the higher voltage to which the VSaupply rises when very lightly loaded and thereby provide the Nicad battery monitor circuit with sufficient current to generate the warning bleeps that the recharge has ended, and the external power lead can be removed and portable operation resumed.

The Nicad discharge monitoring circuit comprises NPN emitter-follower 32, NPN driver 33, PNP output limiter 34, CMOS two-input quad NAND gate IC 35, and piezo buzzer 36. With the equipment switched ON to connect B-I output to the OV earth, emitter-follower 32 operates at constant-current to provide it with a constant collector to emitter voltage drop, controlled by resistor 37 and base voltage preset 38, enabling the slow decrease in the Nicad B+ voltage during operation to be transferred and monitored at emitter-follower output 40 ,across load resistor 39 The initially high emitter output voltage 40, connected via resistors 41,42, turns driver 33 hard-on, and the very low voltage at driver collector 43 via load resistor 44 drives output limiter 34 into full conduction via base resistor 45 and provides a logic low to inhibit input 46 of NAND IC 35.

The Nicad B+ voltage and emitter output voltage 40 fall in step v.rt. OV until the Nicad voltage nears I-OV per cell, eg 6.oV for a 6 cell battery; at this end-point level the emitter-follower preset 38 is adjusted during test to ensure that emitter output voltage 40 starts to turn-off NPN driver 33 and its collector voltage 43 then rises to provide a logic high at input 46 to activate NAKED gate 35 and produceXwarning bleeps from piezo buzzer 36, and progressively reduce output limiter B+2 output until equipment operation ceases.The Nicad voltage stabilizes at I-OY per cell and bleeps continue until the external power lead is reconnected to commence another recharge and resume equipment operation or the equipment with its monitoring circuit is switched OFF.

Referring to the drawing, Fig 2 shows the location of major components on PCB 47, with Darlington transistor 5b using heatsink 48a, output limiter 34 using heatsink 48b and terminal block 49 providing all connections; Figs 2-4 show heatsikks 48a,48b and PCh 47 nounted on box 50 housing six At Nicad cells -forming battery 6; in this mode the whole assembly equals the overall size of a PP9 dry battery; piezo buzzer ó can ba fixed on internal cross-brace 50d or between heatsinks 4Ba,48b on PCB 47. Nicad retaining strip 51 serves also for referencinn TRI connections.

In order to house individual AA, C or D Nicad cells, box 50 is not required and PCB 47, complete with heatsinks 48a,48b and buzzer 36, is mounted separately in the equipment. Where a dry battery and mains PSU formerly gave alternative DC power supplies, with the battery isolated upon insertion of the external power plug, now Nicad 6 is wired to module B+, B- terminals, and the DC power supply transferred from directly operating the system to module V5* input terminals with outputs B+2,BSI, OV now powering the operating system.

Claims (5)

1. CLAUSE

   I A rechargeable Dattery management module comprising a control unit P:B assembly, eitner mounted on a box housing six Nicad AA cells to equal tne overall size of a PP9 dry battery, or separately installed with 4 to 8 individual AA, C or D Nicad cells, enabling replacement of either type of dry battery in-situ in portable equipment, wherein the control unit supervises the Nicad battery recharge and discharge cycling, the means for recharging being adapted from a known automatic timing circuit whereby an astable clock IC produces count pulses for a CMOS multi-stage binary counter IC controlling a PNP driver transistor, LED diode and Darlington constant-current output stage feeding the Nicad negative pole, its positive pole being routed via a blocking diode, forward-biased in recharge, to the VS + rail of a DC voltage supply provided from the equipment's mains PSU or an external source, but since the counter's output stage had returned to logic high to turn-off the PNP driver and terminate the last recharge, a momentary positive-going pulse is now required to again reset all the counter's binary stages to logic low to turn-on tne PNP driver, restart the clock and commence the next recharge; tne said reset pulse is derived from the known reset capacitor connected across tne control unit vSf stipply input with the capacitor upper plate at the VS + rail and its lower plate coupled to the counter IC reset pin and via a timing resistor to tne Vs- rail; wnen the user connects tne external power lead to provide the V5 supply, the lower plate of the reset capacitor rises momentarily with the upper plate to the VS + rail to generate tne required positive-going reset pulse for the counter and thereby commence a fast continuous recharge of 7 hours or the like; but since tne known reset circuit offers little overcharge protection against a temporary loss of recharge power causing unwanted resets of tne counter, and since the said resets can occur at both the disconnection and reconnection of the V5 supply, means are provided whereby the known reset circuit is adapted to include two extra diodes and a resistor to inhibit either cause of counter reset once recharge has commences;;the first diode is normally reverse-oiased by its catnode coupled to the reset capacitor lower plate and anode to V5- but becomes iorward-biased to suppress arc thereby inhibit a momentary negative-o1n capacitor pulse ncted at recnarge power disconnection and found to cause a reset during its discharge;; tne second diode, witn its anode couple witn tne adder resistor from tne capacitor lower plate to tne counter reset pin is initially reverse-Diasea by its catnode at tne counter Output pius, logic neigh prior to recharge; this eriaoles tne initial positive-oirz pulse to reset all tne counter binary stores to logic low to start tne recharge but tne diode now becomes forward-biased to suppress and thereby inhioit any furtner counter resets related to positive-going pulses produced at recharge power reconnection after temporary breaks; by this means the user can safely suspend recharge for one or more convenient breaks eg overnight, with its progress memorized by sourcing the CMOS counter VCC supply continuously from the Nicad battery to maintain the logic state of all its binary stages during the said breaks; after each break the clock pulses resume until reaching tne total count required to terminate the delayed recharge; means are provided to ensure the PNP driver is fully turned-off wnen tne counter output rises to logic high to terminate a recharge whereby a forward-biased diode is added in the driver emitter lead to offset the-ulocking diode voltage drop between Vs + and the counter VDD pin fed from the Nicad battery B+ pole; automatic means for monitoring the gradual decrease of Nicad battery voltage during equipment operation from about I-4V per cell after recharge to tne I.OV end-point level includes a known NPN emitter-follower circuit operating at constant-current to provide a constant collector-emitter voltage drop, preset by adjusting its base voltage, enabling the decrease in Nicad B voltage at its collector to be transferred to its emitter load resistor whereby the initially high voltage is adapted to turn an NPN driver transistor hard-on and its very low collector voltage drives a PNP output limiter in tne B+2 output rail into full conduction, and also inhibits a two-input CMOS ouad iV3 gate bleep generator IC; sampling continues with tne Nicad and emitter-follower voltages slowly falling in step for many operating hours until tne Nicad voltage nears I.OV per cell, tne end-point level to wnicn tne emitter-follower base preset nas been aajustea to ensure tne falling emitter output starts to turn-off tne I driver an its rising collector voltage activates tne bleep generator and progressively reduces the PSS limiter output until equipment operation ceases; the Nicad voltage stabilizes at about I-OV per cell and bleeps continue until the external power lead is recormected to conimence another recharge and restart operation or the equipment is switcned OFF.
2. 2 h recnargeaDle battery management module as claimed in 1 aim I wnerein tne reguiation means to normalize Nicad constant-current and offset power supply load cnanges during recharge is provided oy a 2 7 zener diode and a series resistor assisting tne LEi) diode regulate tne Darlington base voltage
3. 3 A rechargeable battery management module as claimed in Claim I or Claim 2 wnerein means are provided whereby two extra diodes and two resistors form a current-divider circuit enabling moderate equipment current during recharge effectively isolated from tne Nicad constant-current supply wnerein one forward-biased diode with its cathode at Vs- feeds equipment current via limiting resistor to the B-I output terminal; the second diode is initially reverse-biased by its cathode at Nicad B-and anode at B-I terminal, witn tne Nicad B- standing voltage raised to about 2.5ViC w.r.t. Vs - by a series resistor from tne Darlington collectors during recharge; when recharge ends the V5+ supply continues to power the equipment and the Nicad battery is blocked until tne external power lead is removed, wnereupon the two currentdivider diodes reverse state to enable tne Nicad battery to supply power via the module B+ 2, B-Ioutput terminals.
4. 4 A rechargeaDle battery management module as claimed in Claim 3 wherein means is provided for generating warning bleeps to remind the user to remove the external power lead wnen recnarge terminates witn the equipment switcned OFF, dependent on tne equipment ON/OFF power switch being located in its negative supply rail, and when ON providing an earth return via the module OV terminal to power the ì{icai discnarge monitoring circuit; tnis enables a zener diode, shunted by a hign value resistor, and fitted between the module OV and Vs- rails to conduct wnen the VS supply voltage rises above its normal level wnen off-load and tnereby energize tne monitor IDLED gate bleep generator 10.
5. 5 A rechargeaole Dattery management module substantially as descriDei herein with reference to figures I - 4 of tne accompanying drawing.