GB2243931A - Chaining circuit modules - Google Patents

Abstract

A circuit module (e.g. memory chip on a wafer) includes circuitry for connecting it into at least one chain of circuit modules. Each module has at least two sets 16, 18 of data inputs and outputs. Each of these sets can be used to connect the module into any chain of circuit modules, whereby two different spiral paths may pass through one module. The module may also include circuitry for selectably linking any set of data inputs to any set of data outputs and to selectably link any set of data inputs and data outputs to the functional circuitry or the module. <IMAGE>

Description

IM?ROVE##ENTS IN CONFIGURATION LOGIC FOR CHXIDED CIRCUIT MODULES .

This invention relates to configuration logic for circuit modules which enables modules to communicate with their neighbours such that they may be configured into a chain and in particular to systems where more than one chain exists in a group of modules.

GB-A 1,377,859 describes a system for connecting modules together in a chain or spiral path using programmable configuration links on each module. In, for example, a wafer scale integrated circuit comprising a plurality of undiced memory chips, a chain of modules is grown by designating a start chip on the edge of the wafer and testing its neighbours to determine which way the spiral should go and then repeating this process for the selected next chip. This continues until as many as possible of the chips on the wafer are included in the spiral. The configuration logic for each chip consists of a transmit (XMIT) path for sending data from the start chip to a designated target chip and a receive path (RECV) for sending data from the target chip to a controller.It is a well known technique to provide programmable transmit and receive paths in each of the north, south, east and west directions from a designated chip. In each direction there will be an XMIT in and an XMIT out path along with a RECV in and a RECV out path.

See for example GB-A 2 177 825.

It is also known from GB 2174518 to provide chips in which more than one input/output direction can be configured such that a branching tree network of chips can be configured on a wafer. In this network growth of the tree has to take place in more than one direction from a chip. However, XMIT and RECV paths are configured so that the path of interconnection of the chips remains a single spiral path which can lead to relatively long access times for chips towards the far end of the path.

when a spiral is grown on a wafer it is found that stubs occur which prevent the spiral from progressing in certain directions. There are two types of stubs, hard and soft.

Hard stubs occur in situations such as the one shown in Figure 1 where a usable chip 10 adjacent to a spiral path 12 is surrounded by defective chips 14. The configuration logic for this type of chip only allows one input and one output direction to be programmed at any one time so in order to access this chip it is necessary temporarily to reprogram the cormnunications links between chips as described in G3-A 2 181 870. This clearly adds to the access time. The other type of stub is a soft stub and this is caused when a chip is surrounded on three sides by chips which are already included in the main spiral. Thus the spiral in effect blocks itself.

One way of improving access times and increasing data transfer rates on wafers is to configure more than one spiral on the same wafer. It will be appreciated that when more than one spiral path is configured on one wafer the problems of, in particular, the soft stubs will be much greater since spirals will block each other more frequently than with a single spiral.

Another problem with creating multiple spirals on a single wafer is that of equally distributing the total memory or processing capacity of the wafer between the spirals. This problem has to be addressed when configuring the multiple spirals on the wafer otherwise significant memory capacity can be lost.

One object of the present invention is to provide an improved configuration logic system on each chip such that the number of chips on stubs is reduced for both single and multiple spiral paths.

Various aspects of the invention are defined in the appended claims to which reference should now be made.

The invention will now be described in more detail by way of example with reference to the drawings in which: Figure 1 shows a hard stub formed by defective chips as described above; Figure 2 shows the intersection of two spiral paths through chips embodying the inventions; Figure 3 is a schematic circuit diagram of configuration logic embodying the invention; Figure 4 is a more detailed diagram of the circuitry of Figure 3; Figure 5 is a schematic diagram illustrating how a DRAM chip is accessed by the circuitry of Figure 3; Figure 6 is an illustration of how the current invention includes a chip in a stub in the main spiral path.

Figure 7 shows a further module with its connections to other modules in an array; Figure 8 shows an array of modules of the type illustrated in Figure 7 with four spiral paths passing therethrough; and Figure 9 shows an array of modules in which two spiral paths pass through two coitn#n modules.

In the present invention configuration logic is provided on each chip (or module) which enables both primary and secondary data paths to be directed through each chip. Figure 2 shows schematically the intersection through a module 11 of two such data paths labelled path 1 and path 2. The primary configuration logic is similar to that in existing systems (e.g. GB-A 2 177 825) and enables data paths to be configured in the north, east, south and west directions. The secondary data paths are enabled by further configuration logic which enables connections to be made to chips in the north east, north west, south east and south west directions, i.e. with the diagonally adjacent chips.

Using this type of configuration logic permits two independent entry directions into a chip and two independent exit directions from a chip. This allows two different spiral paths to pass through the one chip.

A schematic diagram of the configuration logic used by this invention is shown in Figure 3; for the purposes of this example we shall assume that the data lines shown in this figure are the XEET lines. Configuration of the RECV data lines will be similar to the configuration of the XMIT lines.

The primary configuration logic 16 and the secondary configuration logic 18 are each of a similar circuit structure to that described in our GB-A 2,177,825 and the input and output directions for each of these configuration logics 16 and 18 are selected by programmable carranands received on an XMIT line. The primary configuration logic handles connections in the N, E, S and W directions whilst the secondary logic handles connections in the NE, NW, SE and SW directions.

The configuration logic described in GB-A 2177825 enables any of the N, S, E, and W XMIT input lines to supply data to a chip, the four XMIT input lines preferably being ORed together. However, the XMIT output data lines are programed by ccamands received on the XMIT data line such that a signal travelling through the chip on the XMIT line will only be available at one of the XMIT outputs.

The reverse situation applies to the RECV data lines in that a single RECV input data line is programmably selected to receive data from the same direction as the selected XMIT output data line outputs data. The RECV output is available in all four output directions.

The current invention is intended to be used with circuitry of the above type but it is not limited to this type of use.

The circuit shown further camprises an exchange line 20 which has either a logic 0 or a logic 1 applied to it. This exchange line 20 controls change over switches in the primary and the secondary configuration logic 16 and 18 in such a way that when a logic 0 is applied to exchange, a signal entering a chip on one of the primary data lines leaves on one of the primary data lines and a signal entering on one of the seconday data lines leaves on one of the secondary data lines.

when a logic 1 is applied to the exchange line 20 the changeover switches are so controlled as to cause signals entering on the primary and secondary lines to be exchanged between the primary and secondary configuration logic 16 and 18 via cross over lines 22. Thus a signal entering on a primary data line leaves on a secondary data line and a signal entering on a secondary data line leaves on a primary data line.

The circuitry of Figure 3 is shown in more detail in Figure 4.

In this, we have the primary and secondary configuration logics 16, and 18 which each include four inputs and four outputs as shown in Figure 3. Only the XMIT lines are shown here to illustrate the system.

A token bit received via any one of the eight input lines is loaded into a command decoder 40 which , as in GB-A-2177825, includes a shift register arrangement along which the token bit is clocked. When the global command line CMD is invoked, the circuitry will execute a command in accordance with the position of the bit in the shift register arrangement.

The commands available include a SElECT command which is executed by SELECT circuitry 42 to choose either the N, E, S, or W output directions for XMIT and this is extended in this case to additionally choose one of the NE, NW, SE, or 5W output directions if appropriate with SELECT circuitry 44 i.e.

when two spirals use the chip or when one spiral uses the chip with the exchange function invoked. In the current invention, the commmand decoder may also control the exchange control with a further command. The exchange control simply controls two crossover switches 46 which either connect the primary inputs to the primary outputs and the secondary inputs to the secondary outputs, or, connect the primary inputs to the secondary outputs and the secondary inputs to the primary outputs. In the example of Figure 4, the command decoder 40 also has a SEL command which is used to control further multiplexing circuitry to grant access to the chip circuits (e.g. DRAM) to either the primary or the secondary configuration logic 16, 18.

This exchange command is not essential to the invention since simply providing the facility for a chip to receive and transmit to two independent spiral paths greatly increases the ease with which the spirals can be configured on a wafer. The exchange control 20 allows an even further degree of freedom in the configuration of spirals.

It is preferable that both the primary and secondary configuration logic 16 and 18 should be able to access the functional circuitry on the chip. Let us assume that the chips we are considering are DRAMS. Where both the primary and secondary data paths do have access to the DRAM they will not be able to access it at the same time. A schematic diagram of the circuitry for accessing a DRAM on a chip is shown in Figure 5.

In this circuitry, multiplexing circuitry 24 is connected to both the primary and the secondary configuration logic 16 and 18. This multiplexing circuitry 24 is further coupled to the DRAM 26. The multiplexing circuitry 24 allows either the primary or the secondary configuration logic 16 or 18 access to the DRAM 26 in dependence on the logic state of a select input 28. The select input SEL will be generated by the command decoder as described above with reference to Figure 4 under the control of a signal received on an XMIT data line.

The fact that both the primary and secondary configuration logics 16 and 18 can access the DRAM 26 is an aid to balancing the memory capacity of multiple spirals on a wafer such that the spirals have as near as is possible, a similar memory capacity to each other. This helps reduce the problems of addressing different spirals on the same wafer. It also enables the DRAM to be accessed when one of the sets of configuration logic is defective. For example, if the primary logic is defective and cannot access the DRAM or receive or transmit data, the secondary logic is used for access to be made to that DRAM.

An example of how this new configuration logic handles a stub is shown in Figure 6. In this example the first chip shown in the spiral is chip 30 and the spiral enters this chip from the south direction. The exchange control is switched to logic 1 on this chip and the spiral exits in the north east direction thus entering the chip on the stub 31 from the south west direction. The only direction in which the spiral can exit chip 31 is the west direction and it does this, entering chip 32 from the east. From chip 32 the spiral continues northwards to chip 33 and beyond. Chip 31 will also have its exchange control set to logic 1.

From the above it can be seen that this improved configuration logic will enable better use of the chips on a wafer to be made, particularly where multiple spiral paths exist on a single wafer. The configuration logic for one set of input paths and one set of output paths is usually less that 10% of the total configuration logic on a chip and thus the addition of another set of input and output paths does not greatly increase the amount of chip space used by the configuration logic.

Further degrees of freedom can be added to the spiral configuration by providing further sets of input and output paths for each module. An example is shown in Figure 7. In this an array of twenty five modules 11 is shown. The central module 50 has input and output paths connected to the adjacent modules 52 in the N, S, E, W, NE, SE, SW, and NW directions as has been described above. The central module 50 also has input and output paths connected to each modules 54 displaced by one module in each of the N, S, E, W, NE, SE, SW and NW directions.

Modules can in fact be arranged with other numbers of input and output paths. Possible connections to six adjacent modules is a useful arrangement and improves the flexibility of a module for a modest increase in configuration logic circuitry.

Where the array of Figure 7 is part of a wafer-scale integrated circuit then the connections to the modules 54 would be formed from conductive tracks which go either through, around, over, or underneath the adjacent modules 52.

Each module shown in Figure 7 will have a similar set of input and output paths to the central module 50. These additional sets of input and outputs paths are included in the configuration logic by m3difying the circuitry of Figure 4.

The exchange command for such a module will require multiplexing circuitry to enable a selected input direction to communicate with any selected output direction. This can be implemented in a well known manner.

Using such a system, spirals such as those shown in Figure 8 can be configured. This shows four spirals in an array containing three modules with defective configuration logic.

Connections to operative modules are indicated by the circles.

There are no connections to the defective modules 56. It can be seen from this that simply encountering a defective module 56 need not halt progression of the spiral in a given direction.

In systems where two or more spirals pass through the same module it is important to ensure when configuring the spirals that such a module does not have the same logical module number on each spiral. If it did have the some logical module number then problems would be encountered when the spirals were addressed in parallel. An example of a pair of spirals 58 and 59 in an array of modules is shown in Figure 9. This shows logical module numbers for the broken line spiral 58 in the bottom right hand corner of each module and logical module numbers for the solid line spiral 59 in the top left hand corner of each module. There are two modules (3 and 13 on the solid line spiral 59) where the two spirals meet but the logical module numbers of these is different for each spiral.

A system using two or more spirals through an array of modules could be accessed by a corresponding number of computers or processors, one computer per spiral. The arrangement might be such that at least one of the modules was passed through by all of the spirals. Thus each computer could perform different processing operations on the same piece of data simultaneously.

Claims (14)

1. A circuit module for inclusion in at least one chain of modules passing through an array of circuit modules, the module comprising at least a first set and a second set of data inputs and data outputs for selectably linking the module to modules in the chain.

2. A circuit module according to claim 1, in which the module is substantially rectangular and the first set of data outputs communicate with modules adjacent to the sides of the circuit module and the second set of data inputs and data outputs commLnicate with modules adjacent to the corners of the circuit module.

3. A circuit module according to claim 2, in which the module includes a third set and a fourth set of data inputs and outputs for communicating with modules adjacent those modules communicated with by the first and second sets of data inputs and outputs.

4. A circuit module according to claim 1, 2 or 3, including means for selectably linking any set of data inputs to any other set of data outputs.

5. A circuit module according to claim 4, in which the linking means comprises changeover switches under the control of a logic signal.

6. A circuit module according to any preceding claim, including a second means for selectably linking any set of data inputs and data outputs to the functional circuitry of a module.

7. A circuit module according to claim 5 in which the second linking means comprises multiplexing circuitry under the control of a logic signal.

8. A wafer scale integrated circuit comprising a plurality of circuit modules as defined in any preceding claim.

9. An array of circuit modules as defined in any preceding claim and having at least two chains passing therethrough, each chain being accessed by a separate computer.

10. An array of circuit modules according to claim 9 in which at least one circuit module is included in more than one of the chains.

11. A circuit module for inclusion in at least one chain of circuit modules substantially as herein described with reference to the drawings.

12. A circuit module for inclusion in at least one chain of circuit modules, the module comprising at least a first set and a second set of data inputs and data outputs, decoding means responsive to data received via a data input to selectably link any set of data inputs to any set of data outputs and to selectably link any set of data inputs and data outputs to the functional circuits of the module.

13. A circuit module according to claim 12 in which the decoding means including means for selecting only one output from a set of data outputs for connection to a set of data inputs.

14. A circuit module according to claim 12 or 13 in which the decoding means includes means for selecting only one input from a set of data inputs for connection to a set of data outputs.