GB2103400A

GB2103400A - Data processing system

Info

Publication number: GB2103400A
Application number: GB08221699A
Authority: GB
Inventors: Stewart Fiddian Reddaway
Original assignee: Fujitsu Services Ltd
Current assignee: Fujitsu Services Ltd
Priority date: 1981-08-06
Filing date: 1982-07-27
Publication date: 1983-02-16
Also published as: GB2103400B

Abstract

A data processor consisting of a plurality of modules each containing a sub-array of processing elements (P). Within each module, the connections to at least two of the elements (P) on one edge of the sub-array share a set of external terminals (12) with the connections to the same number of elements (P) on an adjacent edge of the sub- array. For example, if each sub-array contains 4 x 4 elements, the four elements along the northern edge can share the same four external terminals (12) with the four elements along the western edge, thus reducing the number of external terminals (12, 14, 16) required from sixteen to twelve. <IMAGE>

Description

SPECIFICATION Data processing system Background to the invention This invention relates to a data processing system of the kind comprising a plurality of data processing elements connected together in a rectangular array such that each element can transfer data to its four nearest neighbours. Such a system is described, for example, in British Patent Specifications Nos. 1445714, 1536933, 2020457 and 2019620.

Such a system may conveniently be constructed from a plurality of identical modules, each of which contains a sub-array of the processing elements. Such modules may for example be LSI (large-scale integrated circuit) chips, or printed circuit boards with semiconductor components mounted on them.

Clearly, the number of external terminals required on each module depends on the number of processing elements in the module. For example, if the module contains a 4 x 4 sub-array of processing elements, it would appear that sixteen external terminals (four along each edge of the sub-array) are required to connect the module to adjacent modules. This is in addition to other terminals required e.g. for control signals, addresses, power supplies and so on. However, the number of available terminals on any particular type of module is usually strictly limited (e.g. an LSl chip has a limited number of pins). This imposes an upper limit to the number of processing elements which can be incorporated in the same module.

One way of alleviating this problem is described in specification No. 2020457 mentioned above. That specification describes a way of reducing the number of terminals required for connection to adjacent sub-arrays by combining two adjacent terminals on adjacent edges of the sub-array. For example, in the particular embodiment described in that specification, a single terminal (the NW terminal) serves to carry data either northwards or westwards, according to the value of a routing code. Similarly, another terminal (the SE terminal) carries data either southwards or eastwards. This arrangement therefore achieves a saving of two terminals per chip.

One object of the present invention is to provide a way of achieving greater savings in the number of terminals required for connecting adjacent sub-arrays.

Summary of the invention According to one aspect of the invention a data processing system module comprises an array of n x n processing elements, each processing element being connected to neighbouring elements in the array, in which external connections to at least two of the elements on one edge of the array share common external terminals with an equal number of elements on an adjacent edge of the array.

According to another aspect of the invention a data processing system comprises a plurality of processing elements connected together in a rectangular array such that each element is operable to transfer data to its neighbouring elements, the array being subdivided into a plurality of modules each of which contains an n x n sub-array of processing elements wherein within each module the connections to at least two of the elements on one edge of the sub-array share common external terminals with an equal number of elements on an adjacent edge of the sub-array and wherein each shared terminal is connected externally of the module to two unshared terminals on respective adjacent modules.

Brief description of drawings One data processing system in accordance with the invention will now be described by way of example with reference to the accompanying drawings of which Figure 1 is an overall view of the system; Figure 2 shows one module of the system in more detail; Figure 3 shows, in more detail, one of the data processing elements; and Figure 4 illustrates an alternative form of module.

Description of the preferred embodiment of the invention Figure 1 shows a data processing system comprising a plurality of modules 10, each module being an LSI chip. Each module has three groups of terminals 12, 14 and 16 for making connections with neighbouring modules, each group consisting of four terminals. It should be noted that although the modules are shown schematically as being triangular in shape, this is for convenience of illustration only; in reality, they would normally be accommodated in a conventionally shaped LSI package.

The modules are connected together in a rectangular array of rows and columns as shown. The group of terminals 12 in each module is connected by way of branched paths 18 to the group 14 on neighbouring module in the northern direction, and also to the group 16 on the neighbouring module in the western direction. (The terms "north", "east", "south" and "west" are used in this specification merely to describe the logical relationships between the modules and elements and should not be taken to imply any particular physical arrangement).

Figure 2 shows one of the modules 10 in greater detail. The module contains a 4 x 4 sub-array of processing elements P. Each element may be similar to those described in the above mentioned published specifications, and will therefore not be described in detail herein. Each element (except for those at the edges of the sub-array) is connected to its four nearest neighbours in the north, east, south and west directions, to allow data to be transferred between them. The direction of transfer between the elements is governed by a routing code which is broadcast to all the elements in parallel.The routing code consists of two bits, the significance of which is as follows: Routing code Direction 00 North 01 East 10 South 11 West Referring to Figure 3, each element P contains a processing element 28 and a multiplexer 20 having four inputs 0, 1, 2, 3 connected to receive data from the four neighbouring elements in the south, west, north and east directions respectively. The multiplexer 20 is controlled by the routing code on line 30 so that it selects one of its four inputs in accordance with the binary value of the code and outputs data to the processing element 28. For example, if the routing code is 00, input 0 is selected, so that each element accepts data from its southern neighbour. As a result, data flows northwards.

The processing element 28 outputs data on connection 32 to one of the inputs of each of its neighbouring elements. Where connections carry signals in both directions a gate is included between each bi-directional connection and the output of the processing element. Such a gate is shown, by way of example, at 34 in the output to an east direction connection. This gate is controlled by the route code signals on line 36 such that it is active only for shifting of data in an easterly direction.

Generally, the connections between elements Pin a module 10 may be provided by two single direction connections in which case gates 34 are not provided in these connections between elements P. If bi-directional connections are provided between the elements P, gates 34 are provided in each output from the processing element. Connections between the modules 10 are bi-directional and hence gates 34 are provided between the outputs of the elements P at the edges of the module and the terminals 12, 14 and 16 connecting to the bi-directional inter-module connections 18.

Referring back to Figure 2, the four elements P on the eastern edge of the sub-array are respectively connected to the terminals 16, while those on the southern edge are respectively connected to the terminals 14. The terminals on the northern and western edges of the sub-array are both respectively connected, by way of a group of four two-way switches 22, to the terminals 12.

The switches 22 have two states, controlled by the second bit of the routing code. When the routing code represents north or south (i.e. the second bit = 0), the switches connect the terminals 12 to the northern edge of the sub-array. Conversely, when the routing code represents east or west (second bit = 1) the switches connect the terminals 12 to the western edge.

Although the switches 22 are shown symbolically as mechanical switches, in practice they are electronic switches constructed in a conventional manner from known logic components.

Thus, for example, when the routing code is 00 (representing "north"), data is shifted from each element to its northern neighbour within the same sub-array. Moreover, data is shifted from the elements in the northern edge of each sub-array, through the switches 22, the terminals 12 and the branched paths 18, to the terminals 14 on the neighbouring module in the northern direction. The multiplexers 20 in the elements on the southern edge of the neighbouring module will be set to accept this data.

It will be seen that the set of terminals 12 is effectively shared between the four elements on the north edge of the sub-array and the four elements on the west edge. This reduces the number of terminals required for connection to adjacent modules from sixteen to twelve. This sharing of terminals necessitates branched connections 18 between the modules, such that each branched connection joins together three terminals on different modules. However, there is no ambiguity about the direction in which data is required to flow, since at any given time only one of the three terminals is transmitting data, and only one is accepting data.

In the system described above, each of the modules 10 is an LSl chip. In an alternative arrangement, however, each module may consist of a printed circuit board with integrated circuit components, forming the processing elements P and switches 22, mounted on it. In this case, the processing elements P may be implemented in the manner described in the published patent specification No. 2020457 referred to above, in which four processing elements are incorporated into a single LSl chip.

Figure 4 shows a module containing four chips 24 of this type. As shown, each chip has six terminals instead of the eight which would normally be required from such a chip. This is achieved by combining the function of two terminals into a single north-west pin NW, and similarly combining the functions of two other terminals into a single south-west pin SW. The manner in which this is done is described in greater detail in the specification referred to above.

The module also has a set of four switches 26 equivalent in function to the switches 22 in Figure 2, although in this case the switches 26 consist of separate components mounted on the printed circuit board whereas in Figure 2 the switches were incorporated on the same chip as the processing elements.

The connections between the processing elements and between the switches 26 and the edges of the sub-array of processing elements are equivalent to those in Figure 2. It should be noted that the NW pin of the north-west chip is connected to two different switches 26, since this pin is a shared one, and therefore acts both as a terminal on the norther edge of the sub-array and also as a terminal on the western edge.

Claims

1. A data processing system module comprising an array of n x n processing elements, each processing element being connected to neighbouring elements in the array in which external connections to at least two of the elements on one edge of the array share common external terminals with an equal number of elements on an adjacent edge of the array.

2. A data processing system comprising a plurality of processing elements connected together in a rectangular array such that each element is operable to transfer data to its neighbouring elements, the array being sub-divided into a plurality of modules each of which contains an n x n sub-array of processing elements, wherein within each module the connections to at least two of the elements on one edge of the sub-array share common external terminals with an equal number of elements on an adjacent edge of the sub-array and wherein each shared terminal is connected externally of the module to two unshared terminals on respective adjacent modules.

3. A data processing system as claimed in claim 2 in which the shared external terminals are connected by means of switches to the processing elements on adjacent edges of the sub-array and the switches are operable to provide a path for data selectively to the elements on one edge and the elements on the adjacent edge.

4. A data processing system as claimed in claim 3 in which the processing elements and the switches are implemented in an integrated circuit.

5. A data processing system as claimed in claim 2,3, or 4 in which each processing element includes means operable to select a data input from a selected one of the neighbouring elements.

6. A data processing system as claimed in claim 2, 3,4, or 5 in which connections between processing elements are effective to transmit data in either direction and gating means are provided operable to permit transmission of data in one selected direction only.

7. A data processing system module constructed and arranged to operate substantially as hereinbefore described with reference to Figure 2 or Figures 2 and 3 or Figure 4 of the accompanying drawings.

8. A data processing system constructed and arranged to operate substantially as hereinbefore described with reference to Figures 1 and 2 or Figures 1,2 and 3 or Figures 1 and 4 of the accompanying drawings.