GB2243452A - Binary signal bit rate recognition system - Google Patents

Abstract

A system for determining the bit rate of an incoming binary signal (A) from a plurality of possible values of the bit rate operates by determining (3-17) in which of a plurality of time ranges the bit period of each pair of successive bits of like value lies. A count is made (19-35) for each time range and the bit rate deduced (37-49) from the counts for a particular input signal. <IMAGE>

Description

-1.0 Binary signal bit rate recognition system This invention relates to

binary signal bit rate recognition systems.

More particularly the invention relates to systems for determining the bit rate of an incoming binary signal from a plurality of possible values of the bit rate.

Such a function is difficult to achieve using circuits tuned to the different bit rates because the statistical nature of binary signals means that there is no well defined power peak which can be recognised.

Equally this function is difficult to achieve simply by attempting measurement of the minimum bit rate of the incoming signal since noise impulses are likely to give a too low measuremnt.

It is an object of the present invention to provide a bit rate recognition system which operates according to a strategy which overcomes these difficulties.

According to the present invention a system for determining the bit rate of an incoming binary signal from a plurality of possible values of said bit rate comprises: means for determining, in respect of each of a number of pairs of successive bits of like value of the incoming signal, the one of a plurality of time ranges in which the bit period of that pair of successive bits lies, which time ranges have extents such that the minimum possible bit period of signals of each said possible bit rate lies in a different time range; means responsive to the output of said determining means for summing in respect of each said time range the number of times during said number of pairs of successive bits the bit period of a said pair of successive bits lies in that time range; and means for utilising the outputs of said summing means to indicate which of said possible bit rates is the highest which lies in a time range for which said number of times exceeds a predetermined fraction of said number of pairs of successive bits.

In a system according to the invention said means for determining suitably comprises: means for initiating, in response to the first bit of each said pair of successive bits of like value, the generation of pulses of duration equal to respective limits of said time ranges; detection means responsive to the occurrence of the second bit of each said pair of bits to detect which, if any, of said pulses still exist; and decoding means responsive to the output of the detection means to indicate for each said second bit the time range in which the bit period of the pair of successive bits to which that second bit belongs lies.

In such a system said time ranges suitably together cover a continuous time span without overlap and each said pulse has a duration equal to the common limit of a different pair of time ranges which are adjacent in the time span.

Suitably said means for summing comprises a plurality of counters. one for summing in respect of each said time range, and each having a full count equal to said predetermined fraction of said number of pair of successive bits, and said means for utilising comprises a plurality of latch means each arranged for operation if a different one of said counters has overflowed after receipt of said number of pairs of successive bits unless a counter for a time range in which the minimum bit period of a higher possible bit rate lies has also overflowed.

One system for determining bit rate in accordance with the invention will now be described, by way of example, with reference to the acompanying drawings in which:- Figure 1 is a block schematic diagram of the system; and Figure 2 illustrates the waveforms appearing at various points in the system in operation.

The system determines the bit rate of an incoming signal from four possible values. The incoming signal (see Fig 2A) is of the kind in which a bit of value 'T' is represented by a pulse extending over a part only of a bit period e.g the first half only, and a bit of value "0" by the absence of a pulse in a bit period.

Referring to Figure 1, the incoming signal is applied to one input of an AND gate 1 whose output initiates operation of a first pulse generator 3. The output of the pulse generator 3 in turn initiates operation of a second pulse generator 5 whose output is used to clock a D-type flip-flop 7 configured so as to operate as a divide-by-two circuit. The output of the flip-flop 7 is applied to one input of a two-input AND gate 9 whose other input is derived from the output of the first pulse generator 3. The output of flip-flop 7 is also utilised to control operation of three further pulse generators 11, 13 and 15. The outputs of the pulse generators 11, 13 and 15 are fed to a decoder 17 which detects whether pulses are still present at the outputs of pulse generators 11, 13, 15 and when enabled by a pulse from the output of AND gate 9, supplies a pulse to an input of an appropriate one of four two-input AND gates 19, 21, 23 and 25 in dependence on which of the pulses applied to its input are still present, as further described below.

The pulses at the output of AND gate 9 are also counted in a main counter 27 whose output is fed to the second input of the AND gate 1.

The outputs of AND gates 19, 21, 23, 25 are respectively fed to the inputs of four counters 29, 31, 33, 35, having equal full counts which are a small fraction of the full count of counter 27. The outputs of the counters 29, 31, 33, 35 are utilised by a decoding arrangement comprising three AND gates 37, 39, 41 and four latching circuits 43, 45, 47, 49 so that when a pulse appears at the output of counter 27 indicating overflow of the counter 27, information regarding bit rate represented by the relative counts in the counters 29, 31, 33, 35 can be latched.

The second inputs of the AND gates 19, 21, 23, 25 are supplied from the outputs of the counters 29, 31, 33 and 35 respectively so that each AND gate 19, 21, 23 or 25 is disabled when the associated counter 29, 31, 33 or 35 overflows.

In operation the system is first reset by application of a reset pulse to flip-flop 7, counters 7, 29, 31, 33, 35 and latching circuits 43, 45, 47, 49. At the leading edge of the first pulse, i.e value 'T' bit, in the incoming signal (See Figure 2A) after reset, the pulse generator 3 generates a pulse of short duration compared with the minimum possible bit period in a signal of the highest of the four possible bit rates (See Figure 2B). By way of example the four possible bit rates are taken to be 704 kbits/sec, 1544 kbits/sec, 2048 kbits/sec and 3152 kbits/sec, in which case the pulse generator 3 suitably produces a pulse of duration 30ns.

In response to an output pulse from the pulse generator 3 the pulse generator 5 produces a pulse of the similar duration (See Figure 2C) which initiates generation of a pulse by flip-flop 7 (See Figure 2D). The initiation of a pulse by flip-flop 7 enables AND gate 9 and initiates the generation of a pulse by each of the pulse generators 11, 13 and 15 (See Figures 2E, 2F and 2G).

The durations of the pulses produced by generators 11, 13 and 15 are chosen in relation to the minimum possible bit periods of signals of the possible bit rates so as to define four time ranges which together cover a continuous time span, without overlap, in each of which four ranges there lies the minimum possible bit period ofa different one of the four possible bit rates.

Thus the generators 11, 13 and 15 suitably produce pulses of duration of 440ns, 600ns and 1.36,et-s respectively, the minimum possible bit periods of signals of bit rate 3152 kbits/s, 2048 kbits/s, 1544 kbit/s and 704 kbits/s being 317 ns, 488 ns, 648 ns and 1 1 1.42,z,s respectively. Thus the minimum possible bit periods lie respectively in the four ranges 0 440ns, 440 - 600 ns, 600A9- 1.36.ú,.s and 1.36,As -oos, the pulses produced by generators 11, 13 and 15 defining the common limits of adjacent ones of the time ranges in the time span.

The leading edge of the next pulse (value 'T' bit) in the incoming signal following initiation of the generation of pulses by generators 11, 13 and 15 (i.e. second pulse after reset) causes generation of a further pulse by generator 3, which further pulse, since AND gate 9 is now enabled, increments counter 27 and enables decoder 17. When enabled the decoder 17 applies a pulse to AND gate 19 if the pulses produced by all three generators 11, 13 and 15 still exist, to AND gate 21 if only the pulses produced by generators 13 and 15 still exist, to AND gate 23 if only the pulse produced by generator 15 still exists, and to AND gate 25 if none of the pulses still exists. Thus a pulse is applied to AND gate 19, 21, 23 or 25 according to whether the time between the leading edges of the first and second pulses of the incoming signal, i.e. the bit period of those two pulses, is in the time range including the minimum possible bit period of signals of bit rate 3152 kbits/s, 2048 kbits/s, 1544 kbits/s or 704 kbits/s. Hence each of the AND gates 19, 21, 23, 25 and each of the counters 19, 21, 23 and 25 relates to a different time range and hence to a different one of the four possible bit rates.

The counters 29, 31, 33 and 35 are each incremented by one when a pulse is applied to the associated AND gate 19, 21, 23 or 25 until the counter overflows, thereby disabling the associated AND gate. Thus, for the first pair of successive pulses of the incoming signal, one or other of the counters 29, 31, 33, 35 is incremented by one when the decoder 17 is enabled depending on which pulses produced by the generators 11, 13 and 15 still exist according to the following table, where 'T' indicates that a pulse still exists.

Counter Pulse of Pulse of Pulse of Related bit incremented generator 11 generator 13 _generator 15 rate (kbits/s) 29 1 1 1 3152 31 0 1 1 2048 33 0 0 1 1544 0 0 0 704 The pulse produced by generator 3 in response to the leading edge of the second pulse in the incoming signal after reset also causes generation of a further pulse by generator 5 which terminates the pulse generated by flip-flop 7 in response to the first pulse produced by generator 5. The termination of the flip-flop pulse terminates the pulses produced by generators 11, 13 and 15, if still existing, and also disables AND gate 9.

The above sequence of operations leading to increment of one or other of the counters 29, 31, 33, 35 (unless it has already overflowed) is repeated for each pair of successive pulses in the incoming signal until the counter 27 overflows when its output disables AND gate 1.

Figure 2A shows an incoming signal waveform which might be encountered with an incoming signal of bit rate 2048 kbits/s. The table below indicates which pulses of pulse generators 11, 13 and 15 still exist when the decoder 17 is enabled at times tl, t2 and t3 (see Figure 2) and hence which of the counters 29, 31, 33, 35 is incremented at each such time.

1 Pulse of Pul se of Pul se of Counter time generator 11 generator 13, generator 15 incremented ti 0 1 1 31 t2 0 0 1 33 U 0 1 1 31 For the four possible bit rates considered by way of example the counters 29, 31, 33, 35 suitably each have a full count of 8 and the counter 17 a relatively large full count, e.g. 2048. For an incoming signal of bit rate 2048 kbits/s, when the counter 27 overflows the counter 31, is virtually certain to have overflowed due to the occurrence of at least nine pairs of successive pulses at a spacing of 1 bit period during the full count of counter 27. In addition, due to the occurrence of successive pulses at spacings of two or more bit periods during the full count of counter 27, counters 31 and 35 are both very likely to have overflowed. However, the counter 29 will be empty since the minimum possible time between pulses in the incoming signal is too long for the pulses produced by generator 11 to exist when the decoder 17 is enabled.

Thus the bit rate of the incoming signal is indicated by which ones of the counters 29, 31, 33, 35 have overflowed, as follows. If only counter 35 has overflowed the bit rate is 704 kbits/s; if counter 33 has overflowed but not counter 29 or 31 the bit rate is 1544 kbits/s; if counter 31 has overflowed but not counter 29 the bit rate is 2048 kbits/s and if counter 29 has overflowed the bit rate is 3152 kbits/s.

This information is decoded by AND gates 37, 39, 41 and latched in one of the latching circuits 43, 45, 47, 49 when. the counter 27 overflows, as follows.

As previously mentioned, each of the counters 29, 31, 33, when' it overflows disables the AND gate 19, 21, 23 or 25 at its input. In addition, the counter 29 when it overflows disables all the decoder AND gates 37, 39, 41, the counter 31 when it overflows disables the AND gates 39 and 41 only and the counter 33 when it overflows disables the AND gate 41 only. The latching circuit 43 is operated by a pulse at the output of counter 29 when it overflows. The latching circuits 45, 47 and 49 are operated by pulses at the outputs of counters 31, 33 and 35 respectively, when they overflow, via AND gates 37, 39 and 41 respectively unless these gates are disabled. Hence the AND gates 37, 39, 41 prevent operation of a latching circuit 45, 47 or 49 by overflow of the corresponding counter 31, 33 or 35 if a counter relating to a higher possible bit rate has also overflowed. Thus, when enabled by overflow of counter 27, only that one of the latching circuits 43, 45, 47, 49 which corresponds to the fastest bit rate related counter 29, 31, 33 or 35 which has overflowed will latch.

Thus the incoming signal bit rate is indicated by which of the latching circuits 43, 45, 47, 49 latches, the latching circuits being each related to a different possible bit rate in corresponding manner to the counters 29, 31, 33 and 35.

It will be understood that the full count of the counters 29, 31, 33, 35 is chosen to be a sufficiently large fraction of the full count of the counter 27 to ensure that short period noise impulses will not cause overflow of a counter relating to a bit rate faster than that of the true bit rate of the incoming signal before the counter 27 overflows. At the same time the full count of the counters 29, 31, 33, 35 is chosen to be a sufficiently small fraction of the full count of the counter 27 to ensure that the counter 29, 31, 33 or 35 relating to the bit rate of the incoming signal overflows before the counter 27 overflows.

The full count of the counter 27 is, of course, chosen with a view to keeping to a minimum the time before one of the latching circuits 43, 45, 47, 49 latches to indicate the incoming signal bit rate.

-g- It will be understood that if an incoming signal of very unusual format is received which contains less than nine successive pulses at a spacing of one bit period in 2049 successive pairs of pulses, the system will give an incorrect indication of bit rate. A new determination can of course then be initiated by reset.

Whilst in the system described above by way of example the pulse generators 3, 5, 11, 13 and 15 may comprise monostable circuits, it will be appreciated that the functions of these generators are more suitably effected digitally, e.g. using a high frequency clock and frequency counters.

In the case of the four bits rates mentioned by way of example it will be noted that these bit rates have a lowest common multiple of 25 MHz + 1.5% and are approximately in the ratio 8:12:16:36. Hence a frequency source of about 25 MHz in a narrow timing range phase-locked loop and appropriate frequency dividers may conveniently be used to generate both the pulses required for bit rate recognition and clock signals of the required frequencies for extracting data from incoming signals of the different bit rates. Alternatively a digital injection locked system with frequency division could be used.

Claims (10)

1. A system for determining the bit rate of an incoming binary signal from a plurality of possible values of said bit rate comprising: means for determining, in respect of each of a number of pairs of successive bits of like value of the incoming signal, the one of a plurality of time ranges in which the bit period of that pair of successive bits lies, which time ranges have extents such that the minimum possible bit period of signals of each said possible bit rate lies in a different time range; means responsive to the output of said determining means for summing in respect of each said time range the number of times during said number of pairs of successive bits the bit period of a said pair of successive bits lies in that time range; and means for utilising the outputs of said summing means to indicate which of said possible bit rates is the highest which lies in a time range for which said number of times exceeds a predetermined fraction of said number of pairs of successive bits.

2. A system according to Claim 1 wherein said means for determining comprises: means for initiating, in response to the first bit of each said pair of successive bits of like value, the generation of pulses of duration equal to respective limits of said time ranges; detection means responsive to the occurrence of the second bit of each said pair of bits to detect which, if any, of said pulses still exist; and decoding means responsive to the output of the detection means to indicate for each said second bit the time range in which the bit period of the pair of successive bits to which that second bit belongs lies.

3. A system according to Claim 2 wherein said time ranges together cover a continuous time span without overlap and each said pulse has a duration equal to the common limit of a different pair of time ranges which are adjacent in the time span.

4. A system according to Claim 3 wherein said means for initiating comprises: a first pulse generator for producin.g, in response to each pulse in the incoming signal, a pulse of relatively short duration, a second pulse generator for producing in response to each pulse produced by said first pulse generator a pulse of similar duration to the pulse produced by said first pulse generator; a divide by two circuit responsive to the output of said second pulse generator, and further pulse generators each of which is enabled for generation of a said pulse of duration equal to a respective said common limit during production of a pulse by said divide by two circuit.

5. A system according to any one of the preceding claims wherein said means for summing comprises a plurality of counters, one for sunning in respect of each said time range, and each having a full count equal to said predetermined fraction of said number of pairs of successive bits, and said means for utilising comprises a plurality of latch means each arranged for operation if a different one of said counters has overflowed after receipt of said number of pairs of successive bits unless a counter for a time range in which the minimum bit period of a higher possible bit rate lies also overflowed.

6. A system according to Claim 5 wherein said latch means is operated from the outputs of said counters via an AND gate decoding arrangement.

7. A system according to Claim 5 or Claim 6 wherein each said counter is incremented by pulses supplied by said means for determining via a respective AND gate which is disabled when the corresponding counter overflows.

8. A system according to any one of the preceding claims including a main counter having a full count equal to said number of pairs of successive bits and arranged to increment by one in response to the second bit of each said pair of successive bits, and said means for utilising is arranged to be enabled when said main counter overflows.

9. A system according to Claim 8 when dependent on Claim 4 wherein said main counter receives input pulses from said second pulse generator via an AND gate which is enabled only when said divide by two circuit is producing a pulse.

10. A system for determining the bit rate of an incoming signal from a plurality of possi ble values of said bit rate substantially as hereinbefore described with reference to the accompanying drawings.

Published 1991 at The Patent Office, Concept House, Cardiff Road. Newport. Gwent NP9 lRH- Further copies may be obtained from Sales Branch. Unit 6. Nine Mile Point, Cwrnfelinfach. Cross Keys, NewporL NP I 7HZ. Printed by Multiplex techniques lid, St Mary Cray. Kent.