GB2159377A - Data transmission system - Google Patents

Abstract

A data transmission system for distributing data signals from a head end 1 to a terminal 2 of the system. An AC signal of fixed frequency is generated 10 at the head end and abrupt changes in amplitude, or notches, are induced 11 in individual cycles of the AC signal, a notch in the first half cycle representing binary "1" and a notch in the second half cycle representing binary "0". The notched AC signal is transmitted to the terminals and the notches are detected 13 to reconstitute the data signal represented by the notches. The AC signal is broken up into a series of bursts separated by DC levels and each terminal is responsive to only the AC burst following a particular DC level. <IMAGE>

Description

SPECIFICATION Data transmission system The present invention relates to a data transmission system, and in particularto a data transmission system suitablefortransmitting data from the head end of a wired broadcasting system to terminals connected to the system.

Wired broadcasting systems intended primarily for the distribution oftelevision signals are well known, the television signals being transmitted overconductive cables and/or optic fibres. It is highly desirable for such systems to be capable oftransmitting data in both directions between the head end and terminals of the system and various proposals have been made to achieve this end. One such system is described in European Patent Specification No. 0 094 794. It is also highly desirable forterminals of the system to be powered via the system, thereby avoiding having to connect each terminal to a power supply within a subscribers premises.

British Patent Specification No.1554411 describes a system in which power is delivered to terminals by an A.C. signal transmitted from the head end. To avoid the needforseparate power and downstream (head end to terminal) data signals in the system ofthe above British Patent Specification, the power signal is also used to carry downstream binary data signals.

This is achieved by switching the frequency of the powersignal, a complete cycle ofonefrequency representing a binary "0" and a complete cycle of a second frequency representing a binary "1". This system works satisfactorily but, in addition to requiring frequency switching circuits, has the disadvantage that data intended for a particularterminal hasto have associated with it an address code identifying that terminal. This considerably increases the volume of data transmitted.

It is an object ofthe present invention to provide an improved data transmission system.

According to the present invention, there is provided a data transmission system for distributing data signals from a head end to a plurality ofterminals of the system, comprising means atthe head end for generating a composite power and data transmission signal in the form of a series of bursts of AC signal separated by DC signals, each DC signal being allocated one of at leasttwo DC levels which occur in the composite signal in a predetermined order, means for generating binary data signals to be transmitted serially to the terminals, means for modulating the AC components ofthe composite signal in dependence upon the data signals such that individual half cycles ofthe AC signal waveform contain an abrupt change in amplitude the duration of which is substantially less than the duration of a half cycle of the AC signal waveform, each abrupt change in amplitude corresponding to one bit of a binary data signal the logic state of which bit is indicated by the half cycle ofthe AC signal waveform within which the abrupt change in amplitude occurs, means at each terminal for detecting a respective one ofthe DC levels, means at each terminal for detecting only those abrupt changes in amplitude appearing in theAC signal waveform within a predetermined period following detection of the said one DC level, and means for regenerating the binary data signal from the detected abrupt changes in amplitude.

Preferably, the AC signal has a square waveform and the abrupt changes in amplitude are in the form of inverted sine squared pulses.

Preferably, the modulated AC signal contains abrupt changes in amplitude representative of both "0" and "1 " bits ofthe binarysignal, the abrupt changes in amplitude being positioned in one or other half cycle in dependence upon whether the bit corresponds to a "0" or "1" ofthe binary signal, and the regenerating means comprises means for determing the position of each abrupt change in amplitude in the cycle ofthe AC signal in which it occurs to determine whether it is representative of a "0" or "1".

The AC signal transmitted to terminals can be used to powertheterminals as well asto convey data.

An embodiment ofthe present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. lisa schematic illustration of the basic components of an embodiment ofthe invention; Fig. 2 is a circuit diagram of a decoder ofthe system of Fig. 1; Fig. 3 illustrates waveforms appearing in the circuit of Fig. 2; and Figs. 4 and 5 illustrate the structure and operation of a notch generator.

The described embodiment of the invention is intended for integration into the broadcating system described into the above-mentioned European Patent Specification No.0094 794 to which reference must be made to fully appreciate the operation of the described embodiment and in particularthe way in which signals are generated and routed between the head end and individual subscriberterminals via switching centres or exchanges. The above-mentioned European Specification refers to the transmission of data signals to subscriber terminals by frequency modulating a composite power and data signaltransmittedtotheterminalsfrom switching centres, the data signals including an address code unique to a particularterminal and a message code representing the data to be delivered to thatterminal.

The embodiment of the invention described below provides an alternative way of modulating the composite power and data signal to deliver data to selected terminals.

Referring to Fig. 1,the drawing illustrates a head end 1 and three terminals 2. All three terminals may be located within one subscribers premises. In practice, components shown in the head end 1 will be distributed between the head end proper and switching centres (not shown) and each switching centre will serve many more than three terminals but the simplified illustrated arrangement will serve to explain the way in which a full system would operate.

The head end 1 comprises a timing circuit 3 which synchronisestheoperation of all other components of the system so as to be able to direct signals to individual terminals and to identify the source of data signals coming from the terminals. The terminals are connected to the head end by a single coaxial cable 4.

Programme selection signals and data signals from theterminals connected to the common cable 4 are generated by manipulation of keyboards 5 and allocated to respective time slots. Programme selection signals are applied to a circuit 6 which controls a switching matrix 7 to distribute selected signals received from sources 8 to terminal receivers 9.

Thetiming circuit3 controls a power signal generator 10 which produces a 15.625kHz AC square wave power signal in the form of 24ms bursts separated by 2.6ms DC signals, the DC signals beingatOv,6v,12v, Ov, 6v, 12v and soon so that each burstfollows a DC signal of either Ov, 6v, or 12v. This signal is applied to a notching circuit 11 which modulatesthe AC signals such that abrupt amplitude changes in the form of brief reductions in amplitude occur in eithertherfirst orsecond halves of individual cycles, a notch in the first half cycle representing binary "1", and in the second half cycle "O". These abrupt amplitude changes are referred to hereinafter as "notches", each notch representing one bitofa binary data signal provided by data signal generator 12.The notched power signal is transmitted to the terminals via cable 4.

The notches are in the form of sine squared pulses.

Such pulses have a low harmonic content and this minimises any interference which the data signals might cause to other signals on the network at higher frequencies, such asthetelevision signals. In addition, because the sine squared signals have a width which is narrow relative to their peak amplitude they do not detract more than a small percentage ofthe power content of the powerwaveform whilst their relatively high peak amplitude improves the signal-to-noise ratio ofthe data signals atthe subscriberterminals.

Each terminal is provided with a decoder 13, each decoder being responsive to a respective one ofthe three 24ms notched AC bursts identified by the DC signals preceding each burst. Fig. 2 is a circuit diagram ofthat one ofthe decoders 13 which is responsive to the burstfollowing the Ov DC signal.

Referring to Figs 2 and 3, the notched AC power signal is applied to input 14, the power signal being shown in waveform 14 of Fig. 3. A DC power supply (not shown) rectifies the AC signals to derive a 1 2v DC supply for all functions oftheterminal. A square wave pulse appears on line 15 (waveform 15 of Fig. 3) and is applied to one of a pairof gates 16 and also causes a positive pulse to be applied to gate 17. ADCdetector 18 applies a pulse to line 19 onlywhen the0v DC signal appears at input 14, this pulse (waveform 19) being applied to the other input of gate 17.A circuit of the type required to act as the DC detector 18 is described with reference to Fig. 3 ofthe abovementioned European Patent Specification No.0094794. The input to the DC detector includes a series resistor and shunt capacitor which acts as a low pass filter two attenuate the AC powerwaveform whilst passing the Ov, 6v and 12v DC signals. The output 20 of gate 16 (waveform 20) is a pulse the duration of which is equal to the duration ofthe AC burst in the power signal immediatelyfollowing the Ov DC signal.The waveform 20 controls a gate 21 the other input of which receives the AC power signal such that the gate output 22 is a square wave correspondina to the burst of AC signals following the Ov DC signal. The output is shown as waveform 22A with its firstfou r cycles being shown intheexpandedwaveform22B. Twill be seen thatthewaveform 22B includesthe notchesapplied to the power signal at the head end. The waveform 22B is applied via a resistor/capacitorfilter network 23 to inverters 24 and 25 to remove the notch waveform.

Waveform 26 appears via line 26 and is applied to a gate 27 which also receives the output of amplifier 28.

Amplifier 28 receives the notches power signal via line 29 and a DC level derived via a potentiometer from a 12v line 30 energised by the power signal which determines the threshold level for detecting "1" notch signals. Thefourcycles shown as waveform 22B representthe binary data 1001. Itwill be seen that binary "1" is represented by a notch in the first half of a complete cycle whereas a binary "0" is represented by a notch in the second half of a complete cycle. The spacing between adjacent notches is thus a function of the data represented. This of course corresponds to the simple modulation technique implemented in the notching circuitatthe head end. The width of each notch is a maximum of 10.6 microseconds, the waveform 22B having a frequency of 15.625kHz and a pulse rate of 64 microseconds.

The output 31 of gate 27 is shown by waveform 31 and is decoded "1's. Waveform 32 appears on line 32 and is applied to a gate 33 fed by amplifier 34 which detects "O"s. The output 35 of gate 33 is shown by waveform 35 and is decoded "O"s. The filter network 23 introduces a delay between the start of a cycle of thepowers.gnalandthepulseofwaveform26which delay can be seen from waveform 26. Resistor/diode networks 36 determine the width ofthe pulses in waveforms 26 and 32.

The waveform 26 is the gate waveform for data "1" signals, and the waveform 32 is the gate waveform for data "0" signals. Waveforms 31 and 35 correspond to data '1" and "0" respectively. The waveforms 31 and 35 are applied to a gate network 37 to provide clock waveform 38 on line 38. This clocks a shift register 39 to provide parallel data on outputs 40. The data outputs 40 deliverthe downstream data the terminal and the data may be displayed via the terminal receiver to be read by the subscriber or may be used to control functions of the terminal, e.g. to prevent selection of certain programmes.

It will be appreciated from the above that Ov, 6v and 1 2v DC signals in the powwerwaveform are used to direct data to respective ones of the three terminals fed from the common cable 4 (Fig. 1), each terminal having a DC detector 18 responsive to a respective one of the three DC levels. This means that onlythree terminals can be selectively addressed. If it is desired to address more than three terminals, the DC detector 18 could be arranged to include a counter.Each detector in a group to be addressed bythe power signal transmission following immediately upon a particular DC level can bearrangedto respondonlyto data contained in a portion oftheAC brusts of the power signal specific to that detector by counting cycles ofthe power waveform and enabling the detectoronlysolong as the cycle count is between predetermined counts. For example, twelve detectors could be individually addressed by one 24ms burst which contains 375 data cells by allocating to each decoderthirtyofthe data cells.Afirstterminal detector would be allocated the first thirty cells, a second detector the second thirty cells, and soon. This increases the capacity ofthe system to distinguish between terminals.The counters are thus used to address particularterminals in addition to the 0,6 and 12 DC levels to give in the above example an address capacity ofthirtysix.

The notched power signal can be generated by a variety of circuits, part of one such circuit being shown in Fig. 4. Fig. 5 illustrates waveforms appearing in the circuit of Fig. 4.

Referring to Figs. 4 and 5, in the illustrated notch generatorthree fixed frequency signals offrequencies 93.75kHz, 46.875kHz and 15.625kHz are applied to inputs 41,42 and 43 respectivelyfrom a divider network (not shown). The "1" and "0" notches are gated into the power waveform appearing at output 44 buy a CNOS switch 45. Data is held on a FIFO board (not shown) and is released to the notch generator on receipt of a signal at input 46 from the FIFO board. The data is applied serially to input47 and is clocked for notch transmission at a serial rate locked to the 15.625kHz power waveform.Transmission of 32k bytes held bythe FIFO board and loaded by a microprocessor (not shown) is initiated following the termination of the polling signal applied to input 48 and a count offour pulses of power waveform in counter 49. The serial data clock applied to the FIFO board appears at terminal 50. The four pulse delay is included to prevent transient overshoot voltages which follow the DC level waveform from being misinterpreted as data "1" or"0" bythe decoders.

Resistors 51 to 55 determine the amplitude of the depth of notch modulation at switch 45 which in practice is about one third of the peaksquarewave power signal.

Fig. 5 shows waveforms A to E which respectively represent the 93.75kHz signal, the 46.875kHz signal, the 15.625kHz signal, the "1" gate signal (A; B and C) and the "0" gate signal (A, B and C).

It should be noted thatthe low pass filters 23 of Fig. 2 remove the notch modulation from the power wave form thus permitting the synchronising of the gate waveforms correctlywith the delayed transition ofthe waveform from positive to negative. In effectthe filters extract the basic square wave power waveform to provide a clockforextracting notch pulses from the composite power waveform. The use of a square wave power waveform enables an accurately timed clock signal to be derived directly from it in a simple manner. The generation of a clock signal from a sinusoidal waveform is more complex and thus less economic. This clockshould not be confused with the clock generated from the "1" and "0" signals which only appears during data transmission and ensures that data is loaded correctly in the shift register 39.

In the described embodiments notches representing both "0"and "1" bits are transmitted. Itwould be possibleto omitforexamplethe "0" signals but if this is done it is necessaryto transmit a burst of "1" signals to synchronize a clock generator before starting data transmission and either count power waveform pulses or send an "end of message" code afterdata transmission to define the message length. Thetime lost transmitting a burst of "1 "s for synchronising purposes reduces the amount of data which can be handled in a given interval.

Claims (7)

1. A data transmission system for distributing data signals from a head end to a plurality of terminals of the system, comprising means at the head end for generating a composite power and data transmission signal in the form of a series of bursts ofACsignal separated by DC signals, each DC signal being allocated one of at leasttwo DC levels which occur in the composite signal in a predetermined order, means for generating binary data signals to be transmitted serially to the terminals, means for modulating the AC components of the composite signal in dependence upon the data signals such that individual half cycles ofthe AC signal waveform contain an abrupt change in amplitude the duration of which is substantially less than the duration of a half cycle ofthe AC signal waveform, each abrupt change in amplitude corresponding to one bit of a binary data signal the logic state ofwhich bit is indicated by the half cycle of the AC signal waveform within which the abrupt change in amplitude occurs, means at each terminal for detecting a respective one of the DC levels, means at each terminal for detecting onlythose abrupt changes in amplitude appearing in the AC signal waveform within a predetermined period following detection of the said one DC level, and means for regenerating the binary data signal from the detected abrupt changes in amplitude.

2. A data transmision system according to claim 1, wherein the AC signal is a square wave.

3. A data transmission system according to claim 1 or 2, wherein each abrupt change in amplitude is in the form of an inverted sine squared signal.

4. Adatatransmission system according to any preceding claim, wherein the modulated AC signal contains abrupt changes in amplitude representative of both "0" and "1" bits ofthe binarysignal,theabrupt changes in ampitude being positioned in one or other half cycle in dependence upon whetherthe bit corresponds to a "O" or"1" ofthe binary signal, and the regenerating means comprises means for determining the position of each abrupt change in amplitude in the cycle ofthe AC signal in which it occurs to determine whether it is representative of a "O" or "1".

5. A data transmission system according to any preceding claim, wherein each terminal comprises a power supply for deriving DC powerfrom the AC signal to energise the terminal.

6. A data transmission system according to any preceding claim, wherein each terminal comprises a counter for counting the number of cycles of the AC signal occurring afterthe detection of the said one DC level, and means controlled by the counter for selecting only data signals appearing within a predetermined group of cycles of the AC signal.

7. A data transmission system substantially as hereinbefore described with reference to the accompanying drawings.