GB2242290A - On-line format conversion - Google Patents

Abstract

Image processing apparatus (1, 2) produces an image document containing information to a first format and is connected by a link (7) to a second machine (8, 10) which operates to a second format. Apparatus (3) converts the information from the first format to the second format prior to transmission of the documents over the line (7) to the second machine. The apparatus (3) can also convert information sent in the reverse direction. <IMAGE>

Description

ON-LINE FORMAT CONVERSION This invention relates to image processing apparatus conversion.

Apparatus for converting information in one format to the same information in another format is well known. For example, in the field of word processing, it is well known to convert information about a document in one format to the same information in another format so that the information can be processed by a different machine. Similarly in the field of image processing, it is known that different types of image processors have different formats and format conversion has been known. It is normal to take image information (called in this specification a "document") prepared on one machine and to introduce it into a second machine which carries out a programme to convert the document to the format used in the second machine, that format being different from that to which the document was originally prepared in the first machine.The information is transported between the machines either physically by being encoded on a floppy disc or by standard electronic file transfer. Conversion of an image document by means of a programme can be extremely slow.

According to this invention, there is provided an image processing apparatus comprising a first machine which produces an image document containing information to a first format and connected by a link to a second machine which operates to a second format, the first machine including apparatus which converts the information from the format of the first machine to the format of the second machine prior to transmission of the document over the line to the second machine.

The information may be read out of the first machine and translated to the second format simultaneously by the said apparatus included in the first machine.

Various formats are known. The document, i.e. the image, is made up of a large number of pixels arranged in rows. In most formats the information relating to a pixel constitutes a single block of information. However, the format nevertheless can vary as for each pixel four items of information are required, i.e. yellow, magenta, cyan and black, usually denoted by YMCK transmitted in that order in some formats. However in some formats the order is CMYK.

In other formats, all the information relating to, say, Y of all the pixels in a single row is transmitted first, then all the information relating to say M, then say that relating to C and then that relating to say K.

Clearly the conversion could be carried out by a programmed computer but this can be very slow.

In a preferred embodiment of this invention the apparatus which converts the information from the format of the first machine to the format of the second machine comprises an input memory, a plurality of memory units, each capable of storing information about a particular aspect of a plurality of pixels of the image, a processor for controlling the transfer of information about a group of pixels from the input memory to a plurality of memory units, and an output circuit, the processor further serving to control the transfer of information from the memory units to the output circuit so that the information regarding the group of pixels reaches the output circuit in a format other than that of the information stored in the input memory.

Preferably the output circuit can receive information about an image from the second machine and passes that information to the first to fourth memory units in a sequence controlled by the processor, the processor being capable of controlling the transfer of information from the memory units to the input memory which then acts as an output memory, whereby the direction of translations is reversible.

Preferably, the apparatus comprises an address mapper to which the processor is connected and which is connected to the memory units the address mapper defining the memory unit and the position within the memory unit to which each item from the input memory should be transferred under the control of the processor and from which each item of information should be transferred from the memory unit to the output memory.

Preferably, there are four memory units for Y, M, C and K signals.

Preferably, the apparatus comprises a range mapper for receiving signals to be stored in the memory units and changing the magnitude of those signals in accordance with a stored lookup table.

This feature is required for certain format translations.

An exemplary embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings of which: An IBM computer 1 has connected to it firstly an image processor 2 and secondly a translation apparatus 3 which consists of a mother board 4 and a daughter board 5 on opposite sides of an imaginary divider line 6 shown in Figure 1.

The translation apparatus 3 is connected via the daughter board 5 and an electronic link 7 to a Siemens HELL computer 8 via an input buffer 9 of that computer 8. To the computer 8 there is connected a Combiscope 10 which is a high resolution image processing system.

The translation apparatus 3 shown in detail in Figure 2 serves to translate between the image format of the IBM computer 1 and the image format of the Siemens HELL computer 8.

Figure 2 shows the circuitry of both the mother board 4 and the daughter board 5. Although the description so far has assumed translation from the IBM format to the Siemens HELL format, the apparatus 3 is designed to be capable of translations between many different formats as will now be explained.

The translation apparatus 3 comprises a dual port buffer 11 which effectively constitutes an input memory connected to the sixteen bit IBM 80 bus 22, i.e. it receives the output signals of the computer 1 in 16 bit form.

The output of the dual port buffer 11 is connected via a bus 12 firstly to a processor 13 and secondly to four memory units 14, 15, 16 and 17 for Y, M, C and K signals. The memory unit 14, 15, 16 and 17 are denoted 1, 2, 3 and 4 as shown.

An address mapper 18 is connected to the output of the processor 13 is also connected to each of the memory units 14, 15, 16 and 17. The bus 12 is also connected to output link circuitry 19.

A range mapper 20 is connected to receive at its input the signals on the bus 12 and converts those signals under the control of the processor 13 on the basis of an internal look-up memory.

The processor itself is controlled by a controller 21 under the control signals derived from the input signals on the 16 bit IBM 80 bus 22.

Of the blocks shown in Figure 2, all apart from the link circuitry 19 are mounted on the mother board 4 while the link circuitry 19 is mounted on a daughter board 5.

In use, the signals on the 16 bit IBM 80 bus 22 are pixel multiplexed. The dual port buffer 11 receives four blocks of image data, i.e. four blocks of data each relating to a single pixel of the image on the basis of CMYK. These are written into the memory units 1, 2, 3 and 4 on the basis of CMYK and are read out into the link circuitry 19 on the basis of YMCK. Different address mapping is produced by address mapper 18 for read and write under the control of the processor 13 and in this way YMCK is converted to CMCK. In addition YMCK (or CMYK) could be read in in line sequential order, i.e. Y for each pixel of the line, M for each pixel of the line, C for each pixel of the line and K for each pixel of the line and read out in pixel order in CMYK or for that matter in YMCK.

The range mapper 20 provides for range conversion, i.e.

compression or expansion and it has an internal static RAM look-up table which can hold up to 64 conversion factors.

The translation which has so far been described is on the basis that the input format is received at the dual port buffer 11 and the output format is received at the link circuitry 19 but the direction of translation could readily be reversed in which case the memory units 14, 15, 16 and 17 not only perform the function described but also performs the function of an input memory. The dual port buffer 11 acts as an output memory and address mapper 18 and range mapper 20 acts as previously described under the control of the processor 13.

In the example which has been described, the conversion is from the format for IBM to the Siemens HELL format. The conversion can readily be from IBM to either IEEE 488 or SCSI or any other electronic link.

If conversion is required from YMCK to ROB a further circuit is required. For this purpose the outputs of the address mapper 18 and each of the memory units 14, 15, 16 and 17 are connected via appropriate outputs another daughter board only indicated in outline at 23.

Claims (7)

1. Image processing apparatus comprising a first machine which produces an image document containing information to a first format and connected by a link to a second machine which operates to a second format, the first machine including apparatus which converts the information from the format of the first machine to the format of the second machine prior to transmission of the document over the line to the second machine.

2. Image processing apparatus according to claim 1, wherein the apparatus which converts the information from the format of the first machine to the format of the second machine comprises an input memory, a plurality of memory units, each capable of storing information about a particular aspect of a plurality of pixels of the image, a processor for controlling the transfer of information about a group of pixels from the input memory to a plurality of memory units, and an output circuit, the processor further serving to control the transfer of information from the memory units to the output circuit so that the information regarding the group of pixels reaches the output circuit in a format other than that of the information stored in the input memory.

3. Image processing apparatus according to claim 2, wherein the output circuit can receive information about an image from the second machine and passes that information to the first to fourth memory units in a sequence controlled by the processor, the processor being capable of controlling the transfer of information from the memory units to the input memory which then acts as an output memory, whereby the direction of translations is reversible.

4. Image processing apparatus according to either claim 2 or claim 3, wherein the apparatus comprises an address mapper to which the processor is connected and which is connected to the memory units, the address mapper defining the memory unit and the position within the memory unit to which each item from the input memory should be transferred under the control of the processor and from which each item of information should be transferred from the memory unit to the output memory.

5. Image processing apparatus according to any of claims 2 to 4, wherein there are four memory units.

6. Image processing apparatus according to any of claims 2 to 5, wherein the apparatus comprises a range mapper for receiving signals to be stored in the memory units and changing the magnitude of those signals in accordance with a stored look-up table.

7. Image processing apparatus substantially as hereinbefore described with reference to the accompanying drawings.