GB2238899A - Device for teaching electronic logic circuit operation - Google Patents

Abstract

The device comprises at least two units having complimentary external connectors whereby they can be connected together either directly or via an intermediary, the logic circuits in the form of a solid state device being contained in the input unit only. The input unit may include a sensor, e.g. a push switch, photocell or heat sensor, or may be connected to a remote sensor. The input unit can be selectively coupled through other units (having for example AND, OR, NOT, PULSE or LATCH functions) to an output unit which includes an output device, e.g. a buzzer or light. Triggering of the input sensor(s) operates the output device in accordance with the selected logic function(s).

Description

EDUCATIONAL DEVICE This invention relates to an educational device and in particular relates to a device for teaching children the operation of logic circuits.

Teaching devices exist in the form of square units or "links" each of which contains a logic circuit and one or more external complementary connectors. By linking together two or more of these links a circuit could be built up which would result in a simple input (such as a push button switch) operating a simple output (such as a light or buzzer). More complex circuits could involve AND or OR circuits so that a child could visibly see the operation of such logic. Each of these links (other than the output link) contains a microchip containing four twoinput NAND gates. However, this is a relatively expensive way of constructing the links both in terms of component cost and of assembly.

The invention seeks to provide an improved and more economical way of providing unitised logic circuits for use in educating children.

According to the present invention there is provided an educational device which comprises at least two units having complementary external connectors whereby they can be connected together either directly or via an itermediary, characterised in that the logic circuits in the form of a solid state device are contained in the input device only.

By the invention a single quadruple NAND microchip may be employed in the input device which, with the circuitry to be described more fully hereinafter, will give the appearance of the other units having logic circuits within them.

The invention will be described further, by way of example, with reference to the accompanying drawing, in which: Figure 1 is a circuit diagram of an input device in accordance with the invention; Figure 2 is a circuit diagram of an output device in accordance with the invention; Figures 3a - e are cicuit diagrams of different forms of intermediate device in accordance with the invention; Figures 4a and b illustrate schematically the embodiment of Figures 1 to 3 and a second embodiment; Figure 5 is a circuit diagram of the second embodiment corresponding to Figure 1; Figure 6 is a diagrammatic illustration of a fourteen-way bus for use in the second embodiment; and Figure 7 (a) to (g) are circuit diagrams of different forms of unit for use with the second embodiment.

Referring to the drawings, an input device generally designated 10 is the in form of a generally square box like unit or "link" of, for example, two inches on each side and half an inch deep. The input link 10 will contain the circuitry illustrated in figure 1 and be provided with suitable edge connectors which can mate externally with a similar or complementary connector provided on other links to be described further hereinafter. The link 10 contains a quadruple NAND gate microchip and the four individual NAND gates are illustrated as 1,2,3 and 4 in figure 1. The input link 10 is provided with an internal sensor 12 which could be a simple push switch, photocell, heat sensor, or the like, and is further provided with contacts A,B,C by which one or more external sensors may be connected.

An output device designated 14 is also provided.

Physically this is closely similar to the input device and has two sets of contacts 16, 18 by which it may be connected to other links. The output device 14 contains a battery or other power source 20 as well as a transistor output unit 22 and an output device 24. The latter may be, for example, a buzzer, light or the like.

A detailed description of the operation of the circuits follows; but in brief, connection of the input device directly to the output device energises the input device by connecting the battery 20 to the positive rail 26 of the input device. The connections W, X and V are also made effectively completing the battery circuit via the negative rail 28, disabling the NAND gate 4, and connecting the output of NAND gate 3, via a transistor amplifier 30 and connection W to the output amplifier 22. If the sensor 12 is "off" no signal is fed to the output device 24. If the sensor is actuated the signal is fed to the output amplifier 22 and the output device 24 is actuated. In simple terms, a child pressing the button on the input device sees a light come on on the output device.

Referring now to figure 3, various other logic links can be inserted between the input and output links 10 and 14.

These, once again, will have the same physical dimension and complimentary connectors to enable them to be inserted in circuit. The "OR" and "AND" links (figures 3a and 3b) are connected between two input devices, one of which is connected to an output device, the OR link operating to actuate the output device if either of the inputs is operated, and the AND link operating to actuate the output device only if both of the input links is actuated simultaneously. The latch link (figure 3c) serves to maintain the output device in the "on" mode following actuation of the input device even when that actuation is discontinued. The pulse link (figure 3d) causes the output device to pulse with a frequency dependant on the value of the capacitor C.The NOT link (figure 3e) effectively reverses the output from the input device thus actuating the output device when the input device is not actuated and vice versa.

The detailed operation of the cicuits will now be described.

Referring to figures 1 and 2, if the input link 10 is connected to the output link 14 the positive and negative rails are connected, as are connectors W and V. The negative pole of the battery 20 is connected to the negative rail via the contact V. In the "off" state the sensor 12 has a high or infinite resistance, and in the "on" state it has a low resistance. If a remote sensor is connected to the contact B the logic will be as explained below with the roles of A and B reversed.

Off State Sensor has a high/infinite resistance Nand gate 1: A is held high by R3; B is held high by R2 hence D is low (see truthtable) Nand gate 2: D is low; and C is held high by R1, hence E is high Transistor T1 is on because E is high; hence F is low (by the inverting action) Nand gate 3: F is low and G is high (as point X is held low); hence K is high Transistor T2: K is high thus W is low (inverting action) Transistor T3: W is low, T3 is off thus output device is off.

On State Sensor has low resistance Nand Gate 1: A is now low making D high (see truth table) Nand Gate 2: D and C are high making E low (see truthtable) Transistor T1: E is low thus F is high Nand Gate 3: F and G are high hence K is low Transistor T2: K is low and hence W is high Transistor T3: W is high, transistor T3 is turned on thus the output device is on.

Table 1 INPUT A B C D E F G I K H W OUTPUT Off State 1 1 1 0 1 0 1 1 1 0 0 Off Internal sensor On 0 1 1 1 0 1 1 1 0 0 1 On External sensor On 1 0 1 1 0 1 1 1 0 0 1 On The AND gate (figure 3b) is inserted between two input links 10 to one of which is connected the output link 14.

The output device 24 is actuated only when both inputs 1 and 2 are on. The positive and negative rails are connected straight across between output and input units.

Input 1 acts in the same way as described above. Thus when sensor 1 is off W1 is low when sensor 1 is on W1 is high The AND link connects W1 to C2; xl is held low.

Consider now input 2 If input 1 is off : C2 is low Since C2 is low E must be high Making W2 low whatever the state of input 2 If input 2 is off : A is high making D low Thus W2 is low whatever the state of C2 Inputs 1 & 2 both on : A2 is low making D high C2 is high thus E is low If E2 is low W2 is high W2 operates transistor T3 turning the output device on.

Table 2 Inputs A2 B2 C2 D2 E2 F2 G2 K2 H2 I2 2 Output 1 & 2 off 1 1 0 0 1 0 1 1 0 1 0 Off lon 2 off 1 1 1 0 1 0 1 1 0 1 0 Off loff 2 on 0 1 0 1 1 0 1 1 0 1 0 Off 1 on 2 on 0 1 1 1 0 1 0 0 0 1 1 On The OR gate is connected between two input links in the same way as the AND link, and the positive and negative rails are connected across as before.

Input 1 acts in the normal way W1 is on when the sensor is on. However the OR link takes the output from Y (point E1) and connects it to B2.

When the sensor 1 is off E1 hence B2 is high, when the sensor 1 is on E1 hence B is low (see table 1).

As far as input 2 is concerned the OR link looks like an external sensor (see table 1).

When B2 is high and A2 is high (both inputs off) W2 is off.

When either B2 of A2 or both are low (either/both inputs on) W2 is on.

Table 3 Inputs A2 B2 C2 D2 E2 F2 G2 I2 K2 H2 W2 Output 1 & 2 off 1 1 1 0 1 0 1 1 1 0 0 Off lon 2 off 1 0 1 1 0 1 1 1 0 0 1 On loff 2 on 0 1 1 1 0 1 1 1 0 0 1 On 1 on 2 on 0 0 1 1 0 1 1 1 0 0 1 On The latch circuit (figure 3c) connects between an input and an output. Once again the positive and negative rails are connected across between the input and output links 10 and 14. The latch turns the output device on permanently for a momentary actuation of the input. The latch may be turned off by operating the switch K.

The circuit involves NAND gates 1 & 2. The latch link connects Y to Z completing a feedback loop.

Setting the Latch Initially A, B & C are high and W is low (see table 1).

When there is an input A or B will become momentarily low.

This forces D high and E low and W high (see table 1). E is connected to Y and hence via 2 to B. This will maintain B in the low state. D and thus W will remain high whatever the state of A.

Resetting the Latch: Resetting is effected by momentarily bringing B high by means of switch K, Connected via Z.

Table 4 Input A B C D E F G I K H W Output Off 1 1 1 0 1 0 1 1 1 0 0 Off Setting 0 0 1 1 0 1 1 1 0 0 1 On Set 1 0 1 1 0 1 1 1 0 0 1 On Reset(Kl) 1 1 1 0 1 0 1 1 1 0 0 Off The latch can precede AND/OR Gates and can be followed by the pulse generator. It cannot however follow and AND gate as the first input forces C2 low and the latch cannot be set.

The pulse gate (figure 3d) also locates between an input and output connects the battery positive and negative rails across betweeen these two. When the input turns on the pulse link produces on/off pulses. Nand gates 3 and 4 in the input link 10 are used and a feedback connection is made through contacts U and X involving capacitor C1 and resistor R5 as indicated in the equivalent circuit in figure 3d.

The astable circuit of Figure 3d' will be enabled when F is high.

When the sensor is off F is low (see table 1).

When the sensor is on F is high (see table 1) and the output V pulses.

The pulse link can be used after all other process links. It cannot however precede an OR or a LATCH link.

The NOT link (figure 3e) fits between an input and output link and connects the battery positive and negative rails as before. The NOT link inverts the logic so that the output is on when the input is off and vice versa.

The output is taken from point Y of the input link and connected to W input of the output link.

Y is always the inverse of W for the input link (table 1) thus the output link receives an inverted signal.

The NOT link cannot be used with the pulse link. It can be used with all other links.

Turning now to the embodiment of Figures 4(b) to 7, there is illustrated a device which operates, as far as the user is concerned, in a very similar manner to the embodiment of Figures 1 to 3 but it uses units connecting in parallel with an input unit 10'. Wherever possible like numerals will be used for like parts.

The circuit of the input device 10' is modified from that shown in Figure 1. The principal modifications are that a gate 5 replaces the transistor T1 but has essentially the same inverting function. In addition input C is inverted by a NAND gate 6. The latch function of gates 3 and 4 is replaced by the latch function of gates 7 and 8, thus separating the latch and pulse functions of the circuit.

The sensor 12 of Figure 1 is now in a separate unit that of Figure 7(a).

A fourteen-way bus has been added to provide a similar sequential function to that of the embodiment of figures 1 to 3. This is illustrated in Figures 6. It will be seen that the lines W and W' effectively form a single bus only when connected by means of one or more units. Similar comments apply to the lines X and X'. The units are as illustrated in Figure 7 and comprise, as before, various logical circuits such as "OR" "AND" "NOT" "PULSE" and, in this case, a latch circuit (Figure 7(f)). The units in Figure 7 are essentially the same as those illustrated in Figures 2 and 3 except they are single sided instead of double sided, i.e. have connections on one side only. The side with the connections is of course designed to co-operate with the fourteen-way bus and the letters in Figure 7 correspond to the letters in Figure 6.

Figure 7(b) illustrates an "OR" link. This would be employed with, for example, two sensors (Figure 7(A)) and one output (Figure 7(g)). When the sensor is "ON" it brings the potential of line A to ground, giving it logic "ZERO". This implies an output from transistor T2 at W (logic "ONE") which turns the output on. The "OR" link connects the input of the second sensor to input B. When either A or B is set at logic zero by the appropriate sensor, C becomes logic one and W becomes logic one again turning on the output.

The "AND" link (Figure 7(c)), if substituted for the "OR" link, connects the second sensor to input C. W is only at logic one when both inputs are on (A and C low).

The "NOT" link (Figure 7(d)) connects U, not W, to the output, causing an inversion.

The "PULSE" link (Figure 7(e)) disconnects X from the negative line and connects it to the capacitor (Figure 6).

Gates 3 and 4 then become a pulse generator causing a pulsing output to be produced.

The "LATCH" link (Figure 7(f)) connectssb U to the "SET" input (N) of the latch formed by gates 7 and 8. When there is an input (A becoming logic zero) the latch is set. The switch (SW) on the latch unit resets the latch.

The output unit (Figure 7(g)) is a simple transistor circuit which turns on when W becomes logic 1.

The output unit also serves to make the line X negative.

This is passed back through the links except for the pulse link which connects X to the capacitor.

The device of the invention provides a simply used and vivid educational device illustrating logic circuits. The units or links may carry lettering, pictures or other indicia indicating the circuitry and are easily used by children.

Furthermore the circuitry of the invention enables the devices to be produced simply and economically.

Claims (12)

1. An educational device which comprises at least two units having complimentary external connectors whereby they can be connected together either directly or via an intermediary, characterised in that the logic circuits in the form of a solid state device are contained in the input device only.

2. A device as claimed in claim 1 in which the or each additional unit can be connected to the input device either in series or in parallel.

3. A device as claimed in either of claims 1 or 2 in which the input device comprises a single quadruple NAND microchip.

4. A device as claimed in either of claims 1 or 2 in which the input device comprises a single sextuple NAND microchip.

5. A device as claimed in any of claims 1 to 4 in which one of the units is an output device containing a buzzer, lamp, or other audio/vidisual element.

6. A device as claimed in any of claims 1 to 5 in which at least one further unit is present.

7. A device as claimed in claim 6 in which the further is a "OR" gate.

8. A device as claimed in claim 6 in which the further unit is a "AND" gate.

9. A device as claimed in claim 6 in which the further unit is a "NOT" gate.

10. A device as claimed in claim 6 in which the further unit is a "LATCH" gate.

11. A device as claimed in claim 6 in which the further unit is a "PULSE" gate.

12. A device as claimed in any of claims 1 to 11 in which one or more sensors is connected to the input device either directly or via a unit.