GB2234124A

GB2234124A - Auto-calibrating analogue to digital converter

Info

Publication number: GB2234124A
Application number: GB8916503A
Authority: GB
Inventors: Frank George Titchborne
Original assignee: British Aerospace PLC
Current assignee: BAE Systems PLC
Priority date: 1989-07-19
Filing date: 1989-07-19
Publication date: 1991-01-23
Also published as: GB8916503D0

Abstract

An auto-calibrating analogue to digital converter includes offset compensation means 30, 16, and gain compensation means, 32, 15 and is operable during a setting routine to receive respective digital reference codes and corresponding analogue reference signals to adjust the offset and gain in accordance therewith. <IMAGE>

Description

An Auto-calibrating Analogue to Digital Converter This invention relates to an auto-calibrating analogue to digital converter.

For remote systems requiring accurate Analogue to Digital converters which are immune to drift at one or more points on the conversion curve an autocalibration facility is a prerequisite. Such an application exists for instance on a spacecraft, where accurate tracking to the boresight, or offset from the boresight of a beacon is required.

Broadly stated, according to one aspect of this invention there is provided an auto-calibrating analogue to digital converter having offset compensation means and operable during a setting routine to receive a digital reference code and a corresponding analogue reference signal, and to adjust said offset cornpersation means to cause the converted analogue reference signal output by said converter to match said digital reference code.

A non-limiting example of the invention will now be described with reference to the accompanying drawing, which is a schematic block diagram of an auto-calibrating analogue to digital converter. In the Figure, input signals from sources l n are input via respective input buffer amplifiers 10 to a input multiplexer 12. The output from the input multiplexer is supplied via a further buffer amplifier to a multiplying digital to analogue converter (M-DAC) 14, which has offset and gain compensation terminals 16 and 18 respectively. The output from the M-DAC 14 passes to one input of a comparator 20, the other input being connected to earth. The output signal from the comparator 20 constitutes a conversion feedback signal which is supplied to a successive approximation register 22.The comparator output signal is also supplied to a further multiplexer 24 for a gain and offset setting routine as to be described below. The successive approximation register 22 stores a digital approximation of the analogue signal fed to the M-DAC 14.

In general terms, the M-DAC 14 applies the analogue input voltage across a resistor to give a first current, and convcrts and multiplies the digital approximation b a reference voltage to give a second current. The first and second currents are fed in opposite senses to a summing junction so that the output from the summQng junction represents the difference between the analogue input and the digital approximation, i.e. whether the digital approximation is too high or too low. The offset and gain of the M-DAC 14 may be set by adjusting the magnitude and/or sense of an offset current supplied to the summing junction, and varying a gain resistor 15 in one of the first and second current paths respectively.

The multiplexers 12,24 and an output register 26 are controlled by a control 28. In normal, i.e.

conversion operation, an analogue input signal is supplied to the M-DAC 14 and the most significant bit in the approximation register is set to "1" with the remaining bits set to 11011 to provide a first approximation. The sign of the signal from the M-DAC 14 will indicate whether this first approximation is too high or too low and thus whether the most significant bit should be "1" or "O".Having thus determined the most significant bit, the next bit is set to 1" to provide a second approximation and the output from the M-DAC 14 monitored to see whether this bit should be "O" or "1". This process is continued iteratively until all the bits of the digital approximation have been determined and the resultant digital conversion of the analogue input signal is then shifted to the output register 26.

Referring again to the Figure the output from the comparator 20 is supplied to the further multiplexer 24 where it may be switched to an offset integrator 30 or gain integrator 32. The output of the offset integrator is supplied to the M-DAC summing junction and the output of the gain integrator is supplied to a voltage controlled resistor 15 provided in one of the two main input current paths to the summing junction. These components form auto-offset and auto-gain feedback loops for automatically calibrating the offset and gain of the analogue to digital converter.

A calibration routine is performed at intervals, for example after each conversion operation or at longer intervals. In the calibration routine, the offset and gain of the M-DAC are adjusted to compensate errors in the conversion loop made up of the input multiplexer 12, the M-DAC buffer amplifier, the M-DAC 14 and the comparator 20. The corresponding analogue voltages and digital values are stored for two datum points on the calibration curve In this particular example with a 10 bit resolution, both positive and negative errors are required with the greatest accuracy about the origin and hence one calibration point is taken at the centre point, i.e.

code 1000000000 being calibrated to a zero volts analogue voltage. The other calibration point is takenatthepositive limit of the conversion curve, i.e. code 1111111111 calibrated to a analogue reference voltage V.Rr'F.

To calibrate the analogue to digital converter the offset is compensated first by supplying a force offset code 1000000000 into the M-DAC via the successive approximation register, and supplying the corresponding reference voltage (zero volts) to the M-DAC. The output from the M-DAC is fed to the offset integrator 30 the output of which is supplied to the summing junction of the M-DAC until an equilibrium condition is reached at which the output from the M-DAC is minimal. During the subsequent conversion period(s) the offset compensation current is maintained by the integrator by virtue of the stored charge on the feedback capacitor.

Thereafter the gain is compensated by supplying a force gain code 1111111111 into the M-DAC together with a corresponding reference voltage V.REF. The output from the M-DAC is supplied to the gain integrator 32, the output of which is supplied to the voltage controlled resistor, which serves as the gain resistor 15 of the M-DAC, until the equilibrium condition is reached. The gain compensation current is maintained by the integrator during the subsequent conversion period(s).

The circuit uses the non-conversion time to automatically compensate for voltage offsets and DAC gain variations at two chosen calibration points. All offset and gain errors in the source multiplexer, the DAC and the successive approximation comparator of the Analogue to Digital converter are continuously calibrated out. This includes both initial offset and gain variations caused by manufacturing tolerances, as well as drifts caused by effects such as radiation, temperature or ageing. The circuit removes the need for initial ontest gain and offset trimming since this is an automatic function. Using this gain and offset calibration method ensures complete lifetime accuracy within the inherent linearity of the component DAC.

Claims

'CIAI S

1. An auto-calibrating analogue to digital converter having offset compensation means and operable during a setting routine to receive a digital reference code and a corresponding analogue reference signal, and to adjust said offset compensation means to cause the converted analogue reference signal output by said converter to watch said digital reference code.

2. An auto-calibrating analogue to digital converter according to Claim 1, further having gain compensation means and being operable during said setting routine to receive a further digital reference code and corresponding further analogue reference signal and to adjust said gain compensation means to cause the converted further analogue reference signal output by said converter to match said further digital reference code.

3. An auto-calibrating analogue to digital converter according to Claim 1 or Claim 2, wherein said setting routine takes place in the non-conversion time.

4. An auto-calibrating analogue to digital converter according to any preceding Claim, inculding multiplying digital to analogue converter means having offset compensation means and operable to receive a digital code and an analogue input and to output an error signal representing the difference between said digital code and the digitised analogue input, and a successive approximation register for storing a digital code approximation of said analogue input and responsive to said error signal to refine said digital code approximation.

5. An auto-calibrating analogue to digital converter according to Claim 4, wherein, during said setting routine, said multiplying digital to analogue converter means receives one of said digital reference codes from said successive approximation register, and a corresponding analogue reference signal, and said error signal is used to adjust said offset and/or said gain compensation means.

6. An auto-calibrating analogue to digital converter according to Claim 5, wherein said error signal is integrated and stored to provide an offset and/or gain compensation signal.

7. An auto-calibrating analogue to digital converter substantially as hereinbefore described with reference to and as illustrated in the accompanying drawing.

8. Any novel combination or subcombination of features substantially as disclosed herein.