GB2234095A - Memory arrangement - Google Patents

Abstract

An arrangement is provided for expanding memory capacity of a computer just by adding a compatible memory board. A main board 10 controls a plurality of similar memory boards 20, each of which includes: a memory controller 21 for addressing a plurality of memory elements arranged in a memory array 25, on the basis of a memory controller selection signal CS generated on the memory board 20; means 23 for latching memory board selection data D@ output from the main board 10 on the basis of a clock pulse CK input thereto; and a memory board selection means 22, 26 for generating the memory controller selection signal CS on the basis of the output signal of the latching means 23 and controlling the operation of the memory controller 21. Setting of a switch 22 enables only one memory board 20 at a time to respond to the main board 10 to allow the respective memory array 25 to be addressed. <IMAGE>

Description

MEMORY ARRANGEMENTS The present invention generally relates to memory arrangements and is concerned with expansion of memory capacity.

As a control process for a memory board generally depends on its memory capacity, memory boards are usually manufactured in different types, according to their memory capacity. In a conventional system, when memory capacity requires expansion, a new memory board of larger capacity must be installed in place of an existing one, which is then discarded, resulting in a waste of money.

Preferred embodiments of the present invention aim to provide a device capable of expanding memory capacity more efficiently as occasion arises just by adding a compatible memory board.

According to a first aspect of the present invention, there is provided a memory arrangement comprising a plurality of memory boards all arranged to be controlled by a main board in a similar manner and each having a respective memory array, means for addressing said array, and selection means for selectively enabling or inhibiting addressing of the memory array in response to signals received from the main board, the selection means of the memory boards being so set or settable that, in response to a common selection signal received by all of the memory boards from the main board, the selection means of only one of the memory boards enables addressing of its respective memory array in response to signals received from the main board.

Preferably, the memory arrangement further comprises a main board to which all of the memory boards are connected, to be controlled in a similar manner, the main board being arranged to send to the memory boards signals to address their memory arrays and said common selection signal to which the selection means of the memory boards respond.

Preferably, each memory board comprises: a memory controller for addressing a plurality of memory elements arranged in the respective memory array, on the basis of a memory controller selection signal generated in the memory arrangement; and latching means for receiving said common selection signal from the main board and latching that signal on the basis of a clock pulse input thereto: the respective selection means of the memory board being arranged to enable or inhibit the memory controller selection signal on the basis of the output signal of the latching means and to thereby control the operation of the memory controller.

For each memory board, the respective selection means may comprise: switching means connected to receive the output of said latching means, and being settable to distinguish that memory board from other memory boards; and means connected between the switching means and the memory controller, for outputting the memory controller selection signal on the basis of the output of the latching means.

In such a memory arrangement, two of the memory boards may have identical said switching means each connected to receive as inputs complementary outputs of a respective one of identical said latching means, and being switched to output a respective output of said latching means which is complementary to that output by the switching means of the other of said two memory boards.

Preferably, all of said memory boards are identical in all respects, other than said setting of said selection means.

The invention also extends to a computer having a memory arrangement as above, in accordance with the first aspect of the invention.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a diagram showing the connection of a main board and a memory board in one example of an embodiment of the present invention; Figure 2 is a diagram illustrating memory expansion in the embodiment of Figure 1; and Figure 3 is an example of a partial timing diagram of the embodiment of Figures 1 and 2.

Referring primarily to Figure 1, a main board 10 for a computer includes a central processing unit (CPU) 11, an I/O port 12 and a decoder 13. Further, a memory board 20 includes a memory controller 21 for producing control signals to a memory array 25 having a plurality of memory elements so as to store data in the memory array 25 or to read out the data stored in response to a memory controller selection signal on line 3, a tap switching circuit 22 for distinguishing between memory boards according to its switching state, a D flip-flop 23 for controlling the tap switch 22 by being latched by a clock pulse on line 4 so as to enable the CPU 11 to select a corresponding memory board, and a memory board driver 24 for refreshing the memory array 25 periodically by controlling the memory controller 21.

Referring now to Figure 2, a first memory board 20 and a second memory board 30 of the same structure are connected to the main board 10. The inner structure of the board 30 is like that of the memory board 20 illustrated in Figure 1.

Figure 3 shows an example of a partial timing chart of the embodiment, in which 3A represents a basic clock pulse, and 3B and 3C represent respectively a command word and an address signal which are applied from the CPU 11.

3D through 3G represent respectively a row address strobe (RAS), an address A00-A08, a column address strobe (CAS) and a write enable signal WE which are applied to each memory element in the memory array 25. 3H represents an acknowledge (AACK) signal.

The main board 10 and the memory board 20 are connected by a connection cable 40. Through this connection cable 40, data on a data bus 1, address on an address bus 2, a memory controller selection signal on the line 3 and a clock signal on the line 4, which are generated from the main board 10, are transferred to the corresponding lines of the same reference numerals on the memory board 20.

When the memory board 20 is supplied with power, the memory board driver 24 controls the memory controller 21 so as to refresh the plurality of memory elements of the memory array 25, periodically. While the plurality of memory elements are refreshed, the AACK signal shown in 3G of Figure 3, which is a signal for forbidding the CPU 11 to access the memory elements, is applied to a ready terminal (not shown) of CPU 11.

In order to operate the memory controller 21, a chip selection terminal CS must maintain a logic "HIGH" signal.

If this chip selection terminal CS is logic "LOW", the memory controller 21 will not be operated. When the memory controller 21 operates to accesses the memory elements of the memory array 25, the address A00-A08 and the write enable signal WE shown as 3C and 3G in Figure 3 respectively are output from the memory controller 21 by being controlled by the row address strobe RAS and the column address CAS which are generated internally from the memory controller 21. The memory controller selection signal on the line 3, which is applied to the chip selection terminal CS of the memory controller 21 through an AND gate 26 is applied to an input terminal of the AND gate 26, the memory controller selection signal being decoded by the decoder 13. In addition, if logic "HIGH data is applied to another input terminal of the AND gate 26, then the memory controller selection signal on the line 3 will be sent to the chip selection terminal CS by way of the AND gate 26.

In other words, the memory board 20 will be operated when logic "HIGH" data is applied to the latter input terminal of the AND gate 26, while the memory board 20 will not be operated when logic "LOW" data is applied to the latter input terminal of the AND gate 26. However, the logic state of the latter input terminal of the AND gate 26 will be maintained by the D flip-flop 23.

The D flip-flop. 23 receives a board selection signal by receiving the data bit DO, one bit of the data on the data bus 1 which is applied from the CPU 11, and the data bit DO is latched at the rising edge of clock pulse on the line 4 and output through output terminals Q and Q. The output data of the D flip-flop is input to the latter input terminal of the AND gate 26 through the tap switch 22.

Assuming that the memory board 20 which is a first memory board and the memory board 30 which is a second memory board are connected to the main memory board 10 in such a manner as illustrated in Figure 2, it is preferably arranged that the tap switch 22 of the first memory board 20 is switched manually such that the node "a" is connected to a node "b" thereof, while the tap switch 22 of the second switch board 30 is switched manually such that the node "b" is connected to a node "c" thereof.

The tap switch 22 can be easily set by hand, and this can be effected upon the installation of memory board.

Then, the selection of memory board according to data bit DO is as shown in Table 1.

Table 1

DO 0 Q Available Memory Board HIGH HIGH LOW First Memory Board LOW LOW HIGH Second Memory Board It will be well understood that the CPU 11 may use the first memory board 20 by latching the data bit DO to logic "HIGH" through the D flip-flop 23 and use the second memory board 30 by latching the data bit DO to logic "LOW" through the D flip-flop 23. Accordingly, memory capacity may be also easily expanded just by adding a memory board of the same type.

The above described embodiment is very advantageous because it easily enables memory capacity to be expanded not by the use of a new circuit and a new memory board as a replacement, but by the addition of an already-designed circuit and a similar memory board.

Although specific constructions of an embodiment of the invention have been illustrated and described herein, it is not intended that the invention be limited to the elements and constructions disclosed. One skilled in the art will easily recognize that the particular elements or subconstructions may be used without departing from the scope and spirit of the invention.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (8)

CLAIMS:

1. A memory arrangement comprising a plurality of memory boards all arranged to be controlled by a main board in a similar manner and each having a respective memory array, means for addressing said array, and selection means for selectively enabling or inhibiting addressing of the memory array in response to signals received from the main board, the selection means of the memory boards being so set or settable that, in response to a common selection signal received by all of the memory boards from the main board, the selection means of only one of the memory boards enables addressing of its respective memory array in response to signals received from the main board.

2. A memory arrangement according to Claim 1, further comprising a main board to which all of the memory boards are connected, to be controlled in a similar manner, the main board being arranged to send to the memory boards signals to address their memory arrays and said common selection signal to which the selection means of the memory boards respond.

3. A memory arrangement according to Claim 1 or 2, wherein each memory board comprises: a memory controller for addressing a plurality of memory elements arranged in the respective memory array, on the basis of a memory controller selection signal generated in the memory arrangement; and latching means for receiving said common selection signal from the main board and latching that signal on the basis of a clock pulse input thereto: the respective selection means of the memory board being arranged to enable or inhibit the memory controller selection signal on the basis of the output signal of the latching means and to thereby control the operation of the memory controller.

4. A memory arrangement according to Claim 3, wherein, for each memory board, the respective selection means comprises: switching means connected to receive the output of said latching means, and being settable to distinguish that memory board from other memory boards; and means connected between the switching means and the memory controller, for outputting the memory controller selection signal on the basis of the output of the latching means.

5. A memory arrangement according to Claim 4, wherein two of the memory boards have identical said switching means each connected to receive as inputs complementary outputs of a respective one of identical said latching means, and being switched to output a respective output of said latching means which is complementary to that output by the switching means of the other of said two memory boards.

6. A memory arrangement according to any preceding claim, wherein all of said memory boards are identical in all respects, other than said setting of said selection means.

7. A memory arrangement substantially as hereinbefore described with reference to the accompanying drawings.

8. A computer having a memory arrangement according to any of the preceding claims.