GB2232855A - Computer network access control system - Google Patents

Abstract

A priority resolving system (3a-3d) for enabling a network of computers (2a-2d) to gain access to a bi-directional data bus (4). The use of the invention prevents collisions between transmissions from computers competing for bus access and also minimises the access waiting time. Each system (3a-3d) monitors traffic on the bus, waits for a "bus active" to "bus inactive" transition to occur then accesses the bus after a pre-determined and unique time interval. If there is no traffic for a comparatively long time then each system puts a timing pulse onto the bus thus ensuring that the bus never goes completely quiet during long periods when no messages are being transmitted. <IMAGE>

Description

COMPUTER NETWORK ACCESS CONTROL SYSTEM This invention relates to computer networks in which a multiplicity of geographically-dispersed computer stations intercommunicate via a single bi-directional bus. In such networks, a message can be sent by any computer station and can be received by every other computer station connected to the bus. However, only one message can be transmitted at any one time. If two or more computer stations were to attempt to send messages over the bus simultaneously, the messages would collide and either be lost, or in certain instances, a new erroneous one would be created. It is therefore necessary that access to the bus be controlled in some manner.

A number of different techniques have been proposed for controlling access to a bi-directional bus so that collisions can be avoided. In one known method, a computer station wishing access to the bus, monitors the bus for activity. If there is no activity for a pre-determined time interval, T, then the computer station assumes that the bus is clear and subsequently sends its message. A system of priority may be incorporated by allocating different values of T to each computer, the computer having the highest priority waiting the shortest period. However, to ensure collision avoidance, each computer station desiring access to the bus must always wait for the moment of cessation of bus activity before it can commence to time its allocated interval, T.If, at the moment access-is required, the bus is inactive, the computer station has to wait for bus activity to restart and then cease before commencing to time the interval T and even then its access might be overtaken by a higher priority computer.

Hence in certain cases a given computer station comprising the network may have to wait an unnecessarily long and unpredictable time before it is allowed to access the bus.

The present invention seeks to overcome this disadvantage, so reducing the waiting time (and enabling it to be predicted with reasonable accuray) by ensuring that inactivity of the bus does not exceed a set time period.

The present invention therefore consists of a computer network comprising a bi-directional network transmission bus and a plurality of spatially separated computer stations connected to the bus in which each computer station incorporates a computer and an access control system, each computer being assigned a unique priority time interval T2, the computer having the highest priority having the smallest T2, and each access control system comprising means for continuously monitoring the bus for activity and means for enabling its associated computer to access the bus after a period of bus inactivity equal to T2 has elapesed and the network comprising means for putting a timing signal onto the bus after a period of bus inactivity T1 has elapsed where T1 is greater than the value of T2 assigned to the lowest priority computer.

In one embodiment, the means for putting a timing signal onto the bus are incorporated within the access control system of at least one of the computer stations.

The access control system may be provided with means forgenerating a computer interrupt signal in cases where the bus remains inactive for a period TO which is appreciably longer than T1. This situation could occur due to failure of one or more computers comprising the network.

The time periods TO, T1 and T2 are chosen bearing in mind the number of computer stations in network and the largest distance between any two computer stations over which transmitted signals must travel.

TO may have the same value for each computer on the network.

Similarly, each computer may be assigned the same value of T1.

Because each computer must wait a unique time interval (T2) before it can gain access to the bus, collisions are avoided (since no two computers have the same T2 value).

Elapsed time periods may be monitored by an integrated circuit (forming part of the access control system) pre-programmed with the values of TO, T1 and T2 relating to its associated computer. The time periods TO, T1 and T2 commence from the point of cessation of bus activity. If a message is transmitted over the bus during any of these time intervals, then the circuit will be inhibited until bus activity ceases again, whereupon the circuit will be reset.

The timing signal, which may take the form of a single, short pulse and which is put onto the bus after a period of bus inactivity equal to T1 has elapsed, ensures that the network never goes completely quiet during long periods when no messages are being sent.

Hence, any computer wishing access to the bus during a quiet period does not have to wait until another computer has sent a message and then time its allocated (priority) interval (T2) after cessation of such a message, but may reset its timer on detection of the timing pulse alone. The waiting time for access to the bus for any given computer is thus reduced.

An embodiment of the invention will now be described, by way of example only, with reference to the drawings of which: Fig 1 is a block diagram of a computer network in accordance with the invention, Fig 2 is a block diagram of one of the access control systems shown in Fig 1, and Fig 3 is a timing diagram relevant to the function of the access control system of Fig 2.

Fig 1 shows a computer network comprising four geographically dispersed computer stations la, lb, lc and ld. The particular number of computer stations shown is for illustrative purposes only, there may be more or less than four. Each computer station comprises a computer 2a-2d which is connected to one of four associated access control systems 3a-3d. The computers and access control systems are connected to a bi-directional transmission bus 4.

The values of the three aforementioned time intervals TO, T1 and T2 are pre-assigned to each computer. Each computer has a unique T2, typical values in this example for the computers 2a, 2b, 2c and 2d being 10 ps, 20 ps, 30 and 4Oiis respectively. Hence the computer with the highest priority is 2a and that with the lowest is 2d. The values of time intervals TO and T1 are preset to be the same for each computer, typically in this example 200 ps and 100 ps respectively. Each computer (2a-2d) comprises a local area network (LAN) computer board such as an Intel (Trade Mark) SBC 186/51 which includes a microprocessor (Type No 80186), a LAN coprocessor (Type No 82586) and whose transceiver (Type No 8023A) has been removed and incorporated within its associated access control system (3a-3d).

Each access control system 3a-3d comprises the components shown in Fig 2. The aforementioned transceiver 5 senses network activity and receives and transmits information to and from the bus 4. It communicates (in the usual manner) with the local area network computer board via the connections collectively designated by the reference numerals 6 and 7. The transceiver 5 is driven by a 20 MHz crystal-controlled oscillator 8,and turn, generates a carrier sense output (CRS) on pin 6 and a 10 MHz clock output (TXC) on pin 16. The 10 MHz clock output clocks a dual J/K flip flop 9 (such as a Texas Instruments 74 LS 112) and also drives a BCD counter 10 (such as a Texas Instruments 74 LS 192). The counter 10 generates a two-phase 1 MHz clock output at pins 6 and 7.A first of the two phases drives a timer 11 (such as an INTEL 8253) which times the intervals TO, T1 and T2, the values of which are pre-programmed by the microprocessor into the timer 11 via the connections designated by the reference numeral 12. A dual D-type flip-flop 13 (such as a Texas Instruments 74 LS 74) either enables or inhibits the timer 11, thus performing the necessary synchronising functions so that the timer 11 can commence to time the intervals TO, Tl and T2 at the appropriate moments. A second dual D-type flip-flop 14 (such as Texas Instruments 74 LS 74) and the dual J/K flip-flop 9 relay T1 and T2 time interval information to the transceiver 5(on pin 15) via a NOR gate 15.The flip-flops 13 and 14 are clocked by the second phase of the 1 MHz clock output generated by the counter 10. Hence all the flip-flops 9, 13 and 14 the timer 11 and the counter 10 operate in synchronism with the transceiver generated 10MHz clock (tic).

When the computer network is switched on, the microprocessor transmits a reset pulse to the access control system on line 16. This has the effect of clearing the 2CL input of the flip-flop 13 which, as a result, presets the 1PR and 2PR inputs of the flip-flop 9. Any subsequent bus activity is sensed by the transceiver 5 and indicated on pin 6 (CRS), this information being clocked through to the gate inputs (pins 11, 14 and 16) of the timer 11 by the 1Q output of the flip-flop 13. In this way, the gate inputs inhibit the timer 11 whilst the bus is active and then reset it so that it can commence timing the intervals TO, T1 and T2 from the moment that bus activity ceases.

Provided that the timer 11 is reset by the CRS signal within a time interval equal to T1, (lOO ps #sin this example) then pin 13 of the timer 11 remains inactive. If the bus is inactive for a period equal to T1, then pin 13 of the timer 11 changes state. This change of state is clocked through the flip-flop 14 (via the ID input) to the 2J and 2K inputs of the flip-flop 9 which, in turn, passes on the information from its 2Q output via the NOR gate 15 to the transmit/ enable input (TEN) of the transceiver 5. This has the effect of producing a signal on the bus which, in turn, produces a CRS (bus active) signal. Hence the timer 11 is inhibited by the flip-flop 13 and pin 13 of the timer 11 changes state again. The change of state is relayed (on the next 1 MHz clock pulse) to the TEN input of the transceiver 5 by the flip-flops 14 and 9.Hence a timing signal in the form of a pulse is produced on the bus which in this example is 1 ps wide. At the end of the pulse, the CRS output changes state again thus resetting the timer 11.

If the computer which is associated with the access control system of Fig 2 requires access to the bus 4 then the LAN coprocessor makes a request by setting the ready to send (RTS) line 18. This request is transmitted to the flip-flops 13 and 14. It has the effect of pre-setting and priming the 2PR and 2D inputs of the flipflop 14)and presetting the 2PR input of flip-flop 13. However, the computer is not allowed access to the bus until a period of bus inactivity equal to T2 has elapsed, this interval being timed by the timer 11. When the end of this time period is reached pin 17 of the timer 11 changes state and clocks the request (on the 2D input of the flip-flop 14)through the primed flip-flop 14 to the 1J and 1K inputs of the flip-flop 9.The signals on the said 1J and 1K inputs are clocked through to the 1Q and 1Q outputs of the flip-flop 9 on the next 10 MHz clock pulse from the #TXC output of the transceiver 5.

The Iq and 1Q outputs activate respectively a clear to send (CTS)signal on line 18 which connects with the LAN coprocessor and the transmit/ enable (TEN) line of the transceiver 5, 1Q being inverted by the NOR gate 15. Thus the computer is instructed to send its message via the bus 4. Once the message transmission is in progress, the transceiver 5 sets its CRS output so that the timer 11 is inhibited. Also, the LAN coprocessor removes its request from line 17, thus presetting the 2PR input of the flip-flop 14 which in turn propagates to the 1J and 1K inputs of the flip-flop 9 thus removing the CTS and TEN signals.

In the case of a malfunction, which causes the bus to be inactive for a period equal to TO (200 iis in this example), no #CRS signals will be generated for inhibiting and resetting the timer 11 during this period. Hence, when the time period TO has elapsed, the timer 11 transmits an interrupt signal to the associated computer on line 19.

The timing diagram of Fig 3 illustrates one example of a mode of operation of the access control system of Fig 2. The pulse trains designated A, B, C and D represent, respectively, the timing signal, the carrier sense output (CRS), the ready to send request (RTS) and the clear to send signal (#CTS). Time t0 denotes the instant from which the timer 11 begins to time the intervals TO, T1 and T2 forthe first time. After a period equal to T1, during which CRS remains high, (indicating bus inactivity) the transceiver 5 puts onto the bus a 1 p s pulse (see pulse train A) at ti-me t. Subsequently, this bus activity is signalled by CRS going low (see pulse train B). CRS then goes high again (at time t2) after the timing pulse is removed. CRS going high resets the timer 11 which commences to time the intervals TO, T1 and T2 once again. At a time t3, a request is raised ie Ruts (line C) goes low. However, before the computer is allowed to access to the bus in order to transmit its message, a time interval equal to T2 must have elapsed since the last transition from bus activity to inactivity (which occurred at time t2). At the end of this time interval a CTS signal is generated (line D) at time t4 . When the transmission is complete (at t5), the request is withdrawn (ie RTS goes high) causing CTS and CRS to go high again. Subsequent bus inactivity is interrupted at t#by a further timing signal pulse.

If-, in this example, the pre-programmed value of T2 had been shorter than the time interval (t3-t2) then the computer, before gaining bus access, would have to wait a further period T2 after the next active-toinactive transition. This could follow the next timing pulse or the end of a transmission by another computer comprising the network.

Claims (4)

Claims

1 A computer network comprising a bi-directional network transmission bus and a plurality of spatially separated computer stations connected to the bus in which each computer station incorporates a computer and an access control system, each computer being assigned a unique priority time interval T2, the computer having the highest priority having the smallest T2, and each access control system comprising means for continuously monitoring the bus for activity and means for enabling its associated computer to gain access to the bus after a period of bus inactivity equal to T2 has elapsed and the network comprising means for putting a timing signal onto the bus after a period of bus inactivity T1 has elapsed where T1 is greater than the value of T2 assigned to the lowest priority computer.

2 A computer network as claimed in claim 1 in which the means for putting a timing signal onto the bus are incorporated within the access control system of at least one of the computer stations.

3 A computer network as claimed in claim 1 or claim 2 in which the access control system further comprises means for generating a computer interrupt signal after a period of bus inactivity equal to a predetermined time interval which is longer than Tl has elapsed.

4 A computer network substantially as herein before described with reference to the drawings.