GB2229332A - Frequency synthesisers - Google Patents

Abstract

In a frequency synthesiser, oscillations from a controlled oscillator 14 are counted at 16 during a first time interval t, and a control count value is derived therefrom and latched at 28 for controlling the oscillator 14 and the power supplied at least to the counter is switched off by 18 during a second time interval t2. Counter 16 and a counter 12 counting reference oscillations from 12 are enabled during t1. During t2, the count output C1 of 16 latched at 20 is subtracted from a reference count C0 from a register 24. The difference value is again subtracted at 26 from a previously latched value at 28 to derive an error control signal for VCO 14 which is adjusted to zero over a number of cycles. The reference count C0 may be altered for selecting different output frequencies. Frequency mixers, dividers or multipliers may be provided within or outside the control loop. Applications may be in a radio or paging receiver requiring power economy. <IMAGE>

Description

FREQUENCY SYNTHESI SERS This invention relates to frequency synthesisers which may be used to set stable oscillation frequencies, for example, in radio receivers.

It is known to use crystal controlled oscillators in locked oscillator mode to derive the required injection signals for the frequency mixers in radio receivers. In this type of arrangement, signals from a reference oscillator and from a voltage controlled oscillator (VCO), which may be frequency divided as required, are fed to a comparator. The frequency or phase difference produces a dc output which is used to control the VCO, typically by biasing a voltage controlled diode in the VCO, and thus varies the output frequency of the VCO until the two oscillation signals are synchronized and then phaselocked. This approach has limitations in respect of switch off/recovery time, high power requirements and adjacent channel noise.

Also, in certain applications, there is a requirement for controlled oscillators to provide a number of different frequencies, so as to cover a number of transmission channels. One such application arises in the radiopaging field, in which it is being proposed to provide radiopaging receivers capable of scanning a number of frequencies.

Providing a different oscillator crystal for each frequency would be very expensive, and thus a suitable frequency synthesising technique would be advantageous. However, most existing frequency synthesisers have relatively high power consumption, which renders them unsuitable for use in radiopaging receivers, in which power economy considerations are paramount.

According to one aspect of this invention there is provided a frequency synthesiser comprising: an oscillator having its frequency controllable by a control signal; a counter for counting oscillations from the oscillator during a first predetermined time interval to provide a count value; means for latching a control count value derived from the counter count value, the control count value providing the control signal for the oscillator; and means for switching off power at least to the counter during a second predetermined time interval.

According to another aspect of this invention there is provided a frequency synthesiser comprising: an oscillator having its frequency controllable by a control signal; and a control loop for comparing the frequency of the oscillator with a required frequency and generating the control signal for controlling the frequency of the oscillator, the control loop including digital storage means for storing control data representing the required frequency adjustment to the oscillator, and a digital to analog converting means for converting the control data to form the control signal.

A preferred embodiment of the invention, to be described in greater detail hereinafter, provides a frequency synthesiser which overcomes the above problems by providing means for minimising the power consumption by switching off a large part of the circuitry for a high percentage of the time, and by using a counter based frequency locking technique instead of a phase locked loop.

The preferred frequency synthesiser includes a first counter arranged to count the oscillations from a VCO during a predetermined interval defined by a second counter dividing down the output of a reference oscillator. The first counter output is held in a first latch bank and the counters are turned off by a power control circuit until next required. The latched first counter output is compared in a first binary subtractor with a number representing the required frequency held in a binary register. The calculated result is fed to a second subtractor together with a control count already held in a second latch bank. The result from the second subtractor is then stored in the second latch bank and used to control the VCO by means of a digital-to-analog converter. The calculated result is also used as the new control count to be applied to the second subtractor.

The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which: Figure 1 is a diagram of a frequency synthesiser in accordance with an embodiment of the invention; and Figure 2 is a timing diagram showing the operation of the frequency synthesiser of Figure 1.

Referring to Figure 1, the frequency synthesiser includes a reference oscillator 10 which may, for example, be a 32768 Hz CMOS clock oscillator connected to feed its oscillation output to an m-bit binary counter 12. A voltage controlled oscillator (VCO) 14 is connected to an n-bit binary counter 16 whose reset terminal R receives a reset signal from the m-bit binary counter 12. A power control circuit 18 also receives an output from the m-bit binary counter 12 and sends power control signals to both binary counters 12, 16. The count output of the n-bit binary counter 16 is applied to a first set of n-bit d-type latches 20, which also receive an enable signal from the m-bit binary counter 12.

The output of the first set of latches 20 is applied to an n-bit binary subtractor 22. The subtractor 22 also receives a further input from an n-bit binary register 24, which may be responsive to a "data in" signal.

The difference output from the first subtractor 22 is supplied via a second n-bit binary subtractor 26 to a second set of n-bit d-type latches 28. One output from the second set of latches 28 is applied to a further input of the second subtractor 26. Another output of the second set of latches 28 is applied to an n-bit binary digital-to-analog (D/A) converter 30. The analog output of the D/A converter 30 is supplied to the control input of the VCO 14. The output of the VCO 14, as well as being applied to the input of the n-bit binary counter 16, provides the output of the frequency synthesiser at an output terminal 32.

The operation of the circuit shown in Figure 1 will now be described, initially without making reference to the power control circuit 18, and assuming that the n-bit binary register 24 produces a constant count input cO to the further input of the first subtractor 22.

The m-bit binary counter 12 counts a predetermined number of pulses from the reference oscillator 10, thereby defining a time interval tl at the start of which a reset pulse is applied to the n-bit binary counter 16. In the meantime, the binary counter 16 counts pulses from the VCO 14. The effect of this is that the n-bit binary counter 16 divides down the output of the VCO 14 in the time interval tl as determined by the m-bit binary counter 12.If the frequency of the VCO 14 is f1, the count output c1 from the counter 16, next held in the first set of latches 20, will be c1 = f1 x tl. The first subtractor 22 calculates the difference between the count c1 and the count cO from the register 24, and applies the value cO - c1 to the second subtractor 26.

The second subtractor 26 and the second set of latches 28 are connected in a feedback manner such that a preceding count c2 held in the second set of latches 28 has subtracted from it the current count cO - c1 from the first subtractor 22. Thus, the output of the second subtractor 26 is c2 - cO + c1. This then becomes the new value of c2 held in the second set of latches 28, used in the feedback loop and also applied to the D/A converter 30. The analog value of this count is then used as the control input to the VCO 14.

Thus it can be seen that the value c2 is a digital representation of the control voltage setting the output frequency of the synthesiser. The count cO from the register 24 is representative of the required frequency, and if the loop frequency of the synthesiser is not at the required value, this will be represented by the first subtractor 22 output (cO - c1) not being zero. The combination of the second subtractor 26 and the second set of latches 28 will adjust the value of the count representative of the control voltage until the output cO - cl of the first subtractor 22 is zero.At that time, the count c2 being fed back from the second set of latches 28 to the second subtractor 26 will remain unchanged at the output of the second subtractor 26 (since the difference input is zero) and that particular count value c2 will be circulated around the loop formed by the second subtractor 26 and the second set of latches 28. Thus, the control voltage to the VCO 14 from the D/A converter 30 will remain constant, locking the frequency at the required value. Any disturbance of the VCO loop will result in the output of the first subtractor 22 no loner being zero, whereupon the second subtractor 26 and the second set of latches 28 will retrack the control voltage to the necessary value.

A significant advantage of the circuit as described is that, as long as the control count value c2 is held in the second set of latches 28, if power to the rest of the circuit is discontinued and subsequently re-applied, the tracking delay should be eliminated or at least minimised, since the control count value c2 will be available immediately upon switch-on to set the control voltage of the VCO 14 at or very near the required level. This feature is particularly useful in applications such as receivers of radiopaging systems in which it is desirable for the major power consuming components of the receivers to be switched off during periods when desired transmissions are not being received. This type of operation will now be described with reference to the power control circuit 18 in Figure 1, and also referring to the timing diagram of Figure 2.At the beginning of the time interval ti, the n-bit binary counter 16 is reset, and the final count at the end of the time interval tl is passed to the first set of latches 20, this final count being representative of the output state of the VCO 14. As stated above, the transferred count c1 will be equal to fl x tl.

At the end of the time interval tl, the power control circuit 18 shuts down the power to both counters 12, 16 for a predetermined time interval t2 set by the power control circuit 18. The time interval t2 depends on the short term frequency stability of the VCO 14 and the performance required from the frequency synthesiser. During the time interval t2, the difference between the count value c1 and the required count value cO from the register 24 is calculated in the first subtractor 22 and the remaining steps in the process are carried out as described above. At the end of the time interval t2, the counters 12, 16 are both powered up again, and the n-bit counter 16 is reset again.Thus, it will be seen that, during each control cycle of the power control circuit 18, the frequency fl of the VCO 14 will change by an amount proportional to cO - cl, which will place it closer to the required frequency (namely that set by the register 24), unless cO - cl = 0, signifying that no change in frequency is necessary.

The constraints on the time interval tl are frequency accuracy, lock time and power consumption. Maximum frequency error f1 (max) is given by: fl (max) = 1/ti Hz which, in terms of parts per million (ppm) is given by: error = 106/(f1 x tl) ppm.

Lock time will be proportional to tl + t2 and related also to the VCO characteristic and the frequency change required. The time interval t2 can be made very short if a fast lock time is required, but this makes an impact on the power consumption. It is therefore preferable to retain as high a value of the time interval t2 as possible under constant frequency conditions, and reduce its value when a fast frequency change is required. The minimum value of the time interval tl will in general have been defined by the frequency accuracy required and will therefore place a limitation on the minimum lock time.

Mean power consumption p is given by: p = pl x tl + p2 x t2 W tl + t2 where p1 and p2 are the respective power consumptions during the time intervals t1 and t2.

As the power consumption pl includes that of both binary counters 12, 16 operating at a high clock rate, it will be much higher than the power consumption p2. Thus, it can be seen that for minimum power consumption, the value of t1/t2 should be minimised.

If it is desired to extend the frequency coverage, it is possible to include frequency mixers, dividers and/or multipliers inside and/or outside the control loop, in similar manner to that effected in phase locked loop synthesisers.

As described above, the frequency synthesiser shown in Figure 1 generates a single frequency, according to the required count value cO from the register 24. However, if the synthesiser is to generate more than one frequency, the register 24 may receive suitable "data in" signals at its control input, whereby the count value cO supplied by the register 24 will depend on which frequency has been selected by the "data in" signals. Also, pre-determined correction data, to avoid reference oscillator frequency/temperature characteristic effects, can additionally (or alternatively) be held in the register 24.

A practical VCO 14 will typically include a varactor diode receiving the control voltage from the D/A converter 30, and the varactor diode will generally be able to pull the VCO over a frequency swing of about 2:1. However, in radiopaging receivers, the limited voltage available reduces the frequency range to about 10%. This allows for different frequency values over a certain more or less limited frequency band to be chosen. If this band is too narrow, the same basic oscillator circuit can be centred on different frequency bands by means of one or more trimmer capacitors in parallel with the varactor. In addition to this, or alternatively, the VCO may be followed by the above-mentioned mixers, dividers or multipliers, and these components can be selected as required. For example, the VCO can be used directly as the local oscillator over 25 to 54 MHz and followed by a frequency tripler in the 136 to 175 MHz band.

Claims (8)

1. A frequency synthesiser comprising: an oscillator having its frequency controllable by a control signal; a counter for counting oscillations from the oscillator during a first predetermined time interval to provide a count value; means for latching a control count value derived from the counter count value, the control count value providing the control signal for the oscillator; and means for switching off power at least to the counter during a second predetermined time interval.

2. A frequency synthesiser according to claim 1, including a reference oscillator and a further counter for defining the first predetermined time interval.

3. A frequency synthesiser according to claim 1 or claim 2, including a register for supplying a reference count value representative of a desired frequency, and a difference means for subtracting the counter count value from the reference count value to provide a difference count value.

4. A frequency synthesiser according to claim 3, including means for subtracting the difference count value from a previously-derived control count value, and for substituting the result to form the current control count value.

5. A frequency synthesiser comprising: an oscillator having its frequency controllable by a control signal; and a control loop for comparing the frequency of the oscillator with a required frequency and generating the control signal for controlling the frequency of the oscillator, the control loop including digital storage means for storing control data representing the required frequency adjustment to the oscillator, and a digital to analog converting means for converting the control data to form the control signal.

6. A frequency synthesiser according to claim 5, wherein the digital storage means comprises a latch arrangement.

7. A frequency synthesiser according to claim 5 or claim 6, wherein the digital storage means is arranged to store a value derived from a representation of the oscillator frequency subtracted from a representation of the required frequency.

8. A frequency synthesiser substantially as hereinbefore described with reference to the accompanying drawings.