GB2226928A - MAC to digital multiplex video signal transcoder - Google Patents

Description

1 TRANSCODING CIRCUIT This invention relates to a circuit for transcoding

a video signal from time multiplex analog component form (MAC) into digital.component form.

For the transmission of colour television signals, particularly via satellites, time multiplex processors are known.in which the components of the colour television signal are transmitted as analog signals and associated audio signals. Variants of this process, known as a MAC process, essentially differ by the nature of the audio signal transmission. Thus, for example, in the D-MAC process and the D2- MAC process, the audio signals are in digital form. In the MAC process the video signals are time compressed and transmitted as luminance and colour difference signals, the compression ratio for the colour difference signals being 3:1 and for the luminance signal 3:2 One line of the time-compressed luminance signal and one line of alternate time-compressed colour difference signals is transmitted during each successive line period of the standard television system.

Due to the integrated sound transmission, which allows up to eight sound tracks in the D2-MAC process, the MAC process is also advantageous for transmission between studios. However, the MAC signals are not usually in a suitable form for further processing, because within studios other signal formats are preferred, e.g. digital component signals according to the CCIR standard 601-1. which are also known as 4/2/2 signals.

The object of the present invention is to provide a circuit for transcoding a video signal from time multiplex analog component form (MAC) into digital component form.

Accordingly, the present invention provides a circuit for transcoding a video signal from time multiplex analog component form (MAC signal) into digital component form. wherein in operation of the circuit the MAC signal is converted to digital form in an analog to digital converter, following such conversion the luminance and colour difference signals are written into respective random access memories with a first clock frequency equal to the analog to digital conversion frequency and read out from such memories with respective clock frequencies which are lower than the first clock frequency, and the signals read out from the random access memories are multiplexed to form a digital multiplexed signal.

The circuit according to the present invention has the advantage that transcoding is possible with limited expenditure. A further advantage is that the transcoding causes no deterioration of the signals beyond that which in any case takes place due to the analog/ digital conversion required for time decompression.

An embodiment of a circuit according to the present invention will now be described by way of example with reference to the accompanying drawing, the single figure of which is a block diagram of a transcoding 5 circuit.

Referring to the drawing, a D2-MAC format signal is supplied at an input 1 to the transcoder shown in the drawing. A known type of clock regenerator 2 obtains various synchronous clock and switching signals from the D2-MAC signal. Thus, for example, a clock signal T whose frequency is 20.25 MHz is generated for analog/digital conversion of the input signal in an A/D converter 7. A further signal Ta controls a gate circuit 3, which is rendered conductive during the times when the D2-MAC signal contains a digital sound component. By means of a driver 4 the digital sound components thus selected by the gate circuit 3 are supplied to an output 5 from which they can be supplied for further processing, for example for mixing with other sound signals.

The clock regenerator 2 also controls a demultiplexer 6 to which are supplied the output signals of the A/D converter 7. The demultiplexer 6 has five outputs. in each case 8 bits wide, to each of which is connected a respective RAM 8 to 12. The control by the clock regenerator 2 takes place in such a way that the luminance signal is written line by line alternately into the RAMs 8 and 9, whilst the colour difference signals Y are written line by line cyclically into the RAMs 107 11 and 12. As a result of the A/D conversion or sampling frequency of 20.25 Mz, there are 697 8 bit words for one line of the luminance signal, whilst one line of each colour difference signal comprises 349 8 bit words.

Writing into the RAMs 8 to 12 takes place with a frequency equal to the A/D conversion.frequency of 20.25 MHz, for which purpose suitable writing clock signals Tw are produced in a circuit 16. A read/write enable circuit 13 provides for further control of the RAMs 8 to 12. In addition, the circuit 16 produces clock signals Trl and Tr2 for reading out the luminance and colour difference signals respectively in the time base according to CCIR standard 601-1. Since, according to the latter, the sample frequency Trl for the luminance signal is 13.5 MHz and the sample frequency TR2 for the colour difference signals is 6.75 MHz, the luminance signals read out from the RAMs 8 and 9 are decompressed by the factor 3/2, whilst the colour difference signals read out from the RAMs 10 to 12 are decompressed by the factor 3, i.e. they once again correspond-to their original time sequence.

The decompressed luminance signal Y, which is obtained by reading each RAM 8 and 9 while the other is being written into, is supplied by the RAMs 8 and 9 to a multiplexer 14 which is also controlled by the read/ 30- write control circuit 13 such that at the output of the 4 multiplexer 14 the decompressed luminance signal from the RAMs 8 and 9 appears alternately.

There is a further multiplexer circuit 15 for the colour difference signals CR and CB and this circuit combines two multiplexers, so that each of the signals read out from the RAMs 10, 11 and 12 can be supplied to the two outputs of the multiplexer circuit 15. The multiplexer circuit 15 and stores 10 to 12 are con- trolled with the aid of the read/write control circuit 13 in such a way that there is a colour difference signal CR and a colour difference signal CB simultaneously in each line period. This is achieced by controlling the two demultiplexer switches and the RAMs 10 to 12 such that as each fresh line from the demultiplexer 6 is read into one of the three RAMs 10 to 12 the immediately preceding two lines stored in the other two RAMs are simultaneously read out. Thus the contents of each RAM 10 to 12 is read out twice during consecutive line periods.

The outputs of.the multiplexer circuits 14, 15 are supplied, across circuit 17, 18, 19 for adapting the amplitudes of the signals Y, CR and CB to CCIR standard 601-1, to a further multiplexer 20. Advantageously the circuits 17, 18 and 19 can be implemented by ROMs. and/or PROMs. The multiplexer is controlled by a clock generator 21, which is synchronized by the clock regenerator 2 and generates a 27 MHz clock signal which is supplied to the multiplexer 20. The multiplexer 20 is controlled in such a way that it delivers an 8 bit wide data word at its output 28 for each individual pulse of the 27 MHz clock signal, every other word being a luminance value and the interme- diate words being colour difference values taken from CR and CB alternately.

If necessary, the amplitude-adapted signals Y9 CR and CB can also be supplied-via digital/analog converters 22, 23, and 24 to further outputs 25, and 27.

Claims (6)

1.A'circuit for transcoding a video signal from time multiplex analog component form (MAC signal) into digital component form, wherein in operation of the circuit the MAC signal is converted to digital form in an analog to digital converter, following such conversion the luminance and colour difference signals are written into respective random access memories with a first clock frequency equal to the analog to digital conversion frequency and read out from such memories with respective clock frequencies which are lower than the first clock frequency, and the signals read out from the random access memories are multiplexed to form a digital multiplexed signal.

2. A circuit as claimed in claim 1, wherein the clock frequency used to read out the colour difference signals is less than the clock frequency used for reading out the luminance signal.

3. A circuit as claimed in claim 2, wherein the first clock frequency is 20.25 MHz, the clock frequency used for reading out the luminance signal is 13.5 MHz and the clock frequency used to read out the colour difference signals is 6.75 MHz.

4. A circuit as claimed in claim 1, 2 or 3, wherein prior to analog to digital conversion the MAC signal is supplied to a clock regenerator which generates signals for controlling a gate circuit for digital audio signals, a clock signal for the analog to digital converter., and control signals for a demultiplexer by which the luminance and colour difference signals are directed into the respective random access memories

5. A circuit as claimed in claim 1, 2, 3 or 4, wherein the signals read from the random access memories are supplied across a first multiplexer, amplitude- adapting circuits and a second multiplexer to form the digital multiplex signal.

6. A circuit as claimed in claim 1, substantially as described with reference to the accompanying drawing.

is i Published 1990 at The Patent Office. State House, 6671 High Holborn. LondonWC1R4TP.Puither copies maybe obtained from The PatentOlficeSales Branch. St Mary Cray. Orpington. Kent BR5 3RD Printed by Multiplex techruTaes ltd. St Mary Cray, Kent, Con. 167