GB2221328A - Emulative tester - Google Patents

Abstract

A microprocessor-controlled emulative tester includes a programmable state machine (Fig. 7) for emulating bus cycles or other complex signals of a system under test. The state machine comprises a RAM 200 with latched inputs and outputs, and sequences through preloaded states under clock control. The RAM may be split into two banks, one active while the other is inactive or being loaded, to facilitate breaking the state diagram into working subsets and to allow seamless threading of valid output information. Other features include wraparound address bits, immediate response output capability, multiplexed inputs selected from external, internal, or hardwired ones and zeros, and complete programmability. <IMAGE>

Description

TES APPARATUS HAVING A PROGRAMMABLE STATE MACHINE FOR EXlJIATTNG ELECTRICAL SIGNALS OF A SYSTEM UNDER Field of the Invention The present invention relates to emLlative-type test apparatus in general, and in particular to a test apparatus having a programmable state machine for applying electrical signals to and capturing electrical signals from a system under test.

Background of the Invention One of the most effective techniques for testing and troubleshooting microprocessor-based systems is led emulative testing. This type of instrument tests the system from the inside out, that is, beginning with the system kernel, and also can test a system in which the kernel is dead. Emulative testers, so called because they emulate signals at well-defined interfaces between parts of a circuit, and especially at kernel-related devices that are capable of reading and writing data to other devices in a given system, send out Jmown stimuli to devices in the system and measure their responses. Not only can emulative testers verify prefer functionality and operation of the system under test, but also they can diagnose and locate faults within the system.

flrnilative testers fall into several categories, of which the two most common are bus cycle emulators and memory device emulators. A bus cycle emulator, an example of which is described in U.S. Patent No.

4,455,654 issued to X.S. Bhaskar et al. and assigned to John Fluke Mfg.

Co., Inc., is itself a microprssor-based system and is connected in place of a microprocessor in a system under test. The bus cycle emulator is capable of reading and writing to any addressable device or memory location, generating probe#synchronizing signals during bus cycles of interest, and providing an interpretation of test results, allowing a user to thoroughly exercise every node in the system under test. However, because each type of microprocessor has its own characteristics and pin configurations, different bus cycle emulators must be designed for each type, resulting in a multitude of special bardware modules, called pods, which contain microprocessor-specific information.As new microprocessor types become available, new bus cycle emulator pods must be designed. Also, because the bus cycle emulator pods operate in a so-called bus-access mode requiring a bus switch, the increasing complexity and higher clock speeds of newer microprocessors make it increasingly difficult and uneconomic to design new bus cycle emulator pods using this technology.

Memory device emulators, such as that described in pending U.S.

Patent Application No. 07/158,223, filed February 19, 1988, also are microprocessor-based systems which are connected in place of the system under test's memory device. Memory device emulators have the advantage of requiring only a very small specific hardware module for each type of microprocessor; however, they are more limited in their test capabilities than bus cycle emulators.

What is needed is a system for emulating bus-level behavior of micropr#cessors and computer backplanes, and in particular a bus cycle emulator in which the test equipment mimics the "read" and "write" bus operations and appears to be the system under test's own microprocessor without requiring a new hardware design for each microprocessor, and without being limited by a bus switch.

Also, with the growing ccnrrplexity of electronic circuits, the technique of emulative testing, traditionally applicable to microprossor- and bus-based systems, is increasingly applicable to other types of systems as well, through the emulation of electrical signals at other well-defined interfaces. It is also therefore desirable to be able to emulate other types of complex digital signals as well.

Summary of the Invention In accordance with the present invention, a microprocessor- controlled emulative tester includes a programmable state machine for emulating bus cycles or other complex signals of a system under test.

The state machine emulator comprises a randamaccess memory (RAM) with latched inputs and outputs, and sequences through preloaded bus states under control of a clock synchronized with the clock of the system or unit under test (hereafter referred to as UUT). The state machine emulator receives status inputs from the UUT, and generates in response to such status inputs control signals to control the UUT bus. This includes the capability of providing immediate response outputs that are needed within a given clock cycle and cannot wait for the normal sequencing of the state machine, thereby to handle the a#rOnous transitions that occur for many different kinds of bus cycles.The state machine emulator also controls sending predetermed address and data information to the UUT for performing "Write" and "Read" cperations.

The state machine emulator emulator in accordance with the present invention incorporates many features to provide flexibility and programmability in as efficient a manner as possible. It can be appreciated that a state diagram for such a state machine can be very cxalçlex and have hundreds of states. However, in the present invention, the state diagram is broken into working subsets to simplify operation. Inputs to the state machine are multiplexed to provide address bits from several sources, including inputs from the UUT, and internal bits from the state machine itself or from the controller.

Hard-wired ones and zeros may also be provided to selectively disable or mask wr inputs, or to facilitate variable-length microinstructions.

In addition, the state machine RAM itself provides certain address bits, wrapping them around to the input.

The state machine RAM may be split into dual banks of RAM so that one bank can provide activity output while the other bank is being loaded. The microde being loaded into the state machine RAMS can be dynamically altered to suit the situation, such as where successor states need to be changed or where stay activity needs to be generated while other tests or tasks are being formulated.

It is therefore one object of the present invention to provide a novel emulative tester for electrical systems.

It is another object of the present invention to provide a test apparatus having a proamable state machine for emulating bus cycles or other complex signals of a system under test.

It is a further object of the present invention to provide a state machine for which the state diagram is broken into working subsets.

It is an additional object of the present invention to provide a RAM-based state machine in which the RAM may be split into dual banks to facilitate efficient operation.

other objects, advantages, and attainments of the present invention will become cbvicus to those skilled in the art upon a reading of the following description when taken in conjunction with the accatanying drawings.

Brief Description of the Drawings FIG. 1 is a generalized block diagram of a test apparatus in accordance with the present invention, configured to emulate bus cycles at a microprooessor socket; FIG. 2A shows functional signal groups associated with a microprocessor, using an Intel 80386 as an example; FIG. 2B is a ladder timing diagram showing various bus cycles and idle states with non-pipelined address for an 80386 microprocessor; FIG. 2C is a ladder timing diagram showing transitioning to piplined address during a burst of bus cycles for an 80386 microprocesor; FIG. 3 is a simplified block diagram of a RAM-based state machine emulator in accordance with the present invention;; FIG. 4 is a block diagram of a RAM-based state machine emulator having immediate response capability in accordance with the present invention; FIG. 5 shows an input multiplexer arranged to select fixed logical ones or zeros as address bits for the state machine emulator; FIG. 6 shows an input multiplexer in an alternative arrangement to select logic levels provided by the state machine emulator; FIG. 7 is a detailed block diagram of state machine emulator having dual RAM banks in accordance with a preferred eebodiment of the present invention; FIG. 8 is a diagram of an example of dynamically loaded micrscode for bus emulation by dual RAM banks; and FIG. 9 is a detailed schematic of a switching circuit to control switching of the dual RAM banks of FIG. 7.

Detailed Description of the Invention Referring to FIG. 1, a generalized block diagram of an emulative test apparatus in accordance with a preferred embodiment of the present invention includes a mainframe 10 electrically connected via a nntltiple-lead cable 12 to an emulator module or pod 14 (shown enclosed by a dashed line), which in turn similarly is electrically connected via a multiple-lead cable 16 to a unit under test (UNIT) 18.Pod 14, the details of which are fully described hereinbelow, is capable of testing different microprocessor-based systems or buses, including ccnpxrter badkplanes and other systems with complex signals, and contains retargetable circuitry and an interface adapter and plug/socket for any selected specific target UUT connector style.

Changes necessary to adapt to different target Wrs are well within the purview of those skilled in the art, so no attempt will be made herein to enumerate all of the different possibilities. Also, it should be pointed out that while the specific embodiment described herein for the purpose of understanding the invention includes a microprocessor socket into which cable 16 is plugged, cable 16 may include any suitable connection arrangement to connect to appropriate points in a particular system under test.

wr 18, as shown, is exemplary of any of a wide variety of niicroprscssor-based systems or other systems with complex signals which may be tested using the system and techniques of the present invention, and only the central or core section will be discussed herein. In the case of a microprocessor-based system, the core section typically includes a wr kernel comprising a microprocessor 20, a read coily memory (RaM) 22, and a random-access memory (RAM) 24 interconneted by data signal lines 26, address signal lines 28, and status and control signal lines 30. A UUT clock circuit 32 is connected to the microprocessor 20.The wr microprocessor 20 is shown as a dashed line to indicate that the microprocessor may be either disabled or removed from its socket. One end of cable 16 may suitably have a plug or socket appropriately configured to match the pin configuration of the target UUT microprocessor.

The other end of cable 16 is connected to an input/output interface (I/O) 40 located in pod 14. Cable 16 may suitably include lines for transmitting data, address, status and control signals, and together with I/O 40 provides biedirectional communication between pod 14 and UUT 18. I/O 40 includes inppt/output buffers and drivers, protection circuits to protect the pod 14 from over-voltage conditions, and certain target-specific circuits, such as an EPROM containing target-specific information, combination logic circuits, specially tristated outputs, logic level conversions, and signal synchronization.

Operation of pod 14 is controlled by a controller 42, which ccmmunicates with mainframe 10 over cable 12. Controller 42, which also may be referred to as the pod kernel, comprises a microprocessor, a RDM, a RAM, and associated logic circuitry for directing and coordinating operations within pod 14. During the power-up and initialization sequence, the pod kernel reads the information from either the mainframe 10 or from the aforementioned ES6KXM to configure the pod 14 for use with some target uur. Code derived from this information is then loaded as needed into a state machine RAM to be discussed shortly.

Mainframe 10 may suitably include a microprscessor-based control and measure system, as well as a keyboard and display device for interaction with a human operator. Examples of canmercially-available equipment representative of a mainframe 10 are the 9000 Series Micro- System Troubleshooters and 9100 Digital Test Systems manufactured by John Fluke Mfg. Co., Inc.

Pod 14 emulates microprocessor bus activity, or other complex signals using state sequences which represent one or more bus cycles or sequences of operations. It performs operations in response to commands from mainframe 10 and reports the results or errors, if any, upon completion. Between mainframe commands, pod 14 performs a standby activity, such as a "read" bus cycle so that the UUT 18 effectively sees appropriate signal activity that is innocuous so as to not interfere with testing and troubleshooting. The emulation and functional testing is carried out by state machine emulator 50 and its associated circuits 54-70 under control of controller 42.

Briefly, state machine emulator 50 is a RAM-hauxsd state machine that stores in addressable storage locations state information that represents one or more bus cycles or sequences of operation initially applied as code from controller 42, and sequences through states in synchronism with a clock signal fram clock 52, setting control outputs in response to status inputs applied as RAM addresses.

The status inputs for state machine emulator 50 are taken from the pins of microprocessor socket 20 of UUT 18 and from internal sources of pod 14, and applied via cable 16 and a status signal/clock buffer 40-1 of I/O 40. An example of typical microprocessor signals is shown in FIGS. 2A-2C, wherein an Intel 80386 microprocessor is chosen to be the example. Status signals are indicated in FIG. 2A with an "S." The status signal/clock buffer 40-1 in the preferred eneodient of the present invention is a hybrid circuit containing a protection network, a level translator, and an ECL (emitter#oupled logic) buffer.

Buffer 40-1 serves to reduce loading effects on high-speed signals souroed by UUT 18 and to convert Tm logic levels to the ECL levels required by pod 14. One of the most critical of the input signals is the microprocessor clock fran UUT clock 32 which is fed through to generate pod clock 52, and hence, allow the state machine emulator 50 to operate at the UUT clock speed. In the preferred embodiment, the status signal/clock buffer 40-1 has a high impendance to present as light a load to the UUT circuits as possible, and further has a propagation delay minimized to approximately two nanoseconds.

Clock 52 controls the rate at which the state machine emulator 50 changes states, and also furnishes clock signals (CLK) for operation of the various clocked devices within pod 14. Clock 52 is generated from the wr clock as described above. However, if no wr clock is available for external synchronization, the state machine emulator 50 is able to run synchronized to an internally-generated clock of pod 14.

A synchronized clock signal is available frsm clock 52 as an output to UUT 18. Also, if no UUT clock is available, controller 42 detects the absence thereof and reports a clock failure condition to mainframe 10.

Status latches 54 are loaded with expected status values, depending on the sequence of signals being emulated, by controller 42, and at a predetermined state of the state machine emulator 50, the status input signals coming over the Status Lines In from buffer 40-1 are cxxgxnned with the expected values. If a mismatch occurs, an error output is available to state machine emulator 50 and to controller 42, which in turn notifies mainframe 10.

There are several different types of outputs available from the state machine emulator 50 for emulating bus cycles or signal sequences in the wr 18. These include immediate response control outputs, direct control outputs, and registered control outputs from control latches 56. Immediate response control outputs are outputs that may change in response to a change in an immediate input during the state in which the immediate input is sampled, e.g., the present state, rather than waiting for a next clock cycle. An example of such an immediate input is the READY# signal for the 80386 microprocessor.

Direct control outputs change during the state following the state in which the inputs are saapled, i.e., the next state. Both immediate response control outputs and direct control outputs are outputs that are stored as microcode in the RAM-based state machine emulator 50.

Immediate response and direct control outputs may be used for internal state machine emulator control as well as being output to the target UUT via tri-stated buffers 40-3. Outputs from control latches 56 include a group of signals called control group A via tri-stated buffers 40-4 and a group of signals called control group B via tristated buffers 40-5. Control group A or B outputs may change only as a group during a state sequence; however, not all outputs must change on every state of a sequence, and some may need to change one or more times during a state sequence. Control group A outputs are controlled by immediate-response control outputs while control group B outputs are controlled by direct control outputs. Control latches 56 may be loaded by controller 42 prior to the beginning of a test sequence.

An address lat#counter 58 provides stimulation to the wr appropriate to such signals as address signals via tri-stated buffer 40-6. Such address information is loaded into the address latch/counter prior to initiating a state sequence. For example, for a Write or a Read bus cycle, the state machine emulator 50 will establish the required bus control, and also cause address latch/counter 58 to place the desired memory address to be written to or read fran on the address bus. Additionally, address latch/counter 58 is a bidirectional counter which may be used for operations such as RAM testing where each memory location of the RAM is addressed in sequence over the address range in both directions. In such RAM testing, clock signals are applied frum clock 52 to the CLK input of address latch/conter 58.

Both the address and data counters are maskable bit by bit. That is, any given bit may be masked so that it will be ignored if so desired. A masked bit is held static during counting. Carries and borrows in the count process are passed on by the masked bits to the next urmasssed bit. This greatly speeds up ramp (count up or count down) functions since a full ramp through 32 bits would involve over four billion cycles. Ramps can be done on selected bits of the address or data buses.

Input data latches 60, which may suitably be operated as first-in, first-out (FIFO) devices, receive signals such as UUT data signals via a buffer 40-7, and such data is latched under control of the state machine emulator 50, for example, during a read operation of a particular bus cycle. Controller 42 reads the data latch 60, and may send the data on to the mainframe. Outgoing data to the wr data bus for write operations is preloaded into output data latch/counter 62 and sent out via data buffer 40-8 at the appropriate time under control of state machine emulator 50.Additionally, data patterns or count data may be loaded into the output data latch/counter 62 and compared with inoaning data in input data latch 60 by means of a comparator 70. This ccmparison operation is achieved by comparing selected bits in latches 60 and 62 simultaneously on a bit-by-bit basis. If an input value fails to compare with an expected value, an error signal is generated and sent to state machine emulator 50 and to controller 42. A pseudorandom number generator 64 is also connected to output data latcc/counter 62 for generating pseudo-random numbers for #n#tory testing via data buffer 40-8 and the data bus.One such system for memory testing and capable of being implemented in the system described herein is the SN prsbabalistic test described in U.S. Patent No.

4,715,034 issued to David M. Jacobson and assigned to John Fluke Mfg.

Co., Inc.

Logic level latch 66 permits logic levels to be output and input via buffers 40-9 and 40-10, respectively. The output logic levels for testing the UUT 18 are loaded into latch 66 by controller 42. Input logic levels are read by controller 42.

An interrupt detector 68 monitors selected signals of the UUT via buffer 40-11, and when a signal such as a microprocessor interrupt oocurs, notifies controller 42.

State machine emulator 50 will now be described in greater detail, and a simplified block diagram thereof is shown in FIG. 3. Basically, state machine emulator 50 is a modified state machine knawn in the art as a Mb21y machine in that outputs are a function of both the present status inputs and present machine state.

The basic state machine shown in FIG. 3 comprises a RAM 100, an address latch 102, and an output latch 104. Address latch 102 latches the RAM addresses in order to prevent race conditions (two or more transitions oocurring simultanecusly or nearly simultaneously), glitches, and other unwanted intermediate states. Output latch 104 performs a similar function for output signals. One or more of the RAM 100 outputs are applied in wraparour,d fashion to the input of address latch 102, so that in addition to providing control outputs via latch 104 to the wr 18, RAM 100 functions as a next-state decoder.Bus state sequences comprising both next-state and present state output information are loaded into addressable storage locations of RAM 100 by the pod controller 42. Both latches 102 and 104 are updated on each clock cycle provided by clock 52. While both latches 102 and 104 are provided for stability, the effect of having two latches is that the output provided by latch 104 is delayed one clock cycle from the inputs latched by latch 102.

Buses and micr#rocessors may have a large number of status inputs which would result in excessively large requirements for RAM 100 to represent all possible states. In addition to status inputs of the target WT, signals internally generated by pod 14 must be represented as well, placing a further demand on memory size. To reduce the number of RAM locations required, input multiplexers 106 are employed to select among groups of inputs. These inputs may include not only microprocessor status inputs, such as those from a 32-bit micraprocessor, but internal inputs as well. Internal inputs will be dieazsed later.In a preferred embodiment of the present invention, the wraparound inputs from the outputs of RAM 100 provide the higherorder bits of the address to be latched into latch' 102; however, it should be understood that the wraparcund inputs could provide any desired number of bits and in any order. Selection by multiplexers 106 is controlled by selection signals applied from RAM 100. Thus it can be discerned that a very flexible and programmable state machine may be implemented for emulating complex behavior of any digital signals, including those for microprocessors and computer backplanes.

For both control and status signals associated with mic m processors, there is a type of signal that may be referred to as "immediate." An immediate signal is involved in a state or output transition within the present clock period or machine state as opposed to waiting for the next state. A traditional example of immediate signals is the READY&num; signal for the 80386 microprocessor. The READY# line is sampled at the final edge of the second phase of Cull2 of state T2 (refer to FIGS. 2B and 2C). If READY# is asserted, then the first phase of state T1 may begin, a new address is generated, and control signals like AD6# are asserted.If READY&num; is not asserted, then state T2 is repeated with no change in the address or AD6#. That is, there is not a complete CLK2 state between the sampling of READY# and the assertion of control signals to allow the state machine to make a state transition - an immediate response is needed.

The state machine of the present invention is modified as shown in FIG. 4 to be able to respond to immediate inputs, and thereby to handle the asynchronous transitions that occur for many different kinds of bus cycles. We will assume that one of the input mwltiplexers 106 selects an immediate response input and applies it to address latch 102. RAM 100 is programmed with two sets of outputs to respond to the immediate response input wherein one set of outputs assumes the presence of the immediate response condition and the other set of outputs assumes the absence thereof.Both sets of outputs are provided to a multiplexer 108, the selection of which is controlled by the immediate response input line. That is, if an immediate response condition is latched by latch 102, multiplexer 108 selects the RAM 100 set of outputs that assumes the presence of an immediate response condition. On the other hand, if no immediate response condition is present at latch 102, then nultiplexer 108 selects the RAM 100 set of outputs that assumes the absence of an immediate response condition. Of course, where n immediate response inputs are used, MUX 108 would have to select from 2n possible outputs, some of which may not be in RAM.

The selected set of outputs is latched by output latch 104. A slight delay 'd' is built into the clock line, indicated by delay buffer 110, so that an immediate response output to an immediate response status input is provided within the same clock cycle. The delay 'd' must observe the following: RAM address change and output change time + MUX delay > d > MUX control delay. That is, the clock applied to output latch 104 must be delayed just long enough to allow for the address latch 102 clock-to-output delay plus the selection time of nnrltiplexer 108 and the setup time of output latch 104; however, it must be less than the time it takes for the outputs of RAM 100 to change.

The privyprograirmable state machine in a proposed commercial anbodiment of the present invention forms the RAM address of the next state to be executed by concatenating two bits from the current state's control output with six bits taken frsm six input multiplexers. That is, an eight-bit address is formed by two higher-order bits taken from the current state output, and the six lower-order bits are provided by each of six input multiplexers. In same instances, a faulty UUT can prevent the state machine emulator from generating the sequences of control outputs desired or expected.In such cases, it would be desirable that the state machine emulator be able to selectively ignore status inputs from the UUT which may be the sources of faults. Particularly, it would be desirable that the inputs to be ignored can be dynamically selectable by the operator of the equipment. Accordingly, the input nultiplexers 106 may be used to selectively disable inputs to be ignored.

With reference to FIG. 5, each input multiplexer 106' is provided with two additional inputs, one of which is a fixed logical one, and the other of which is a fixed logical zero. Controller 42 loads the RAM of state machine emulator 50 with program instructions to ignore the particular inputs to be ignored. This is achieved by replacing the affected input multiplexer selection field in the microode with a new value that causes the associated input multiplexer to gate a logical one or zero rather than a UUT status input. The ability to dynamically select logic states to override or replace UUT status signals has several advantages.A very flexible system is provided, since any or all of the input rmiltiplexers may at any time during a sequence be instructed to select as an address bit a specific logic level, either high or low, rather than a UUT status signal. Also, no additional gate delays appear in the RAM address path, allowing the state machine emulator to operate at a higher frequency than would be possible using traditional AND gates or some other type of logic gates to disable the wr status inputs.

FIG. 6 shows an alternative arrangement wherein each input multiplexer 106" is provided with an input fed directly fran a control output of the state machine emulator. In this arrangement, the state machine emulator itself provides the desired logic level. It should be noted that a system combining the arrangements of FIGS. 5 and 6 could be provided as well.

An important aspect of the present invention is that in addition to selectively disabling or "masking" UUT status inputs, the arrangements of FIGS. 5 and 6 facilitate implementation of variablelength microinstructions. The state machine emulator of the present invention uses a large number of UUT inputs to simultaneously determine the next state to be executed. For example, it was indicated above that up to six multiplexers could select among several inputs to provide six bits of the state machine RAM address of the next microinstruction. That is, each state may have up to 26 successors (the state's "successor set") which may be reached in one clock cycle.

However, on the average, most states have only one or two successors.

The arrangement of FIG. 5 reduces RAM usage since no memory locations have to be set aside to account for unused inputs. Thus, if a state has only one successor (always branches to a fixed following state), all multiplexer select codes are assigned so that a fixed binary value selected from the fixed logic ones and zeros forms the next address.

If only one or two inputs are required to determine the next state address, the multiplexer select codes for the unused inputs in that state are assigned so that fixed values are substituted for the "don't care" or unused inputs. The effect of using the fixed multiplexer inputs in this manner is to allow each microinstruction, or state Successor set, to vary in size from one to sixty-four instructions.

In state machines of the type employed in the present invention, the code which represents the outputs of the state machine during a particular state, e.g., state "q", is copied into the successor sets of all states which transfer control to "q". The only unique address which can be identified with state "q" is the address assigned to the successor state of "q". The bit pattern placed in the micooaddress field of state "q" is the higher-order several bits of the address assigned to the successor set of "q", and the lower order address bits are formed by the state machine inputs themselves. The variable-length microinstructions used in the present invention require that an important restriction on state address assignment be observed.If state "q" transfers control to n successors, the address al assigned to the first member of the successor set of "q" must be zero mcdulo 2n so that a1=0 mod 2". As n gets large, assignment restrictions become severe in that it becomes difficult to assign a legal address in a fixed-size RAM. As will become apparent, RAM usage can be minimized through state address selection by appropriate use of the input multiplexers.

When states do not use inputs on one or more of the lower-order address-bit input multiplexers, the state's successor set will not occupy all of the locations from the successor set base address al to the end of the successor set at address a+2n-1. The unused locations will never be transferred to by a transfer of control from state "q", which means that the other (smaller) state successor sets can be packed into the unused locations.A state machine memory allocator assigns locations to states in decreasing order of successor set size, and from the bottom (location O) of the RAM to the top so that states with the largest memory requirements are satisfied first, and smaller states can be used to fill unused holes in larder successor sets. The sizes of state socoessor sets themselves are minimized by judiciously choosing the multiplexers to which various UUT inputs are assigned. The choice should be guided by the criterion that the inputs which are most often used in conditional state transitions should be preferentially assigned to rrrultiplexers which generate lower-order address bits.This guarantees a neaos < ptimal multiplexer assignment when applied to a particular set of state machine programs or descriptions.

A state diagram adequate for complete emulative testing is extremely complex. For example, a state diagram for an Intel 80386 processor has over a hundred states. Due to the expense and power requirements of high-speed RAM, it is impracticable to provide enough RAM to store the entire state diagram of any real microprocessor. Our solution to this problem is to provide enough RAM to store a working subset of the state diagram.

A working subset of the state diagram typically consists of all states for either a full READ or WRITE operation. A working subset may include the states for multiple independent READS, WRITEs, or other bus operations. High-speed RAM testing such as the Jacobson 5N probabilistic test discussed earlier uses accesses (desired bus operations) which include combined READ and WRITE cycles in a working subset. Working subsets are loaded on demand based on information stored in slower, but more economical RAM resident in controller 42.

To facilitate operation using such working subsets, the state machine emulator of the present invention is implemented with dual banks of RAM as shown in FIG. 7. This arrangement allows the state machine emulator 50 to continuously emulate bus cycles or generate innocuous bus activity using one bank while controller 42 loads the other bank with the microcode for a different bus cycle. Once an access is required, state machine emulator 50 can then switch banks without any delay or pause in the bus cycle emulation seen by the UUT; that is, the UUT sees a "seamless" sequence of valid bus cycles. The request to switch banks is generated by controller 42, which runs asynchronously with respect to the state machine emulator.Special logic circuitry synchronizes the request and provides it to the currently executing working subset, which causes the transition to occur such that the code is threaded seamlessly fran one RAM bank to the other. This allows the use of relatively small RAM devices which are very fast, as will be seen shortly. only one or two W T accesses need to be loaded at one time.

Once started, emulation can be continuous without idle states even though different accesses are requested. Also, microcode in the working subsets can be combined dynamically while maintaining continuous legitimate output (valid bus cycles).

When a UUT access is completed, the emulation continues by switching banks again to execute a "standby cycle" until the next access request is made. The standby activity typically consists of some default bus cycle, such as an idle cycle or a READ cycle with other supporting cycles, such as a bus arbitration (e.g., "hold acknowledge" and "bus grant") cycle, or an interrupt acknowledge cycle.

The standby activity microcode has no knowledge of the accesses to which it may be threaded in the other RAM bank; it simply knows about some absolute RAM addresses to jump to in the event of a bank switch.

These absolute addresses are entry points to the different accesses (the accesses Share the same entry point absolute addresses). To the standby activity, the access would seem to be a subroutine except for the fact that the standby activity never knows which "subroutine" it calls.

An access is typically some kind of READ or WRITE bus cycle or a combination of READ and WRITE cycles. Often, fields in the micoocode for an access are modified before such dynamically altered microcode is loaded into the second RAM bank, depending upon the exact cycle desired (e.g., according to data size, bus size, address space, and a number of other factors peculiar to the situation). Similar to the standby activities, the access microcode has no knowledge of the standby activity to which it will be threaded in the other RAM bank; it simply knows about sane absolute addresses through which the microcode is threaded. The absolute addresses are the entry points of whatever standby activity is loaded into the other bank of RAM.

When a sequence of microcode is to be loaded into a RAM bank, whether an access or standby activity, its entry states must be loaded at their associated absolute locations. An entry state provides a valid bus cycle, and a branch into the rest of the microcode sequence.

The microcode sequence itself may be loaded anywhere in the free memory of the RAM bank as determined by the memory allocator mentioned above.

When a bank switch is to occur and the currently executing microode sequence branches to an absolute address, a microode sequence with an entry state for that absolute address must be present in the other RAM bank in order to sustain the continuous valid bus cycles.

FIG. 8 shows a diagram of two possible RAM bank images and the branches between the segments of their microode. In the example shown here, the standby activity consists of an interrupt acknowledge cycle, a hold acknowledge cycle, and a default read.

In a RAM-based state machine emulator in accordance with the present invention, it is important that the RAM be able to operate quickly. For example, to emulate a 25-megahertz Motorola 68020 mirraprocessor, the state machine must be able to run at 50 megahertz, which means that the state machine emulator 50 must cycle in 20 ndnoseonds. However, presently-available RAMS capable of sustaining such perfornance consume considerable power and are quite expensive.

To provide the desired speed while overcoming the problems attendant with large, fast RAMs, the preferred embodiment of the present invention incorporates two banks of 256 X 96 bits of dual-ported memory to form the RAM for the state machine emulator as shown in FIG. 7. One of the two banks of RAM is active at any given time as mentioned above, sequencing thtcugh bus states and generating outputs for the target UUT, while the other bank of RAM is available for loading new sequences by controller 42. Each bank of RAM is implemented with 256 X 4-bit five-nanosecond ECL RAM devices, each of which nominally consumes 700 milliwatts of power, so that the 48 RAM devices required for both banks of RAM dissipate a total of about 33 watts.Thus, the capability of breaking the state diagram into working subsets as described above, as well as the advantages of both high speed and low power consusption, are attained by the use of dual RAM banks.

In FIG. 7, state machine emulator RAM 200 is split into RAM bank Y (200-Y) and RAM bank Z (200-Z). Six address bits are selected fran among wr status inputs, logic ones or zeros, or internal inputs by input nultiplexers, and applied along with two wraparound address bits fran RAM 200 to an address latch 202, in a manner as previously discussed. The selected eight-bit address stored in latch 202 is applied to a pair of address multiplexers 210-Y and 2l0-Z. An immeciiate response signal is also applied to ixr~nediate response multiplexer 208 to select the desired irmnediate response output from RAM 200 to be applied to the wr via output latch 204.Output latch 204 is shown having applied thereto a delayed clock signal CALK+ as described earlier in connection with FIG. 4. Other outputs from RAMS 200-Y and 200-Z include direct outputs via a latch 212, SME control outputs to control all of the various latches and uur interface devices as discussed in connection with FIG. 1, wraparound address bits to be applied to the higher-order bit positions of address latch 202, and a cycle finished bit to facilitate RAM bank selection. A memory bank select circuit 214, the details of which will be discussed later in connection with FIG. 9, receives the cycle finished bit and generates Y-select and Z-select signals to control switching of RAMS 200-Y and 200-Z.Controller 42 provides internally-generated addresses and chip select signals to address GXs 210-Y and 210-Z, and furnishes data and control signals to RAMs 200-Y and 200-Z and memory bank select circuit 214.

Operation of the state machine emulator having dual RAM banks is based on the fact that one RAM bank is active while the other is inactive. Typical operation is as follows: Suppose that RAM 200-Z is the active bank and RAM 200-Y is the inactive bank. Under control of memory bank select circuit 214, address MUX 210-Y selects the innernally-generated address from controller 42, and the appropriate data is loaded into RAM 200-Y. When the loading is canpleted, the controller 42 requests that the RAM 200-Y became the active bank for the duration of the sequence. The bank switch logic in memory bank select circuit 214 responds by asserting an Access Request signal which is sampled by the input multiplexer;.When the standby sequence reaches an appropriate point in the sequence, it samples Access Request and acknowledges by asserting a Cycle Finished signal (a bit in the RAM 200-Z), indicating that a bank switch may occur on the next state transition. The bank switch logic in memory bank select circuit 214 then allows state sequences to be retrieved from the newly loaded bank, RAM 200-Y. That is, RAM 200-Y becomes the active bank in performing the state machine emulator functions.When the new sequence is catplete, either through normal termination or termination by error, RAM 200-Y issues a cycle finished signal to memory bank select circuit 214, which can, if so prograrrpned, cause PA#I 200-Z to once more beck'cue the active bank.

In addition to allowing bus state sequences to be loaded "on the fly (as the state machine animator is sequencing through a set of intructions), the dual RAM bank system also allows the active bank to execute a "stand-by" sequence, such as a READ operation, to ensure that the sequence of signals applied to the wr is always valid and unlikely to change the state of the UUT in a manner so as to interfere with testing.

FIG. 9 shows the details of memory bank select circuit 214, and will be described in conjunction with the dual RAM bank state machine emulator of FIG. 7 to provide a better understanding thereof. The task of the memory bank select circuit 214 is to determine which RAM bank is in use for emulation, to moderate requests fran the controller 42, and to cause the switching to occur in synchronization with the emulation cycle based on the UUT clock (or clock 52 in FIG. 1). It is to be noted that the wr clock may be faster or slower than the pod controller clock, and the switching logic must take into account either situation.

Controller 42 writes a request (either Y REQ and/or Z REQ) to a trarwarZ latch 300-Y or 300-Z just as it would write to ary memos location. The existence of transparent latches 300-Y and 300-Z guarantees that in the case of a slow wr, the request will be seen an acknowledged. Controller 42 rust then wait until the ready (RDY) signal indicates that the request is being acted upon before it can make another request. This action ensures that in cases of a slow wr clock, controller 42 does not make another request before the first request is latched into a request-perxling register 302-Y or 302-Z.The request Y REP or Z RD# is passed on to the request-pending register 302-Y or 302-Z Synchronously with the wr clock. This prevents race conditions between the controller 42 write cycle and the setup time of the reqpest-pending register. Once in the request-pending register, the request waits for a cycle finished signal fran the state machine emulator RAM indicating that the state of the RAM is at a valid bank switch transition point. The request and the cycle-finished signals are applied as inputs to AND gates 304-Y and 304-Z, which in turn provide inputs to a bank-select flipflap 306 which switches on the next wr clock.

Note that the logic is symmetrical and the "Y Select" and "Z Select" ouputs from the bank-select flip-flop 306 are crossqled to the inputs of AND gates 304-Y and 304-Z to be ANDed with the request and cycle-finished signals. Both RAM banks 200-Y and 200-Z may be used identically. A typical wr access involves the controller 42 requesting switches to both banks. ten the first switching by bankselect flip-flop 306 ours, the "uur access" begins. As soon as that cycle is finished, as indicated by a cycle-finished signal from the selected RAM bank, the second switching by bank-select flip-flop 306 occurs, reverting back to a "standby cycle" in the first bank. This allows the controller 42 to initiate a temporary bank switch lasting for only a single wr cycle in cases of a utir clock that is much faster than the controller 42 clock.

In addition to bank-select flip-flop 306 responding to pen#in'g requests to switch RAM banks, switching to a particular RAM bank may be forced by asserting a "Force Y" or a "Force Z" signal fran controller 42 to the preset and clear inputs, respectively, of the flip-flop 306.

Such forced switching may be desired at startup or to initialize a particular test.

Logic circuits 308-Y and 308-Z are connected to the reset inputs of request-pen,iing registers 302-Y and 302-Z, respectively, to clear the reqest-peeding register on the next wr clock pulse following the bank switch which it requested. The request-pending registers 308-Y and 308-Z are also cleared if a Force Y or Force Z signal is asserted.

As nentioned earlier, the controller 42 must wait until the RDY signal indicates the request is being acted upon before making another request. A logic control circuit providing the RDY signal as well as enabling the request-penng registers comprises a bistable flip-flop 310, a pair of D-type flip-flops 312 and 314 connected in tandem, an OR gate 316, and an AND gate 318. This circuitry guarantees that in the case of a fast uur clock, only one request will be seen and adknowledged for each wRrrE from controller 42.

Initially, the output of bistable flip-flop 310 is low, and hence the output of OR gate 316 is low, indicating RDY, and the output of AND gate 318 is low, inhibiting west-pending registers 302-Y and 302-Z.

Upon receipt of a low-going /WR signal from controller 42, flip-flop 310 trips, its output going to the high state, causing the output of OR gate 316 to go high, indicating /RDY (not ready). On the next wr clock, the output of flip-flop 312 goes high, causing the output of AND gate 318 to go high also, enabling the request-pending registers. On the next wr clock, the /Q output of flip-flop 314 goes to the low state, causing the output of AND gate 318 to go low, inhibiting the request-pending registers once again. The low state of flip-flop 314 /Q output is also applied to one input of flipflop 310; however, flipflop 310 does not switch states until /WR returns high.As long as /WR is still low, the output of flipflop 310 remains high and /RDY remains high. ten /WR goes high, flip-flop 310 switches states, its output going to the low state. On the next t;ur clock, the output of OR gate 316 goes low, providing the RDY signal to controller 42. The output of AND gate 318 remains low until the cycle is repeated. The requestpending latches 302-Y and 302-Z will see a high latch enable (LE) for only one wr clock cycle for each time /wR is re-asserted, regardless of the timing relationship of the wr clock to /WR.

The Access Request signal discussed above in connection with FIG.

7 is produced by logic circuit 320, which consists of an OR gate and a pair of AND gates. It can be readily discerned that either a carbination of a Y request and a Z select (not Y select) or a cattination of a Z request and a Y select (not Z select) will produce the Access Request signal.

While there has been shown and described a preferred embodiment of a test apparatus in accordance with the present invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing fran the invention in its broader aspects. Is is therefore contemplated that the appended claims will not be construed in a limiting sense and will cover any such modifications and emodimnts as fall within the true scope of the invention.

Claims (2)

1. An apparatus for testing an electrical system, ccxaprising: means for receiving input signals fran said electrical system; a state machine responsive to said input signals for producing control signals; means responsive to said control signals for applying test signals to said electrical system; and means for retrieving results of said test signals to determine faults in said electrical system.

2. A state machine, comprising: a RAM having addressable storage locations for storing predetermined information; an address latch coupled to said RAM for latching addresses of said addressable storage locations: an output latch coupled to said RAM for latching information fran said addressable storage locations; and means for causing said address latch and said output latch to be updated under clock control.