GB2219672A - Display apparatus - Google Patents

Abstract

Display apparatus comprises: (a) a first terminal means (I), for providing a clock visual output; (b) a second terminal means (II) such as a loudspeaker, for providing an audio output and a functional signal for control and/or data purposes; (c) an automaton (17), for providing an automaton display; (d) a first control means (I), for at least partly controlling said first terminal means; (e) a second control means (II), for partly controlling said second terminal means, said second control means being responsive to said first control means and responsive to the third control means (III) mentioned below; and (f) a said third control means, for at least partly controlling said automaton, said third control means being responsive to said second terminal means. The third control means may provide an interactive push button control for a user. <IMAGE>

Description

DISPiAY APPARATUS There is a continuing need and desire for novel ,display apparatus.

The present invention provides display apparatus, comprising: (a) at least one first terminal means, for providing at least one clock visual output; (b) at least one second terminal means, for providing at least one audio output and at least one functional signal for control and/or data purposes; (c) at least one automaton, for providing at least one automaton display (e.g. a bird automaton for providing at least one bird display); (d) at least one first control means, for at least partly controlling said at least one first terminal means; (e) at least one second control means, for at least partly controlling said at least one second terminal means, said at least one second control means being responsive to said at least one first control means and responsive to at least one third control means mentioned below; and (f) at least one said third control means, for at least partly controlling said at least one automaton, said at least one third control means being responsive to said at least one second terminal means.

The present invention may be embodied in any suitable manner, One kind of embodiment is a speaking or talking clock.

At least one clock visual output may comprise at least one display of time, e.g. comprising instantaneous and/or periodic time(s), Examples of clock displays are analogue or digital time displays, The at least one audio output may comprise at least one display of audio information, Such a display may comprise time statement(s) and/or other audio statement(s), e.g. an advertising, educational, or other service statement. The at least one second terminal means may comprise at least one loudspeaker, The at least one automaton may comprise a bird automaton, e.g. when the display apparatus is to be a talking clock.

First circuitry, comprising the at lest one first terminal means and ttie at least one first control means may comprise at least one random access and/or read only register ( e.g. an EPROM register). The first circuitry may comprise at least one clock means, for providing timing operation(s), e,. timings that overlap data in time domains in order to cue in and exit activities. The at least ore clock means may be set, reset, or recalibrated.The at least one clock means may comprise oscillator means. Exchan, > eable registers ( e.g. FM registers) m be provided when it is too expensive to pre-programm e.g. suniner time, leap years, public holidays, or other timed events, or whether the display apparatus requires a different frequency of operation during any part of or during all of a 24 hours day.

Second circuitry, comprising the at least one second terminal means and the at least one second control means may comprise at least one memory means, e.g.

comprising random access memory and/or read only memory. At least some information (e.g. control and/or data information) stored by the at least one memory means may be erasable or fixed. At least one memory means may be interactive or non-interactive with a user of the display apparatus, The at least one memory means may store a plurality of programs, e.g, a respective program for each day of a week or other period of time.Some examples of different memory means are: integrated circuits; laser recorded discs, e,g. a compact disc; magnetic discs, e.g. floppy or other discs; and magnetic tapes, e.g, a compact cassette tape, A 90 minute compact cassette tape may store e,g, 180 thirty second message "spots", Any message spots may correspond to predetermined time values from the initial mode of a compact cassette tape, etc, When the display apparatus is to be interactive with user(s), the apparatus may comprise any suitable peripheral(s), e.g. a bell push, a buzzer push, or a key pad, Third circuitry , comprising the at least one third terminal means and the at least one third control means may comprise at least one processor means for processing tone signals derived or outputted from audio output signals from at least one said memory means comprised by the second circuitry.

At least one of said first, second , and third circuitry may provide optional control and/or data output signals for functions not part of the display apparatus.

Such functions may serve any suitable purpose(s), e.g.

for at least partly controlling a heating system, a lighting system, or a MLUSAK audio system.

The present invention will be of especial but not exclusive interest for providing a point-of-sale or point-of-interest ability to command or encourage attention in commercial or other enterprises. The display apparatus may be an inexpensive way of researching acceptability of advertising or other marketing procedure at different places and to different auditors. The apparatus can enable access between a user and at least one other party ( e.g. in single or network use), if only e.g. to change memory(s) or discuss reactions.

In the accompanying drawings, which are by way of example of the invention: Fig. 1 shows a circuit layout portion comprising Figs. 1 to 9 and 19.

Fig. 2 shows a circuit layout portion comprising Figs. 10 to 18 and 20, the circuit layout portions of Figs. 1 and 2 being interconnected.

Fig. 3 shows power supply circuitry.

Fig. 4 shows oscillator and mains synchronisation circuitry.

Fig. 5 shows divide by 3000 circuitry.

Fig. 6 shows divide by 114140 circuitry.

Fig. 7 shows clock and timer circuitry.

Fig. 8 shows clock display multiplexer circuitry.

Fig. 9 shows clock display driver circuitry and a connection socket.

Fig. 10 shows tone decoder circuitry.

Fig. 11 shows tone identification circuitry.

Fig. 12 shows tone output circuitry.

Fig. 13 shows control circuitry.

Fig. 14 shows power supply circuitry for memory means.

Fig. 15 shows audio control circuitry.

Fig 16 shows automaton control circuitry.

Fig. 17 shows automaton driver circuitry.

Fig. 18 shows an audio cassette player for outputting tone identification signals to Fig, 10 and for outputting audio signals to Fig. 15.

Fig. 19 shows display circuitry.

Fig. 20 shows loudspeaker circuitry.

Fig. 21 is a flow sheet inter-relating Figs. 3 to 20 , to which reference should be made for considering Fig. 21.

In Fig. 3, terminals L, N enable a 240 volts AC mains supply to be coupled te mains transformer TX via pins A, D; the pins B, C of the transformer are coupled together. Pins P, R of transformer TX each provide an output of 9 volts AC of mains frequency. Pins Q,S of transformer TX each provide an output of 0 volt AC.

Components 2 to 7 convert said outputs into an output of 9 volts AC of mains frequency on line E, an output of +12 volts DC on line F, an cutput of +5 volts DC on line G, and an output of 0 volts DC on line H. Components 2, 3 are rectifier diodes. Component 4 is a capacitor.

Components 5, 7 are decoupling capacitors. Component 6 is a 5 volt regulator circuit.

In Fig. LI , oscillator and mains synchronisation circuitry acts as a mains synchronised burst oscillator, coupled to lines E, G, H from Fig. 3. The 9 volts or, line E from Fig. 3 is converted into a squarewave signal by components 15 to 21, which signal controls via component 114 the components 8, 9, 13 of a burst oscillator having output line I. Components 10, 11, 12 and switch 22A are used to vary the number of pulses generated in each burst provided by the burst oscillator, so as to enable the user to vary clock speed in order to set correct time. The output of the burst oscillator passes via line I to Fig.

5. Component 8 is an inverting amplifier. Components 9, 10, 11, 12, 15, 17, 20, 21 are resistors. Component 13 is a timing capacitor. Components 114, 19 are signal diodes.

Components 16, 18 are silicon NPN transistors.

In Fig. 5, component 26 is a divide by 3000 (twelve bit binary) counter driven by square wave signal available on line I from the burst oscillator of Fig. 14. Component 26 is controlled by components 27 to 44 to give a count of 3000. Components 22B, 23 to 25 are used to reset and hold component 26 at zero, thereby enabling the user to stop the clock at any time should the displayed time be ahead of real time. Output line J frcm component 26 provides a one pulse per minute signal to Fig. 6. Component 22B is a switch. Components 23, 25, 31, 44 are resistors.

Component 24 is a silicon PNP transistor. Components 27, 29, 32 to 143 are signal diodes. Components 28, 30 are inverting amplifiers.

In Fig. 6, component 46 is a divide by 1440 (twelve bit binary) counter controlled by components 45, 47 to 61 to give a count of 114140 corresponding to the number of minutes in a twenty four hours day. Output lines K1 to Kil from component 46 each provide a binary encoded signal to Fig. 7, those signals reFresenting each minute of the day. Components 47, 50 to 60 are signal diodes.

Components 45, 48 are inverting amplifiers. Components 49, 61 are resistors.

In Fig. 7, component 62 is a 64K EPROM (8K-byte), and component 63 is a 614K EPROM (8k-byte), the signals on lines K1 to K11 from Fig. 6 providing addressing inputs to components 62, 63. Component 62 may be programmed by the user to operate at least one automaton at at least one selected time. Data output lines M1 to M8 from component 62 are protected against overload, the protection being provided by components 614 to 71. Line M1 provide a data imput signal to Fig. 13. Lines M1 to M8 make available data signals to the user, e.g. for control of external apparatus or equipment, for instance house light(s), a juke box, etc. Component 63 contains data for clock display, and is addressed by the binary encoded time signals cn lines K1 to K11.Output lines L1 to L8 from component 63 provide clock display data signals. Imput lines N1, N2 to component 63 provide multiplex signals from Fig. 8, to enable component 63 to select correct data for each display character. Components 64 to 71 are output protection resistors.

In Fig. 8, component 75 is a digital counter with four discrete, output lines 01, 02, 03, 04 controlled by components 86 to 89, those lines providing signals to Fig.

9. Components 76 to 81 are used to encode the outputs placed onto lines 01, 02, 03, 04 by component 75, the encoded signals being binary encoded signals that pass via lines N1, N2 to component 63 of Fig. 7. Components 72 to 74 form an oscillator that drives component 75. Components 72, 76, 77, 82 to 85 are resistors. Component 73 is an inverting amplifier. Component 74 is a timing capacitor.

Components 78 to 81 are signal diodes. Cor.pcnents 86 to 89 are silicon NPN transistors.

In Fig. 9, clock display driver Component 90 is an integrated circuit having 8 buffer amplifiers, which convert to high current signals the input signals available on lines L1 to L8 from Fig. 7. These high current signals pass via components 91 to 98 to component 99 which connects to each segment in the clock display, the current in each segment being set by components 91 to 98. Lines 01 to 014 from Fig. 8 enable digit select signals to pass via component 99 to the clock display. Components 91 to 98 are current limiting resistors.Component 99 is a connector plug and socket (Fig.19)0 In Fig. 10, tone identification signals from Fig.l8 go to line Tl and via components 100 to 104 to components 105, 112, 119, 126, components 100 to 104 providing some protection against excessive signals from line T1.

Components 105, 112, 119, 126 decode the individual frequencies from line T1. Components 106, 107, 113, 1114, 120, 121, 127, 128 determine the operating frequency of each tore decoder 105, 112, 119, 126, and these frequencies are passed via lines P1, P2, P3, P4 to Fig. 12. Components 108 to 111, 115 to 118, 122 to 125, 129 to 133 set the operating range(s) of the tone decoders 105, 112, 119, 126. Lines Q1, Q2, Q3, Q4 pass to Fig. 11 output signals from those decoders. Components 100, 101, 106, 110, 111, 113, 117, The , 120, 124, 127, 131, 132 are resistors.

Components 102, 103 are signal limiting diodes. Conponents 107, 108, 109, l;4 to 116, 121to123, 128, 129, 130, 133 are capacitors. Component 1014 is a signal coupling capacitor.

In Fig. 11, tone identification signals on lines Q1, Q2, Q3, Q4 pass via components 134 to 153 to component 154, components 134 to 153 providing some protection against noise/spurious signals. Component1s4 is is a tone identification unit, which identifies the tone identification signals. Output line S1 from component 154 passes a signal to Fig. 16 and output line S2 from component 154 passes a signal to Fig. 13, when the tone signals match the signals set by switch 155. Output lines R1, R2, R3, R4 from component 154 pass signals to Fig. 12, controlled by components 156 to 159. Components 134, 138, 142, 146 are signal diodes.Components 135, 139, 143, 147 are filter capacitors, Components 136, 140, 144, 148, 150 to 153, 156 to 159 are resistors. Components 137, 141, 144, 149 are inverting amplifiers.

In Fig. 12, signals on lines P1, P2, P3, P4 from Fig. 10 pass to components 166, 167, 168, 16C, which are controlled by signals on lines R1, R2, R3, R4 frcm Fig.

11. Thcse components output to line T2 via components 160 to 16C appropriate tone signals selected by switch 155 in Fig. 11. This selecting makes preselected tones available to the user. Component 160 is a coupling capacitor.

Components 162, 163, 164, 165 are resistors. Components 166, 167, 168, 169 are NAND gates.

In Fig. 13, control signals on line M1 from Fig. 7 pass to components 170 to 174 which convert those signals into long pulses (e.g. 5 seconds pulse width) that pass to component 178. Identified tone signals on line S2 from Fig. 11 pass to components 175 to 177 and to 180.

Comonents 175 to 177 convert those received signals into short pulses (e.g. 1 second pulse width) that pass to components 179, 180. After a predetermined delay, components 180, 182 pass output signals onto line V3 leading to Fig. 15. Components 178, 179 are NAND gates and constitute a bistable latch or flip flop, set by the long pulses to give output signals onto line V1 leading to Fig. 14, and reset by the short pulses. Components 178, 179 enable cancellation of the signals outputted by those components onto line VI. Component 181 provides optional compliments to line V2 of those signals.

Components 170, 173, 176 are resistors. Components 171, 174, 177, 182 are inverting amplifiers. Components 172, 175 are each capaciters. Components 178, 179, 180, 181 are NAND gates.

In Fig. 14, components 183 to 190 constitute a switches regulated power supply that is controlled by signals on line VI from Fig. 13. When line VI is at e.g.

+ 5 volts, output line V ir Fig. 12 is at e.g. + 3 volts.

Components 183, 184, 186, 188 are resistors. Components 185, 189 are NiN transistcrs. Component 187 is a Zener diode. Component 190 is a decoupling capacitor.

In Fig. 15, components 191 tol93B contrcl relay 194 and its switch contacts 195 to select audio signals presented to lines W1, W3 from input line W2. This selection responds to signals on line V3 from Fig. 14.

Components 191, 192 are each resistors. Component 193 is a signal diode. 193B is a silicon NPN transistor.

In Fig. 16, tole identification signals from line S1 of Fig. 11 pass via components 196 to 198 to line X2, those components delaying these signals by a F:redet.errined time e.g. 0.5 second. Compliments of those signals pass via component 199 to line X1 that leads to an automaton driver (Fig. 17). Cort,}:clrer.t 196 is a resistor. Component 197 is a timing capacitor. Components 198, 199 are inverting amplifiers.

In Fig. 17, signals on lines X1, X2 from Fig. 16 are converted by items 201, 202 and 203, 204 into negative going pulses whenever lines X1, X2 chc.nge state. The pulses from componerts 201, 202 set the bistable latch or flip flop constituted by components 205, 206 which in turn signal the automaton drive ccmponents 216 to 223 to cause automaton motor 232 to rotate in a clockwise manner. The pulses from components 203, 204 set the bistale latch cr flip flop constituted by components 208,208 that in turn signal automaton motor drive components 224 to 231 to t cause motor 232 to rotate in an anti-clockwise manner.

When the automaton mechanism actuated by motor 232 reaches the end of its travel in either' direction, motor 232 will stall and pass excessive current through component 209, which current is sensed by components 210 to 215, which send pulses to components 206, 208, which resets whichever bistable latch that was signalling motor 232 to rotate.

Components 201, 203 are capacitors. Components 202, 204, 209, 210, 212,213.215,216,218, 219, 220, 221, 224, 226, 227, 228, 229 are resistors. Components 205, 206, 207, 208 are NAND gates. Components 214, 223, 225, 230 are NPN transistors. Components 211, 222, 231 are PNP transistors.

In Fig. 18, component 222 is an auto reverse audio cassette player. An audio cassette is inserted into component 222, with one side of the cassette fully wound to its beginning. Power is supplied to component 222 by line V (eg. + 3 volts) from Fig. 14 and line H (e.g. 0 volts) from Fig. 3, when required by component 62 of Fig.

7 to find the first message as selected by component 155 of Fig. 11. Component 222 then sends identification tone signals via line T1 to Fig. 10 and audio signals via line W1 to Fig. 15.

In Fig. 19, components 216 to 219 are 7-segment displays wherein each identical segment is driven via connector 99, whose line 991, 992, 993, 994 respectively control components 216 to 219. The common cathode of each component 216 to 219 is driven via connector lines 991, 992, 993, 994. The circuitry of Fig. 19 then displays time in hours and minutes.

In Fig. 20, audio signals from line W2 of Fig. 15 pass via component 221 to loudspeaker 220 which emits an audio message. Component 221 is an audio power amplifier.

The disclosures with reference to the drawings also include equivalents and modifications, For example, component 62 (Fig. 7) may be a 128 or 512 K EPROM.

Applications of the present invention can include any systems where multiple control means are required in response to time signals or feed-back signals from remote equipment or sensors (fire, heat, etc,), such that the invention produces surveillance and/or automatic operation of multiple programmed activities.

The storage means can be any suitable medium, e,g, including video tape for the retention of audio and digital signals quite apart from and not excluding video data, In general, the present invention may be applied to any suitable application.

Claims (22)

1. Display apparatus, comprising: (a) at least one first terminal means, for providing at least one clock visual output; (b) at least one second terminal means, for providing at least one audio output and at least one functional signal for control and/or data purposes; (c) at least one automaton, for providing at least one automaton display; (d) at least one first control means, for at least partly controlling said at least one first terminal means; (e) at least one second control means, for at least partly controlling said at least one second terminal means, said at least one second control means being responsive to said at least one first control means and responsive to at least one third control means mentioned below; and (f) at least one said third control means, for at least partly controlling said at least one automaton, said at least one third control means being responsive to said at least one second terminal means,

2. Display apparatus as claimed in claim 1, wherein said apparatus is a clock for speaking or talking.

3. Display apparatus as claimed in claim 1 or 2, wherein said at least one first terminal means is adapted such that said at least one clock visual output comprises at least one display of time,

4. Display apparatus as claimed in any one of claims 1 to 3,. wherein said at least one second terminal means is adapted such that said at least one audio output comprises at least one display of audio information,

5. Display apparatus as claimed in any one of claims 1 to 4, wherein there is first circuitry, comprising the at least one first terminal means and the at least one first control means.

6. Display apparatus as claimed in claim 5, wherein said first circuitry comprises at least one random access and/or read only register,

7. Display apparatus as claimed in claim 6, wherein said register is an EPROM register.

8. Display apparatus as claimed in any one of claims 1 to 7, wherein said first circuitry comprises at least one clock means, for providing timing operation(s).

9. Display apparatus as claimed in claim 8, wherein said at least one clock means is adapted such that said timing operation(s) will provide timings that overlap data in time domains in order to cue in and exit activities,

10. Display apparatus as claimed in any one of claims 1 to 9, wherein there is second circuitry, comprising the at least one second terminal means and the at least one second control means.

11. Display apparatus as claimed in claim 10, wherein said second circuitry comprises at least one memory means.

12. Display apparatus as claimed in claim 11, wherein said at least one memory means comprises random access and/or read only memory.

13. Display apparatus as claimed in claim 11 or 12, wherein said at least one memory means is adapted to be interactive with a user of the display apparatus,

14. Display apparatus as claimed in claim 11 or 12, wherein said at least one memory means is adapted to be non-interactive with a user of the display apparatus.

15, Display apparatus as claimed in any one of claims 11 to 14, wherein said at least one memory means is adapted to store a plurality of programs.

16, Display apparatus as claimed in claim 15, wherein said plurality of programs comprises a respective program for each day of a week or other period of time.

17. Display apparatus as claimed in any one of claims 11 to 16, wherein said at least one memory means comprises at least one means chosen from: integrated circuitry memory means; laser recorded memory means; and magnetic recorded memory means.

18. Display apparatus as claimed in any one of claims 1 to 17, wherein there is third circuitry, comprising the at least one third terminal means and the at least one third control means.

19, Display apparatus as claimed in claim 18, wherein said third circuitry comprises at least one processor means for processing tone signals derived or outputted from audio signals from at least one said memory means comprised by the second circuitry.

20. Display apparatus as claimed in any one of claims 5 to 19, wherein at least one of said first, second, and third circuitry is adapted to provide control and/or data output signals for functions not part of the display apparatus.

21. Display apparatus as claimed in claim 20, wherein said functions not part of the display apparatus comprise at least one function chosen from: control function(s) for at least partly controlling a heating system; a lighting system; and an audio system.

22. Display apparatus, substantially as hereinbefore described with reference to and as shown in the accompanying drawings.