GB2219453A

GB2219453A - Analogue to digital convertors

Info

Publication number: GB2219453A
Application number: GB8912779A
Authority: GB
Inventors: Ian Juso Dedic
Original assignee: General Electric Co PLC
Current assignee: General Electric Co PLC
Priority date: 1988-06-06
Filing date: 1989-06-02
Publication date: 1989-12-06
Anticipated expiration: 2009-06-02
Also published as: GB2219453B; GB8813350D0; GB8912779D0

Abstract

An analogue to digital convertor of the "half-flash" type, in which an input analogue signal Vin, is first compared with a set of coarse reference values and then with a set of fine reference values, using the same set of comparators 5, wherein the fine reference values are derived by switching split capacitor values 6, 7 at the input of the comparators 5 to effect voltage division between two adjacent coarse reference values. In the uppermost comparator 5 the capacitors 6, 7 are proportioned 15:1, in the next comparator 14:2 and so on down to 1:15 in the lowest comparator. <IMAGE>

Description

Analogue to digital convertors.

The present invention relates to analogue to digital convertors, and in particular although not exclusively to very high speed convertors.

The fastest method of analogue to digital conversion is simultaneously to compare the value of an analogue input signal with a complete range of reference values spaced at intervals equal to the finest resolution required, a method referred to as 'flash conversion but this for an N-bit convertor requires 2N reference values and 2N comparators. Thus for 8-bit conversion this method would require 256 reference values and comparators.

The number of comparators can be reduced at the expense of speed by splitting the conversion into two parts, first comparing the input signal with 2N/2 coarse reference values and then comparing it with 2N/2 fine reference values between the two closest coarse reference values. A convertor using this method requires only 16 comparators for 8-bit conversion, and is referred to as a Uhalf-flashU convertor. Problems which may arise with this method of conversion are keeping the input signal value constant during the two stages, and producing the required fine reference voltages.

According to one aspect of the present invention in an analogue to digital convertor in which a plurality of comparators are used to compare an input signal value with a like plurality of coarse reference values there are provided switch means and capacitive divider means arranged to derive in respect of each comparator a respective fine reference value between any selected two adjacent coarse reference values for comparison with said input signal.

According to another aspect of the present invention in an analogue to digital convertor comprising a plurality of comparators each having associated therewith capacitive input means by way of which an input signal value and a respective one of a plurality of coarse reference values may be applied to the respective comparator, there are provided switch means whereby the capacitive input means associated with each comparator is selectively configured as a capacitive divider arranged to provide the respective comparator with a respective fine reference value between any two adjacent coarse reference values applied to said capacitive input means.

According to another aspect of the present invention in an analogue to digital convertor in which an electric input signal value is arranged to be compared substantially simultaneously in a plurality of comparator means with respective ones of a like plurality of different reference signal values spaced over a range of values to determine between which two of said reference signal values said input signal value lies, the input signal value and the respective reference signal value being applied to each comparator means by way of respective capacitive input means, said capacitive input means in respect of each of said plurality of comparator means is formed in two parts in respective different proportions, and there are provided switch means to apply said two of said reference signal values to each said capacitive input means, such that a respective different fine reference signal value between said two of said reference signal values is derived in each of said capacitive input means for application to the respective comparator.

An analogue to digital convertor in accordance with the present invention will now be described by way of example with reference to the accompanying drawings, of which: Figure 1 shows schematically a known form of convertor, Figure 2 shows schematically a form of signal comparator, and Figure 3 shows schematically an analogue to digital convertor in accordance with the present invention.

Referring first to Figure 1 a flash convertor to encode an input signal voltage value Vin to eight-bit resolution requires a chain of 256 equal value resistors R to provide reference voltages spaced over a range extending up to the maximum value expected for Vin. The tapping points on the chain of resistors are connected to respective ones of 255 comparators C, the outputs of which indicate between which pair of adjacent reference voltages the input signal voltage lies. An additional comparator (not shown) may be provided to detect the occurrence of an input voltage exceeding the maximum reference voltage. An 8-bit code group representing the value of Vin may be derived from the outputs of the comparators C by logic circuits (not shown).

A form of comparator C, sometimes referred to as an auto-zeroed comparator, is shown in Figure 2. In the flash convertor of Figure 1 the switches 1 and 2 of this comparator would first be closed to "autozero11 the circuit, whereby the left hand side of a capacitor 3 is connected to the appropriate reference voltage while the right hand side of the capacitor 3 and the output of the comparator settle at the comparator threshold. When switches 1 and 2 are opened and a switch 4 is closed the input voltage Vin is applied to the left hand side of the capacitor 3, and the change in the comparator output is dependent only on the difference between Vref and Vin, and not on the comparator threshold.In a half-flash convertor (not shown) working to the same resolution a third switched input (not shown) may be provided to apply a fine reference value to the autozero comparator.

Referring now to Figure 3, which shows a form of half-flash convertor, the input capacitor of each of fifteen comparators 5 is divided into two parts 6 and 7 in different proportions, from 15:1 in the case of the uppermost comparator, 14:2 in the next, and so on down to 1:15 in the lowest comparator. The convertor is operated in three stages, as follows: In a first time period, switches 8,9 and 10 are closed to autozero each comparator with the input signal voltage Vin on the left hand side of all capacitors 6 and 7. In a second time period, the switches 8,9 and 10 are open and switches 11,12 and 13 are closed to apply respective UcoarseU reference signal values to the left hand sides of all the capacitors 6 and 7, whereupon the outputs of the comparators 5 indicate between which two of these coarse reference signal values the inut signal value Vin lies.

In a third time period the switches 13 are open and switches 11 and 12, 14 and 15 are used to apply the two reference signal values, between which the input signal value Vin lies, to the left hand sides of respective capacitors 6 and 7. The different proportions of these capacitors in different comparators 5 then effectively provide different input t'fine11 reference signal values to those comparators, which fine reference signal values are spaced between the two coarse reference signal values.

Thus in respect of the top or fifteenth comparator 5 the effective reference signal value applied is: 15VT + VB 16 - where VT is the upper coarse reference value and VB is the lower coarse reference applied in common to all the comparators.

This effective reference signal value, rearranging the symbols, can be seen to be: 15VB + 15(VT-VB) + YB 16 or VB + 15(VT-VB).

16 Compared with a resistive arrangement for deriving the fine reference signal values, 256 resistors and switches are replaced by 16 resistors and 80 switches, giving a considerable saving in chip area.

The capacitors 6 and 7 occupy little more area than the single autozero capacitor in a standard comparator (Figure 2).

Claims

1. An analogue to digital convertor in which a plurality of comparators are used to compare an input signal value with a like plurality of coarse reference values wherein there are provided switch means and capacitive divider means arranged to derive in respect of each comparator a respective fine reference value between any selected two adjacent coarse reference values for comparison with said input signal.

2. An analogue to digital convertor comprising a plurality of comparators each having associated therewith capacitive input means by way of which an input signal value and a respective one of a plurality of coarse reference values may be applied to the respective comparator, wherein there are provided switch means whereby the capacitive input means associated with each comparator is selectively configured as a capacitive divider arranged to provide the respective comparator with a respective fine reference value between any two adjacent coarse reference values applied to said capacitive input means.

3. An analogue to digital convertor in which an electric input signal value is arranged to be compared substantially simultaneously in a plurality of comparator means with respective ones of a like plurality of different reference signal values spaced over a range of values to determine between which two of said reference signal values said input signal value lies, the input signal value and the respective reference signal value being applied to each comparator means by way of respective capacitive input means, wherein said capacitive input means in respect of each of said plurality of comparator means is formed in two parts in respective different proportions, and there are provided switch means to apply said two of said reference signal values to each said capacitive input means, such that a respective different fine reference signal value between said two of said reference signal values is derived in each of said capacitive input means for application to the respective comparator.

4. An analogue to digital convertor substantially as hereinbefore described with reference to the accompanying drawings.