GB2214011A - Continuous monitoring of electronic equipment - Google Patents

Abstract

The apparatus includes various modules for testing specific types of equipment, e.g. AF circuitry, RF circuitry, etc.. In one example, an AF test module receives AF signals from the equipment under test into one of terminals SK1 or SK2. A test signal from a 1KHz source is applied to terminal 3. In order to test, for example, an AF amplifier, the 1KHz test signal is also applied to the input of the amplifier so that the apparatus effectively compares 53 the 1KHz test signal before entering the amplifier under test with that having passed through the amplifier. The circuitry tests both for amplitude variations outside a certain range, and for excess noise and/or distortion, and actuates a latched alarm when a fault is detected. Frequency reponse and RF tuner and receiver characteristics may also be monitored. <IMAGE>

Description

"TESTING OF ELECTRONIC EQUIPMENT" This invention relates to a method and apparatus for the testing of electronic equipment, particularly domestic equipment such as Hi-Fi systems, videos, televisions and the like. The invention finds utility both in the routine testing of equipment during production, and in the testing of bought equipment which is malfunctioning.

Testing of equipment which has been brought in for repair of an intermittent fault poses a particular problem in the busy repair shop. The fault experienced by the customer may not manifest itself for many minutes or even hours after switch on, and it is clear that continuous monitoring of the equipment until the fault occurs is very costly in manpower.

The present invention seeks to overcome this problem by a method of testing which comprises utilising a piece of electronic circuitry to continuously monitor an output signal of the equipment under test and automatically actuating an audible and/or visible alarm when some parameter of the output signal falls outside a predetermined limit or limits, indicative of a fault condition.

The output signal may be provided at terminals on the equipment under test - for example the loudspeaker terminals for an A.F. amplifier - or may be provided on an ad hoc basis at some suitable point within the circuitry of the equipment under test by the technician carrying out the test.

The occurrence of the above condition causes the technician to be alerted, and the fault can then be investigated. Often however the fault occurs for only a short time and may indeed have corrected itself before the fault can be investigated or even before the existence of a fault condition has been realised. To meet this problem it is preferred that the existence of the fault condition, and its nature, once detected, are maintained even in the event that the fault subsequently corrects itself. In order to cater for relatively short-term transitory perturbations, such as might arise due to mains variations, it is preferable to delay actuating the alarm condition for a short period after a fault occurs.

In a preferred method of detecting the fault condition, the parameter being monitored is converted to a property (for example voltage or current-level, or frequency) of a test signal, which property is then itself monitored to test for variations outside predetermined upper and/or lower limits to actuate the alarm condition. As an example, if distortion in an AF amplifier is to be detected, those components of the output signal which are responsible for distortion are separated off, and are converted into an amplitude level in a d.c. test signal. This test signal is itself monitored for a rise in its amplitude, representative of a rise in distortion level, above a pre-set level known by experience to represent an unacceptable level of distortion for the amplifier concerned.The pre-set level may be made adjustable so that account can be taken of the differing properties of the various equipments being tested.

Preferably the test signal is compared with two pre-set reference signals to thereby define a "window" for the test signal within which the equipment under test is reckoned to be operating satisfactorily.

In a further aspect of the invention there is provided apparatus for testing electronic equipment, said apparatus comprising means for continuously monitoring an output signal of the equipment under test, means for detecting when some parameter of said output signal falls outside a predetermined limit or limits indicative of a fault condition, audible and/or visible alarm means, and means for actuating said alarm means when said output signal falls outside said predetermined limit or limits.

In order that the invention may be better understood, several embodiments thereof will now be described by way of example only and with reference to the accompanying drawings in which: Figure lA,B is a circuit diagram of the master unit for a modular test apparatus embodying the invention; Figure 2 is a block diagram of an AF test module forming part of the test apparatus of the invention; Figure 3A to E is a circuit diagram of the AF test module of Figure 2; Figure 4 is a block diagram of an AF sweep test module forming part of the test apparatus of the invention; Figure 6 is a block diagram of the signal generator section of an RF test module forming part of the test apparatus of the invention; Figure 7 is a block diagram of the signal analysis section of the RF test module of Figure 6;; Figure 8A to C is a circuit diagram of the signal generator section of the RF test module of Figure 6; and Figure 9A to D is a circuit diagram of the signal analysis section of the RF test module of Figure 7.

Referring to the drawings there is shown a modular test apparatus comprising a mains transformer (not shown) and master unit, shown in Figure 1, and one or more optional modular units to be described in detail with reference to Figures 2 to 9. The advantage of this modular approach is that modules can be bought as needed and as expense permits.

Referring now in particular to Figure 1A,B there is shown a circuit diagram of the master unit.

The master unit has three principal functions: 1. The provision of unregulated and regulated dc supplies for use within other modules; 2. The provision of a low distortion 1 kHz signal for use by the various modules; 3. Alarm generation.

The master unit receives a 12 volt ac supply at terminals 31,32 which is passed to a full wave bridge rectifier BRl. Positive and negative outputs from this rectifier are smoothed by electrolytic capacitors C1 and C2 respectively and passed to positive and negative regulators IC1,IC2 and positive regulator IC4.

The three regulators produce supplies of plus 12 volts, minus 12 volts and plus 5 volts respectively for distribution within a rack system (not shown) to the other modules.

The 1 kHz signal is provided by a twin-T oscillator built around transistor TR1. The frequency determining components comprise resistors R1,R2,R3 and capacitors C5,C6 and C7. Adjustment of the 1 kHz output frequency can be obtained by adjustment of trimmer RV1 in series with resistor R3. Transistor TR2 provides a constant voltage source for the collector of transistor TRI and, by this means, is able to compensate for variations in transistor parameters, thus enabling the cheapest transistors to be used for the oscillator. Adjustment of the purity of the waveform can be obtained by varying the base bias of transistor TR2 by adjustment of trimmer RY3.

The output from the oscillator is taken from the wiper of a level adjustment trimmer RV2 to the input of a unity gain buffer amplifier IC3. The output from the buffer, for application to the other modules, is taken from terminal 2 and will be seen to be at a low impendence, typically 100 ohms. A typical output level is 200 mV RMS.

The alarm circuitry is conventional, being centred around a 555 integrated circuit IC5. Two LED's are provided in the alarm circuitry; diode D1 is indicative of power on; diode D2 which is connected to the output of IC5 is energised when an alarm condition occurs. Although a 555 integrated circuit is shown, it will be clear that any similar circuit could be used. What is needed is some form of generator which may be selectively triggered to energise an audible and/or visual alarm. In this case, the output pin 3 of IC5 is connected both to a visual alarm, the aforesaid diode D2, and an audible alarm in the form of a piezo transducer WD1. Integrated circuit IC5 is triggered by a trigger signal input at terminal 17.

The alarm is triggered when terminal 17 goes low, which switches transistor TR3 off, thus causing input terminal 4 of IC5 to rise to plus 5 volts, which causes triggering of the 555 to send an output from pin 3.

The trigger signal is applied to terminal 17 from the individual modules, as will be explained below.

Thus, the master unit provides the basic functions needed by all of the modules. A basic test apparatus would thus comprise at least the master unit, and one module. The individual modules will now be described in turn.

Referring firstly to Figure 2, there is shown the AF test module. This is designed for the general purpose testing of audio frequency amplifiers, both stand-alone amplifiers and amplifiers incorporated in other equipment. The module is able to test both signal amplifiers and power amplifiers by means of two inputs SK1 and SK2. Input SK1 is intended to be connected to the loudspeaker terminals of an amplifier.

An 8 ohm load 50 takes the place of the loudspeaker and ensures that no damage occurs to the amplifier during the test. The internal load is protected by a 1A quick-blow fuse F1. The output of the amplifier is passed via an isolating transformer T1 to an amplifier 51. Low level signals are inputted to input SK2 via a buffer amplifier 52 to the input of amplifier 51.

Although the inputs SK1 and SK2 will only be used, in practice, one at a time, the signals from each are amplified in amplifier 51 by different amounts so that, at the output of amplifier 51, they are at approximately the same level. The output of amplifier 51 is passed to a precision rectifier 52 which provides at its output a dc level, typically of the order of +1 volt, which is proportional to the peak value of the input voltage. The output from the precision rectifier 52 is passed to a window comparator 53 whose output on line 54 is high if the input is within a defined window and low if the input is outside this window. The window is set by upper and lower voltage limits defined respectively on input lines 55,56 of the window comparator.

These upper and lower limits are generated from the 1 kHz signal from the master unit which is inputted to the AF module at terminal 3. The 1 kHz signal is rectified in precision rectifier 57 to give a dc output level, typically +1 volt, representative of the peak value of the output voltage of the master unit oscillator. The output from the precision rectifier 57 is applied to a level shifter/adder 58 which acts to add and subtract a fixed voltage level from the input signal from rectifier 57. Thus, two outputs are created, one on line 55 and one on line 56 representative, on the one hand, of the input voltage plus the fixed voltage level (the upper limit), and, on the other hand, of the input voltage minus the fixed voltage level on line 56 (the lower limit). The size of the window about the output level from rectifier 57 can be adjusted within the unit 58.

Typically the fixed voltage level is of the order of lOOmV.

In order to test an amplifier, the output from the oscillator in the master unit is applied to the input of the amplifier, or to some other suitable point in the signal path of the amplifier, and the output monitored at terminals SK1 or SK2, as appropriate. In these circumstances, it will be seen that the output of rectifiers 52 and 57 should both be representative of the output of the master unit oscillator, but one having been first applied through the amplifier under test. If all is well, therefore, the two outputs from precision rectifiers 52 and 57 should be steady with respect to one another. However, if the amplifier has an intermittent fault which causes the gain of the amplifier to rise or fall, then the output from precision rectifier 52 will vary.In order to detect this variation, the upper and lower limits set by the level shifter 58 can be set to define the limits of the acceptable variation of the output of rectifier 52.

Thus, if the gain of the amplifier under test varies for any reason beyond an amount which is known by experience to be acceptable, the output signal from precision rectifier 52 will vary beyond the window, and cause the output of the window comparator 54 to go low, thus indicating a fault in the amplifier.

The output from comparator 54 is passed to level shifter circuitry 59 which energises a light emitting diode D10 which is illuminated when the input signal from rectifier 52 is within the defined window i.e. no fault condition. When a fault condition occurs, the diode D10 is extinguished. It should be noted that the diode D10 has no latching function: it goes on and off according to whether a fault is present or not.

The output from the level shifter circuitry 59 is passed to a latch 60 whose Q and Q outputs are passed respectively to a second light emitting diode D11 and to an open-collector NOR gate 61. The output from the NOR gate is passed as a trigger signal to the trigger input of the alarm circuitry on the master unit.

In the event of a fault, the 4 output of the latch 60 goes low and switches the diode D11 on. The Q output goes high, and causes the output of the NOR gate 61 to go low, to actuate the alarm, as explained previously.

Because of the latching function of the latch 60, the subsequent cessation of the fault condition causes the outputs Q and Q of the latch 60 to remain latched to continue to indicate the fault condition.

The diode D10, on the other hand, switches on again, as soon as the fault condition ceases. The latch can be re-set by means of push switch S1.

If desired, the 1 kHz signal from the master unit can be monitored at terminal SK3 which is derived from terminal 3 via a buffer amplifier 62 whose output level can be set to a suitable value for monitoring purposes.

A further output from amplifier 51 is passed to a notch filter 63. This notch filter is set to a centre frequency of 1 kHz, and thus filters out the 1 kHz test signal being used to test the amplifier. The output of filter 63 is thus representative of any noise and/or distortion occurring in the amplifier output.

This output is rectified in a precision rectifier 64 and passed as one input to a comparator 65. The other input of comparator 65 is derived from the output of precision rectifier 52, suitably reduced in amplitude by trimmer resistor RV3.

It will be seen that the comparator 65 is able to judge the magnitude of the noise/distortion component of the output of the amplifier under test. The two inputs to comparator 65 are both subject to external variations not due to noise and/or distortion and the comparison in comparator 65 is thus a good representation of the noise/distortion within the amplifier. Obviously, any amplifier will be subject to a certain amount of noise and/or distortion but, given the class of amplifier, an unacceptable level of noise and/or distortion can be detected. A typical output of the precision rectifier 64 would be of the order of IO mV for an acceptable level of noise and/or distortion, above this is judged to be unacceptable.

In the present case, the output of comparator 65 is high if the distortion/noise is less than 10 mV (i.e.

acceptable) and low if the input rises above 10 mV, indicative of a fault condition. The output from the comparator 65 is passed to level shifting circuitry 66 which energes a light emitting diode D12 in the event that the noise/distortion level is acceptable. If the noise/distortion level becomes unacceptable, then the diode D12 is extinguished. The output from the level shifting circuitry 66 is passed to a second latch 67 whose Q and Q outputs are passed respectively to one input of the NOR gate 61 and to a light emitting diode D13. If the noise/distortion level becomes unacceptable, then the Q output of latch 67 goes high to trigger the alarm within the master unit. Likewise, the Q output of latch 67 goes low, to energise diode 13 to indicate a fault. As before, if the fault condition ceases, then the diode 13 will remain energised, and the master unit alarm will remain energised. The diode D12, on the other hand, will become illuminated once again, indicating that the fault condition has ceased.

The circuitry shown in Figure 2 can also form the basis of a tape test module, the main differences between such a module and that shown in Figure 2 would be that the high level input via the 8 ohm load and isolator transformer would be unnecessary, and there w-ould also preferably be a delay network incorporated into the circuitry of the alarm to avoid the alarm circuit being triggered by tape drop-out. A typical delay would be in the region of 200 - 500 ms. In order to test the tape recorder, a 1 kHz test tape could be recorded as an alternative test input to that from the oscillator in the master unit.

Figure 3 shows the detailed circuit diagram of the AF test module of Figure 2. The reference numerals in Figure 3 are, where appropriate, identical with those of Figure 2 and the blocks in Figure 2 indicate the particular principal active and passive devices which form the basis of the circuits described.

Since the circuitry of Figure 3 is by and large conventional, detailed description thereof is omitted.

Figure 4 shows the AF sweep test module which is designed for detecting faults in audio amplifiers of a type which manifest themselves as defects in the overall frequency response. The module provides a sinusoidal output which is swept over a pre-set frequency range and effectively compares the amplitude/frequency characteristic of the amplifier under test with that of the outgoing signal. When any difference is detected, a latching alarm signal is generated in the same manner as described above with reference to the AF test module. In order to cater for amplifiers having different frequency responses, the preset frequency range is preferably switchable to give different lower and upper limits - for example: lower limit: 10,20,50 Hz; upper limit: 5,10,15,20 kHz.

The basis of the circuit is a voltage controlled oscillator 100 whose sign wave output is passed via respective buffers 101,102 to respective left and right output terminals 103,104. The output frequency of the oscillator 100 is swept in a rising and falling cycle of triangular shape by means of a voltage controlled oscillator 105. The output of oscillator 105 is triangular, and is passed via a trimmer RV1 for amplitude adjustment to a shifter 106 in which the sweep output may be set by a trimmer RV3.

The output of the oscillator 105 is also applied to a shifter 107 for display of the output waveform of oscillator 105 in an LED display module 108. The display module 108 comprises a plurality of individual LCD display units arranged to form a bar graph whereby the rising and falling output of oscillator 105 can be monitored. A typical frequency of oscillator 105 is 0.5 Hz.

The outputs 103,104 are applied to the left and right inputs of the amplifier under test. If only a mono amplifier is being tested, then just one channel is utilised. The left and right outputs from the amplifier are applied to respective terminals 109,110 and thence via input level potentiometers VRla,VRld to buffer amplifiers 111 and 112 respectively. The amplifier outputs applied to terminals 109 and 110 are taken from a low signal level in the amplifier chain, probably after the pre-amplifier stage in which the frequency response is shaped.

The outputs from the buffers 111,112 are applied to respective precision rectifiers 113,114 to produce a dc output level representative of the input level. At any one moment in time, the output level from rectifiers 113,114 represents the output level, and hence the amplification, at a particular frequency, but this frequency is being continuously swept by the oscillator 105, The outputs of rectifiers 113,114 are passed to respective window comparators 115,116. Also applied to the two window comparators are upper and lower limit signals which are derived in the same manner as previously described with respect to Figure 2. In this case, however, the origin of the signals is the output from the voltage controlled oscillator 100 which is applied to a high pass filter 117 which is intended to compensate for low frequency deficiencies in the amplifier under test.This is achieved by simulating the low frequency roll-off of the amplifier, for example 3 dB down at 10 Hz would be typical. The output from the filter 117 is passed via a buffer 118 to a precision rectifier 119. The output signal of the precision rectifier 119 is thus representative of the peak value of the output of the voltage controlled oscillator 100 at a particular moment in time. The signal output from rectifier 119 is applied to a level shifter/adder circuit 120 which adds and subtracts a fixed voltage level to the input signal for application to the respective upper and lower limit lines defining the window for comparators 115 and 116. The concept is identical to that described previously with reference to Figure 2 and will not therefore be repeated in detail.

In order to explain the operation, the lefthand channel is taken as an example. It will be seen that the outputs from the two rectifiers 113,119 are both representative of the peak value of the output of voltage controlled oscillator 100, but that from rectifier 113 has passed through the amplifier under test.

Thus, any variation above or below preset values known to be acceptable will be detected by the window comparator 115 and will result in a change in its output status.

The output from each of the window comparators 115,116 is applied to respective level shifter circuitry 117,118 and latches 119,120 which energise diodes Di2,D13,D14 and D15 in the same manner as described above to indicate fault conditions. The Q outputs of each of the latches 119,120 are passed to a NOR gate 121 for actuation of the alarm on the master unit, as previously. A push switch S1 operates to reset the latches 119 and 120.

Detailed circuitry for the AF sweep module of Figure 4 is illustrated in Figure 5. Where appropriate, the same reference numerals have been used and, since the circuitry is conventional, detailed description is omitted.

Figures 6 and 7 show the two main parts of the RF test module which is intended for detecting faults in FM tuners and receivers. Such faults include level changes, including noise disturbances, and stereo dropout (i.e. incorrect reversion to mono output only).

Drift may also be detected since this normally results in a combination of level change, noise and stereo drop-out. The module provides a multiplexed stereo output modulated on a crystal controlled carrier at approximately 95 MHz - approximately the centre of the normal VHF broadcast tuning range. The modulation is arranged in such a way that the sinusoidal modulation, typically at 1 kHz, appears in antiphase on the left and right channels. The recovered audio signal from the tuner is applied to the test module and, where an amplitude disturbance is detected, or a relative phase change occurs, an alarm signal is generated.

The RF module is divided into two sections: a signal processing/modulator section which generates the FM stereo signal modulated at 1 kHz, and a signal analysis section which receives the demodulated left and right outputs from the receiver or tuner under test. The signal processing/modulator section is shown in Figure 6 to which reference will now be made.

The 1 kHz test modulation signal is derived from the master unit oscillator and applied via terminal 201 to an amplifier 202. The output from amplifier 202 is split, with one line 203 being taken directly to a first balanced modulator 204 and the other line 205 being taken to a second balanced modulator 206 via an inverter 207. The signals applied to the modulators 205 and 206 are in antiphase and represent the left and right signals. The 38 kHz stereo subcarrier frequency for the modulators 204/206 is generated by a 76 kHz Colpitts oscillator 208 whose output is shaped by a shaper 209 and divided down to the subcarrier frequency of 38 kHz in a divide-by-two circuit 210. The divide-by-two circuit 210 provides antiphase outputs on lines 211,212 for application to the two balanced modulators 204,206.

A further output from line 212 is taken to a second divide-by-two circuit 213 which generates a 19 kHz square wave signal. The output from the divideby-two circuit 213 is passed to a high-Q bandpass filter 214 which converts the 19 kHz square wave signal into a 19 kHz sine wave signal which is passed to a buffer 215 for application to the modulator as the pilot tone signal.

The modulators 204,206 act to amplitude modulate the 1 kHz modulation signal onto the 38 kHz subcarrier, the latter being suppressed during modulation due to the action of the balanced diodes D2 D5 and D6-D9 within the detectors. The antiphase outputs from the two modulators 204,206 are summed in a summer circuit 216 and are then likewise passed to the modulator 217. Both the pilot tone signal and the subcarrier stereo signal are passed through respective trimmers RV1,RV3 so that their levels can be suitably adjusted.

The modulator 217 acts to frequency modulate the stereo signal and the pilot tone signal onto a 10.5 MHz signal derived from a crystal oscillator 218. The modulated output from the crystal oscillator is passed to a times - nine multiplier 219 which increases the frequency to 94.5 MHz. Final filtering takes place in bandpass filter 220. The output from the bandpass filter is applied to a terminal 221 for connection to the aerial socket of the receiver/tuner under test.

Full circuit details of the signal processing/ modulator section are given in Figure 8A to C but detailed description thereof is omitted since the circuits involved are conventional.

Reference will now be made to Figure 7 which shows the signal analysis section of the RF module.

Suitable low level signals from the demodulated left and right channels of the tuner or receiver under test are applied to respective input terminals 301,302 and thence to respective buffers 303,304. The outputs from the two buffers are summed in a summer circuit 305, the right hand signal being first phase shifted by 1800 in a phase shifter 306. The output signal from the summer 305 is thus the summation of two in-phase inputs. This output signal is rectified in a precision rectifier 306 which gives a dc output level representative of the summation of the two input levels to summer 305. It will be seen that any variation in the phase of either one of the channels will cause a reduction in this amplitude. This would happen, for example, if stereo drop-out were to occur.A range of values of the output of rectifier 306 will, in practice, be found to be acceptable and therefore the test apparatus looks at a window defined by upper and lower limit signals on lines 307,308 respectively.

The signals on these lines are applied to a window comparator 309 which analyses the signal from rectifier 306 to ascertain whether it is within the window.

The upper and lower limit signals are generated from the 1 kHz signal provided by the oscillator in the master unit which is first rectified in a precision rectifier 310 before being passed to a level shifter/ adder 311. The manner in which the upper and lower limit signals are generated is identical to that described above with reference to Figure 2 and will not be repeated here. Likewise the output circuitry from the window comparator 309 is identical with that described above with reference to Figure 2. In the event that the output from rectifier 306 is within the window, the output of the comparator 309 is high. If the input from rectifier 306 is outside the window i.e. either above the upper limit or below the lower limit - then the output from comparator 309 goes low.

Comparator 309 is applied to a level shifting circuit 310 and thence to a latch circuit 311. These operate in the same manner as described hitherto. Diode D18 is illuminated all the time that the output from comparator 309 is high - i.e. the output from rectifier 306 is within the window, indicating no fault. As soon as a fault occurs in the level of the signal reaching comparator 309, the diode D18 goes out, and the diode Dl9 is illuminated. At the same time, the Q output from latch 311 is passed, via a NOR gate 312 to actuate the alarm on the master unit. If the fault subsequently disappears, then the alarm and the diode D19 will remain latched on, but the diode D18 will revert to its "no-fault" state - i.e. illuminated.

The latch 311 can be re-set by means of a re-set push button SI.

The two antiphase signals from buffers 303,304 are also passed to a summer circuit 313 whose output on line 304 thus represents the difference between the two input signals. If all is well, this signal should be zero. The output signal from summer circuit 313 is rectified in a precision rectifier 315 and thence is passed to one input of a comparator 316. In comparator 316, the output signal from rectifier 315 is compared with the output signal from rectifier 306 in order to provide a signal indicative of possible decoder faults. The output signal from rectifier 315 should in practice be less than 10 mV, and any signal greater than this may be regarded as a fault condition.

The comparison in comparator 316 is carried out in order to compensate for any external occurrences which affect both channels simultaneously.

The output from comparator 316 is passed to a level shifter 317 and thence to a latch 318. Diodes D20 and D21 indicate fault conditions in the same manner as described previously. Likewise, the Q output from latch 318 is passed to the NOR gate 312 to actuate the audible alarm on the master unit.

Figure 9A to D shows the detailed circuitry of the analysis circuit shown in Figure 7, but detailed description thereof is omitted since the circuitry is conventional.

Claims (12)

1. A method of testing electronic equipment, said method comprising utilising a piece of electronic circuitry to continuously monitor an output signal of the equipment under test and automatically actuating an audible and/or visible alarm when some parameter of the output signal falls outside a predetermined limit or limits, indicative of a fault condition.

2. A method as claimed in Claim I wherein the existence of the fault condition, once detected, is maintained, even if the fault causing the fault condition subsequently corrects itself.

3. A method as claimed in Claim 2 wherein the nature of the fault condition is additionally maintained even after possible correction of the fault.

4. A method as claimed in any one of Claims 1 to 3 further comprising delaying the onset of the above condition for a predetermined period after a fault occurs.

5. A method as claimed in any one of the preceding claims wherein the parameter being monitored is converted to a property of a test signal, which property is then itself monitored to test for variations outside predetermined upper and/or lower limits to actuate the alarm condition.

6. A method as claimed in Claim 5 wherein the test signal is compared with two pre-set reference signals to thereby define a "window" for the test signal within which the equipment under test is judged to be operating satisfactorily.

7. Apparatus for testing electronic equipment, said apparatus comprising means for continuously monitoring an output signal of the equipment under test, means for detecting when some parameter of said output signal falls outside a predetermined limit or limits indicative of a fault condition, audible and/or visible alarm means, and means for actuating said alarm means when said output signal falls outside said predetermined limit or limits.

8. Apparatus as claimed in Claim 7 further including means for maintaining the existence of the fault condition even in the event that the fault which gives rise to the fault condition subsequently corrects itself.

9. Apparatus as claimed in either one of Claims 7 or 8 including means for generating a test signal having a particular property indicative of the parameter being monitored, and means for monitoring said test signal to test for variations of said property outside predetermined upper and/or lower limits whereby to activate said alarm actuating means.

10. Apparatus as claimed in Claim 9 wherein said monitoring means includes means for comparing said test signal with two pre-set reference signals to thereby define a "window" for the test signal within which the equipment under test is judged to be operating satisfactorily.

11. Apparatus as claimed in any one of Claims 7 to 10 further comprising delay means for delaying the onset of a fault condition once a fault has occurred.

12. Apparatus for testing electronic equipment substantially as hereinbefore described with reference to the accompanying drawings.