GB2213685A

GB2213685A - Microcomputer circuit

Info

Publication number: GB2213685A
Application number: GB8828552A
Authority: GB
Inventors: Peter Pequignot Gracey; Keith David Wain
Original assignee: UK Secretary of State for Defence
Current assignee: UK Secretary of State for Defence
Priority date: 1987-12-10
Filing date: 1988-12-07
Publication date: 1989-08-16
Anticipated expiration: 2008-12-07
Also published as: GB2213685B; GB8828552D0; GB8728902D0

Abstract

Handling of data by a microcomputer is improved by converting quasi-continuous data flows into higher frequency bursts to leave the microcomputer free for data processing. Data is sent over asynchronous lines 11, 12 in bursts, thereby tying up the processor in the microcomputer 10 for short periods only. External Universal Asynchronous Receiver Transmitter (UART) 14, 15 are used to reconstruct either parallel or non-burst asynchronous data. In one particular application (Fig 5) the invention is applied to an intelligent T switch. Quasi-continuous input data (41) for connection to User A or User B includes transparent embedded codes signifying A or B data. The data and codes are connected to UART 1 which converts the data frequency (Fin) to a higher burst frequency (Fc) for parallel input 42 to the microcomputer 40. Burst data at the serial output 43 is connected first to UART 3 operating at frequency (Fc) and then the parallel output from this UART is connected to UART 4 operating at the frequency (Fin). Quasi-continuous serial data reconstructed at the output 45 of UART 4 is then connected to a changeover circuit 50 which connects the data to User A or User B depending on a signal (53) received from the microcomputer 40 in dependence on the embedded codes which are read from the incoming data during during quiescent periods of computer operation on data input and output. <IMAGE>

Description

Microcomputer Circuits The invention relates to microcomputers and in particular to reducing computer time required for input/output control.

Microcomputers normally have a restricted number of input/output lines and to make best use of these data is often transmitted in serial form. This saves lines in parallel and obviates a need for parallel multiplexers. Such an arrangement is convenient where data is produced serially as for example from a sensor. The timing of this serial data is critical but if a microcomputer has to control the input/output timing then virtually no processing power remains for other tasks, particularly when processing continuous data. One solution is to use more components, for example a DMA controller, to allow data transfer without involving the microcomputer processor.

This allows the microcomputer to carry out processing, other than timing, on the data. This, however, adds to the complexity and expense of the circuitry and also tends to reduce reliability. A further problem related to the use of some microcomputers is a lack of suitability to multi-user computer systems because of a shortage of a sufficient number of output lines.

The object of the invention is to provide a microcomputer circuit arrangement which may have serial in/serial out data while retaining microcomputer processing time for other functions.

The invention provides a microcomputer circuit for processing quasi-continuous serial data comprising: a terminal, input or output, to which the serial data is connected; at least one serial data port to the microcomputer through which asynchronous burst data is transmitted; and asynchronous baud rate conversion means connected between the microcomputer and the terminal for conversion between the higher frequency microcomputer burst data and the quasi-continuous data frequency at the terminal; the arrangement being such that the serial data flow is quasi-continuous while the computer operates on burst data.

By operating the microcomputer in bursts the circuit is able to receive and transmit quasi-continuous serial data leaving microcomputer time to process the data as required.

Preferably frequency conversion is effected by means of at least one UART (Universal Asynchronous Receiver Transmitter).

In one arrangement a pair of back-to-back UARTs is connected between the input terminal to the circuit and a serial input port to the microcomputer and a pair of back-to-back UARTs is connected between a serial output port of the microcomputer and the output terminal of the circuit, the input UARTs being used to convert the input data to a higher burst baud rate for operation by the microcomputer and the output UARTs being used to convert the burst serial output data from the microcomputer to the quasi-continuous serial data at the output terminal.

In an alternative arrangement a pair of back-to-back UARTs is connected between the input terminal of the circuit and a serial input port to the microcomputer to convert the input data to a higher burst baud rate for operation by the microcomputer and a single parallel-to-serial UART is connected between a parallel output port to the microcomputer and the output terminal of the circuit to convert the burst parallel output data from the microcomputer to the quasi-continuous serial data at the output terminal.

In a further arrangement a single serial-to-parallel UART is connected between the input terminal of the circuit on a parallel input port to the microcomputer to convert the quasicontinuous serial input data to the circuit to asynchronous parallel input data to the microcomputer and a pair of back-toback UARTs are connected between a serial output port to the microcomputer and the output terminal of the circuit to convert the burst serial output data from the microcomputer to the quasi-continuous serial data at the output terminal.

In one application of the circuit there is provided an intelligent T switch operatively connecting a single input line to a selected one of a plurality of output lines comprising a microprocessor circuit as described and further including: a switching circuit having a single input connected to the output terminal of the microcomputer circuit and a plurality of outputs corresponding to the output lines; means to detect a plurality of escape sequences in the quasicontinuous serial data, each escape sequence corresponding to a respective predetermined connection between the input line and an output line; and switching signal means connected between the microcomputer and the switching circuit to provide an appropriate switching signal in dependence on the detected escape sequence.

The invention will now be described by way of example only with reference to the accompanying Drawings of which: Figure 1 is a schematic block diagram illustrating the invention; Figures 2 - 4 are block diagrams of alternative arrangements of the invention; and Figure 5 is an intelligent T switch application of the invention.

In Figure 1 there is shown a microcomputer such as the Zilog Z8. This microcomputer 10 has a single serial input line 11 and a single serial output line 12. Where quasi-continuous data at frequency fB is input to the microcomputer 10 and a similar data stream also at frequency fg is present at the serial output line 12 then the microcomputer 10 time is almost exclusively devoted to input/output timing and little processing time remains for operation on the data stream. The invention overcomes this problem by presenting the input data to the microcomputer 10 in bursts, thus creating processing time when no data is present at the input 11. At the output of the microcomputer 10 the quasi-continuous data stream is then reconstituted from the burst data on the output line 12.

Quasi-continuous serial input data fD is connected to the input 13 of an asynchronous frequency converter 14 wherein the input data at frequency #D is converted to a burst output data at a higher frequency fB. The burst data is then connected to the input serial line 11 to the microcomputer 10 which is run at the burst frequency fB. In a complementary manner the output burst data at frequency fB after processing in the microcomputer is transmitted via the serial data output line 12 to a second asynchronous frequency converter which converts the input data to a quasi-continuous data stream of frequency fD at the output 16.

Figure 2 shows one possible implementation using UARTs (Universal Asynchronous Receiver Transmitters). UARTs are commonly available as a pair of circuits on a single chip; one UART being serial to parallel and the other parallel to serial.

The frequencies selected are for illustration of the invention, with the frequency of 19.2 baud being selected as the maximum microcomputer operating frequency. Serial data at 9.6 k baud is connected to the serial input 21 of UART 1 operating at 9.6 k baud. The parallel output 22 is connected to the parallel input of UART 2 operating at 19.2 k baud. The burst serial output from UART 2 is then connected to the serial input 23 of the microcomputer 20 running at 19.2 k baud. Since the microcomputer 20 runs at twice the continuous data rate at input 21 about half the computer's time is available for real time data processing. Burst data at 19.2 k baud is connected from the microcomputer serial output 24 to the serial input of UART 3 operating at 19.2 k baud. The parallel output 25 from UART 3 is then connected to the parallel input of UART 4 operating at 9.6 k baud.The data at the output 26 of UART 4 is quasi-continuous data at 9.6 k baud.

Figures 3 and 4 show respective alternative microcomputer arrangements which use serial in/parallel out ports and conversely parallel in /serial out. In the Figure 3 arrangement 9.6 k baud input quasi-continuous data is connected to the serial input 31 of UART 1 operating at 9.6 k baud. The parallel output 32 from UART 1 is connected to the parallel input of UART 2 operated at 19.2 k baud. Serial burst data at the serial output of UART 2 is then connected to the serial input of microcomputer 30 which as before is operated at 19.2 k baud.

Data is taken out from the microcomputer 30 via a parallel output port 34 and connected to the parallel input port of UART 4 operated at 9.6 k baud. This arrangement provides quasicontinuous output data at the serial output 35 from UART 4 but is more efficient than the Figure 2 arrangement in terms of provision of microcomputer processing power (because of the use of parallel output of data) and of reduction in the required number of circuit components. In Figure 4 serial data is connected to the serial input 41 of UART 1 operated at 9.6 k baud.

Data is connected from the parallel output port to a parallel input port of the microcomputer 40 operated at 19.2 k baud.

Burst serial data, after processing, is connected from the microcomputer serial output port 43 to the serial input of UART 3 operated at 19.2 k baud. The parallel output 44 from UART 3 is then connected to the parallel input to UART 4 operated at 9.6 k baud. As in previous arrangements the processed serial data appears quasi-continually at the serial output (45) from UART 4.

The above arrangements prevent total commitment of the microcomputer to the timing of serial in/serial out data, leaving spare time for the computer processor. One application of the invention is a one into two intelligent T switch, having a quasi-continuous serial data stream on an input line with a capability of transparent intelligent switching between two output lines. This represents a solution to a significant problem area as with the growth of multi-user computer systems there is a lack of a sufficient number of output lines from the computer. Often the usage of output lines is very inefficient when a sufficient number is provided for maximum use. Extra lines add to the cost and tie up facilities that may be underutilised.By providing an intelligent one into two T switch one line from a computer can be connected to two users who can then share the data sent over the line by in-line switching of the data in real time.

Figure 5 shows an intelligent T switch using the arrangement equivalent to that shown in Figure 4. Embedded in the serial data input, at 9.6 k baud say, are switching sequences. These may be an escape character followed by one of two other characters which can be recognised by the computer 40 to switch the stream of serial data at the output 45 to a selected one of two target lines. As shown the input and output UART 1 and UART 4 are operated at FIN (=9.6k baud) and the microcomputer 40 and UART 3 are operated at a higher frequency Fc of 19.2 k baud.

say. The serial data at output 45 is connected to the input of a switching circuit 50 which connects the input to either USER A or USER B via the respective outputs51,52 in dependence on whether input 53 is high or low. The microcomputer is programmed to detect the two routing direction escape sequences which are embedded in the input data. On detecting these sequences an output, connected to the switching circuit 50, is switched between high and low. The arrangement shown in Figure 5 has been operated at input data rates (FIN) between 1.2 k baud and 9.6 k baud with the microcomputer operating at 19.2 k baud.

The choice of escape sequences for data routing is determined by what escape sequences are already in use by the microcomputer and these could easily be changed by reprogramming a plug-in EPROM. The switching or change-over circuit could be a relay or a CMOS integrated circuit switch for example. A larger number of outputs than two could be connected to the microcomputer output port by using the appropriate larger number of escape sequences and a larger changeover circuit with the required number of input control signals from the microcomputer.

Claims

1. A microcomputer circuit for processing quasi-continuous serial data comprising: a terminal, input or output, to which the serial data is connected; at least one serial data port to the microcomputer through which asynchronous burst data is transmitted; and asynchronous baud rate conversion means connected between the microcomputer and the terminal for conversion between the higher frequency microcomputer burst data and the quasi-continuous data frequency at the terminal; the arrangement being such that the serial data flow is quasi-continuous while the computer operates on burst data.

2. A microcomputer circuit as claimed in claim 1 wherein frequency conversion is effected by means of at least one UART (Universal Asynchronous Receiver Transmitter).

3. A microcomputer circuit as claimed in claim 2 wherein a pair of back-to-back UARTs is connected between the input terminal to the circuit and a serial input port to the microcomputer and a pair of back-to-back UARTs is connected between a serial output port of the microcomputer and the output terminal of the circuit, the input UARTs being used to convert the input data to a higher burst baud rate for operation by the microcomputer and the output UARTs being used to convert the burst serial output data from the microcomputer to the quasi-continuous serial data at the output terminal.

4. A microcomputer circuit as claimed in claim 2 wherein a pair of back-to-back UARTs is connected between the input terminal of the circuit and a serial input port to the microcomputer to convert the input data to a higher burst baud rate for operation by the microcomputer and a single parallel-to-serial UART is connected between a parallel output port to the microcomputer and the output terminal of the circuit to convert the burst parallel output data from the microcomputer to the quasi continuous serial data at the output terminal.

5. A microcomputer circuit as claimed in claim 2 wherein a single serial-to-parallel UART is connected between the input terminal of the circuit on a parallel input port to the microcomputer to convert the quasi-continuous serial input data to the circuit to asynchronous parallel input data to the microcomputer and a pair of back-to-back UARTs is connected between a serial output port to the microcomputer and the output terminal of the circuit to convert the burst serial output data from the microcomputer to the quasi-continuous serial data at the output terminal.

6. An intelligent T switch operatively connecting a single input line to a selected one of a plurality of output lines comprising a microprocessor circuit as claimed in any one preceding claim and further including: a switching circuit having a single input connected to the output terminal of the microcomputer circuit and a plurality of outputs corresponding to the output lines; means to detect a plurality of escape sequences in the quasicontinuous serial data, each escape sequence corresponding to a respective predetermined connection between the input line and an output line; and switching signal means connected between the microcomputer and the switching circuit to provide an appropriate switching signal in dependence on the detected escape sequence.