GB2211991A - Electrical isolation of regions within semiconductor bodies - Google Patents

Electrical isolation of regions within semiconductor bodies Download PDF

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Publication number
GB2211991A
GB2211991A GB8825311A GB8825311A GB2211991A GB 2211991 A GB2211991 A GB 2211991A GB 8825311 A GB8825311 A GB 8825311A GB 8825311 A GB8825311 A GB 8825311A GB 2211991 A GB2211991 A GB 2211991A
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United Kingdom
Prior art keywords
silicon
ions
semiconductor material
voids
layer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8825311A
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GB2211991B (en
GB8825311D0 (en
Inventor
Dr Geoffrey Dearnaley
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UK Atomic Energy Authority
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UK Atomic Energy Authority
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Publication of GB8825311D0 publication Critical patent/GB8825311D0/en
Publication of GB2211991A publication Critical patent/GB2211991A/en
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Publication of GB2211991B publication Critical patent/GB2211991B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)

Abstract

A process for producing a buried dielectric or high-resistivity layer within a body of semiconductor material comprising the operations of implanting ions (2) of hydrogen or an inert gas into the body at an energy and dose such as to form a layer of discrete bubbles and/or voids (4) within the body (3) of semiconductor material and subsequently implanting ions of oxygen or nitrogen into the semiconductor material at an energy and dose such as initially to stabilise the bubbles and/or voids within the semiconductor material and then form a layer of oxide or nitride of the semiconductor material bridging the gaps between the said bubbles and/or voids. <IMAGE>

Description

Electrical Isolation of Regions within Semiconductor Bodies The present invention relates to the electrical isolation of regions within a body of a semiconductor substance as a step in the production of micro electronic devices.
In order to prqduce micro electronic devices it is necessary to isolate adjacent elements of the electrical circuit concerned and to provide isolation between active devices and underlying substrate material. It has been shown that this can be done by producing one or more buried layers of high-resistivity or dielectric material within a silicon substrate body by implanting sufficient ions of oxygen or nitrogen to create a continuous layer of silicon oxide or nitride where the ions come to rest in the silicon. However, the ion doses required are very high G1018 ions cm~2) and the process is a difficult one to carry out economically due to the need for high fluxes of ions at energies of 150-200 KeV. It is desirable therefore to find alternative techniques that can be more attractive economically.
It is known that when high doses ( > 10l7 ions cm~2) of inert gas ions are implanted into a body of silicon, bubbles of gas are formed within the silicon. If the silicon is then subjected to a post-implantation anneal, there is a tendency both for the bubbles to migrate through the silicon and for the inert gas to diffuse through the silicon and escape from the surface of the silicon so leaving voids in the silicon. It has been found, furthermore, that if oxygen is implanted into the silicon after the inert gas, then, either at the time of bombardment or during a subsequent anneal, it will migrate to the bubbles, associate with them and stop their migration when the silicon is annealed.
According to the present invention there is provided a process for producing a buried dielectric or highresistivity layer within a body of semiconductor material comprising the operations of implanting ions of hydrogen or an inert gas into the body at an energy and dose such as to form a layer of discrete bubbles and/or voids within the body of semiconductor material and subsequently implanting ions of oxygen or nitrogen into the semiconductor material at an energy and dose such as initially to stabilise the bubbles and/or voids within the semiconductor material and then form a layer of oxide or nitride of the semiconductor material bridging the gaps between the said bubbles and/or voids.
Suitable ion doses and energies for the formation of the bubbles and/or voids are at least 1014 ions cm~2 and the range 10-100 KeV, respectively. The ion energy required depends on the depth at which it is desired to produce the buried layer of dielectric or high-resistivity material. It is to be noted that the implantation energy required to produce any given penetration for hydrogen is about half that required for helium. Also if hydrogen is implanted to form the bubbles or voids, then the implantation temperature should be kept below about 7000K.
Suitable ion doses for the implantation of the oxygen or nitrogen are at least 1014 ions cm 2 The energy required is about twice that for helium ions and five times that required for hydrogen.
Preferably the semiconductor material is silicon.
The invention will now be described by way of example with reference to the accompanying drawing which illustrates the steps involved in producing a buried dielectric layer by a process embodying the invention.
Referring to the drawing, a body 1 of single crystal silicon is subjected to bombardment with a beam 2 of helium ions at an energy of about 75 KeV until a dose of about 1015 ions cm~2 is implanted. The temperature of the body 1 of silicon is maintained at about 6000K so that recrystallisation of the surface region 3 of the body 1 of silicon occurs continuously as the implanted helium ions pass through it. As a result of this bombardment an array of buried helium-filled bubbles 4 is formed as shown at (a) in the accompanying drawing.
The body 1 of silicon is then subjected to further bombardment with a beam 5 of ions of oxygen having an energy of 200 KeV until a dose of about 1015 ions cm 2 has been implanted. This time the temperature of the body 1 of silicon is maintained at between 800 and 9000K so as to facilitate the migration of the oxygen through the crystal lattice to the surfaces of the array of bubbles and/or voids 4. (Voids are now present because some of the helium will have diffused out of the bubbles as a result of the heating of the body 1 of silicon). Also, a layer 6 of silicon oxide is formed which bridges the gaps between the bubbles and/or voids 4, thus providing a continuous buried dielectric layer 7, as shown at (b) in the accompanying drawing.
Finally, the body 1 of silicon is annealed in an inert environment such as dry nitrogen in order to stablilise the structure and to remove any residual strain and/or disorder which may be present in the region of the body 1 of silicon above the buried dielectric layer 7.
If desired, the helium ions may be replaced by hydrogen ions and the oxygen ions by nitrogen ions. If the helium is replaced by hydrogen, then although the ion dose remains about the same, the energy required for a given depth of penetration is reduced by a factor of 2. The temperature of the body 1 of silicon needs to be reduced to about 5000K. The implantation energy and dose of the oxygen or nitrogen remains the same as before.
It should be noted that there is an upper limit to the ion dose of the hydrogen or helium arising from the need to prevent the bubbles and/or voids from being so densely packed that they may coalesce to form a continuous defect which will allow the upper region of silicon to become detached. This ion dose varies with temperature but in general is above 1018 ions cm' 2 Also, if required the ion implantations can be carried out through masks which define specific areas of the body of silicon which require to be provided with buried isolation.
As this practice is standard in the art of micro electronic device production it is not thought necessary to describe such a variation of the process according to the invention, specifically.
The invention is not restricted to the details of the foregoing example. For instance, the process might also be applied to other semiconducting materials, such as germanium, gallium arsenide, or layered structures of more than one semiconducting material, for the purpose of providing buried isolation.

Claims (12)

Claims
1 A process for producing a buried dielectric or highresistivity layer within a body of semiconductor material comprising the operations of implanting ions of hydrogen or an inert gas into the body at an energy and dose such as to form a layer of discrete bubbles and/or voids within the body of semiconductor material and subsequently implanting ions of oxygen or nitrogen into the semiconductor material at an energy and dose such as initially to stabilise the bubbles and/or voids within the semiconductor material and then form a layer of oxide or nitride of the semiconductor material bridging the gaps between the said bubbles and/or voids.
2 A process according to claims wherein the operation of forming a layer of discrete bubbles or voids within the body of semiconductor material comprises implanting the ions of hydrogen or inert gas to an ion dose within the range 10l4-10l8 ions cm 2 and with an energy within the range 10 - 100 keV, the ion energy being selected so as to form the layer of bubbles or voids at a predetermined depth within the body of semiconductor material.
3 A process according to claim 1 or claim 2 wherein the oxygen or nitrogen is implanted to an ion dose within the range 1014-10l8 ions cm 2 and with an energy such that the ions of oxygen or nitrogen come to rest within the body of semiconductor material at the same depth as the layer of discrete bubbles or voids.
4 A process according to any of claims 1 to 3 wherein the semiconductor material is silicon.
5 A process according to claim 4 wherein there is included the operations of bombarding the body of silicon with ions of helium having an energy of approximately 75 KeV until an ion dose of approximately 1015 ions cm~2 has been implanted the body of silicon being maintained at a temperature such that recrystallisation of the surface region of the silicon through which the ions pass occurs, bombarding the silicon body with ions of oxygen or nitrogen having an energy of approximately 200 KeV until an ion dose of approximately 1015 ions cm~2 has been implanted the body of silicon being maintained at a temperature such as to facilitate the migration of the oxygen or nitrogen through the crystal lattice to the surfaces of the discrete bubbles or voids and the formation of a layer of silicon oxide or nitride bridging the gaps between the discrete bubbles or voids thus providing a continuous buried dielectric layer within the silicon body, and subjecting the body of silicon to an annealing operation.
6 A process according to claim wherein there is included the operations of bombarding the body of silicon with ions of hydrogen having an energy of approximately 40 KeV until an ion dose of approximately 1015 ions cm~2 has been implanted the body of silicon being maintained at a temperature such that recrystallisation of the surface region of the silicon through which the ions pass occurs, bombarding the silicon body with ions of oxygen or nitrogen having an energy of approximately 200 KeV until an ion dose of approximately 1015 ions cm~2 has been implanted the body of silicon being maintained at a temperature such as to facilitate the migration of the oxygen or nitrogen through the crystal lattice to the surfaces of the discrete bubbles or voids and the formation of a layer of silicon oxide or nitride bridging the gaps between the discrete bubbles or voids thus providing a continuous buried dielectric layer within the silicon body, and subjecting the body of silicon to an annealing operation.
7 A process according to claim 5 wherein the body of silicon is maintained at a temperature of approximately 6000K during the bombardment with helium ions and at a temperature within the range 8-9000R during the bombardment with oxygen or nitrogen ions.
8 A process according to claim 6 wherein the body of silicon is maintained at a temperature of approximately 500K during the bombardment with hydrogen ions and at a temperature within the range 8-9000K during the bombardment with oxygen or nitrogen ions.
9 A process according to any of claims 5 to 8 wherein the annealing process comprises the operation of heating the body of silicon to a temperature of approximately 7000K in an inert atmosphere.
10 A process according to any of claims 1 to 4 wherein the semiconductor material is germanium, or gallium arsenide.
11 A process according to any preceding claim wherein the buried layer is formed within specific regions of the body of semiconductor material only.
12 A process for producing a buried dielectric or high resistivity layer within a body of semiconductor material substantially as hereinbefore described and with reference to the accompanying drawings.
GB8825311A 1987-10-30 1988-10-28 Electrical isolation of regions within semiconductor bodies Expired - Fee Related GB2211991B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB878725497A GB8725497D0 (en) 1987-10-30 1987-10-30 Isolation of silicon

Publications (3)

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GB8825311D0 GB8825311D0 (en) 1988-11-30
GB2211991A true GB2211991A (en) 1989-07-12
GB2211991B GB2211991B (en) 1991-02-20

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FR2681472A1 (en) * 1991-09-18 1993-03-19 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL
EP0660140A1 (en) * 1993-12-23 1995-06-28 Commissariat A L'energie Atomique Method for making a relief structure on a substrate from semiconductor material
EP0703608A1 (en) * 1994-09-23 1996-03-27 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Method for forming buried oxide layers within silicon wafers
EP0767486A2 (en) * 1995-10-06 1997-04-09 Canon Kabushiki Kaisha Semiconductor substrate and producing method thereof
FR2756847A1 (en) * 1996-12-09 1998-06-12 Commissariat Energie Atomique METHOD FOR SEPARATING AT LEAST TWO ELEMENTS OF A STRUCTURE IN CONTACT THROUGH THEM BY ION IMPLANTATION
EP0889505A1 (en) * 1997-07-03 1999-01-07 STMicroelectronics S.r.l. Process for cutting trenches in a single crystal substrate
WO1999039378A1 (en) * 1998-02-02 1999-08-05 S.O.I.Tec Silicon On Insulator Technologies Method for forming cavities in a semiconductor substrate by implanting atoms
US6225192B1 (en) 1996-05-15 2001-05-01 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
FR2849017A1 (en) * 2002-12-20 2004-06-25 Michel Bruel Multilayer capacitive structure micrometric/nanometric internal space having process region producing final structure internal space with space extending part interface zone parallel interior surface/distanced surface
US6790747B2 (en) 1997-05-12 2004-09-14 Silicon Genesis Corporation Method and device for controlled cleaving process
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US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
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US7320929B2 (en) * 2002-07-29 2008-01-22 Shin-Etsu Handotai Co., Ltd. Method of fabricating SOI wafer
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GB2211991B (en) 1991-02-20
GB8825311D0 (en) 1988-11-30

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