GB2211310A - Programmable multiplexer circuit - Google Patents

Programmable multiplexer circuit Download PDF

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Publication number
GB2211310A
GB2211310A GB8824338A GB8824338A GB2211310A GB 2211310 A GB2211310 A GB 2211310A GB 8824338 A GB8824338 A GB 8824338A GB 8824338 A GB8824338 A GB 8824338A GB 2211310 A GB2211310 A GB 2211310A
Authority
GB
United Kingdom
Prior art keywords
circuit
switch means
lead
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB8824338A
Other versions
GB8824338D0 (en
Inventor
Mark E Fitzpatrick
Yat-Sum Chan
Richard F Pang
Gary R Gouldsberry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gazelle Microcircuits Inc
Original Assignee
Gazelle Microcircuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gazelle Microcircuits Inc filed Critical Gazelle Microcircuits Inc
Publication of GB8824338D0 publication Critical patent/GB8824338D0/en
Publication of GB2211310A publication Critical patent/GB2211310A/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318502—Test of Combinational circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2839—Fault-finding or characterising using signal generators, power supplies or circuit analysers
    • G01R31/2841—Signal generators

Abstract

A multiplexing type circuit includes circuit portions having input and output leads associated therewith, to allow testing of the individual circuit portions, and further includes laser programmable fuses which allow selective disconnection of certain input and output leads as chosen to disconnect circuit portions from the overall circuit as appropriate.

Description

2 2 11 10
PROGRAMMABLE MULTIPLEXER CIRCUIT DESCRIPTION
This invention relates to circuits, more particularly, to multiplexing type cirzuits or circuits wherein selected input and output leads thereof can be disconnected.
A typical prior art multiplexing circuit 10, as shown in Fig. 1 of the accompanying drawings, includes a plurality of circuit port-lons 12t 14 16. gRach. one or more input leads 18, 20, 22 and one or more output leads 24, 26, 28 connected the- reto. The output leads 24, 26, 28 are in turn connected to an overall circuit output lead 30. Control leads 32, 34, 36 are individually connected to the respective circuit portions 12, 14, 16 so that the user of the circuit '10 may choose which circuit portion he wishes to have in operation, and then apply input signals thereto and receive output signals therefrom to be applied to the overall output lead 30 of the circuit.
In this manner, the functions of each circuit portion can be applied individually as needed.
Presently, it has been found desirable to initially provide a multiplexing circuit which inclUdes multiple circuit portions only one of which is to be chosen for ongoing future use, while the others may be -chosen for ongoing future use, while the others may be in4'.-ial-ly included in but eventually excluded front the overall circuit. In such case, it may be desirable to 3-1 test each of the circuit portions individually to determine its functionality, and then to choose the one which most optimally fits the needs of the user.
The multiplexing circuit of the type shown in Fig. 1 lends itself to that testing. However, such a circuit, subsequent to testing, includes the undesired circuit portions as part of the overall cir cuit, resulting in excessive use of power and a higher degree of loading on the previous and following circuits than is optimum.
The present invention accordingly provides a circuit comprising first circuit means connecting a first input lead of the circuit with an output lead of the circuit, second circuit means connecting a second input lead of the circuit with the output lead of the circuit, and means, preferably laser programmable means, for providing disconnection of a selected input lead of the circuit from the output lead of the circuit, whereby testing of the first circuit means and second circuit means can be undertaken prior to providing the disconnection.
The invention can thus provide a multiplexing type circuit which allows for testing of individual circuit portions thereof, and subsequent disconnection of any one or more of these circuit portions which are not desired as part of the overall circuit.
The invention is further described below, by way of example, with reference to Fig. 2 of the accompanying drawings, which shows the circuit incorporating the invention.
Shown in Fig. 2 is the overall multiplexing circuit 50 which incorporates the present invention.
As shown therein, the multiplexing circuit includes circuit portions 52A, 52B, 52C, 52D, each of which includes paired switching transistors 54A, 56A, 54B, 56B, etc. Each circuit portion includes input leads 58A, 60A, etc. which are connected to the respective gates of the transistors 54A, 56A, etc. These input leads 58A, 60A, etc. are connected respectively to overall corresponding input leads 59A, 61A, etc. of the circuit 50. The drains of the transistors 54A, 56A etc. have respective output leads 62A, 64A etc. connected thereto. The output leads 62A, 62B etc. in turn connect to an output lead 66 of the overall circuit 50, while the output leads 64A, 64B etc.
connect to an output lead 68 of the overall- circuit 50. The output lead 66 connects through a resistor 70 to a voltage supply terminal 72, while the output lead 68 connects through a resistor 74 to the voltage supply terminal 72. The sources of each pair of transistors 54A, 56A, etc. are connected and are in turn connected to a respective control line 76A, 76B etc.
which connects through a transistor 78A, 78B etc. and resistor 80A, 80B etc. to a ground terminal 82. A voltage supply terminal 84 is connected to the gate of each transistor 78A, 78B etc.
If it is chosen that, for example, the circuit portion 52A be tested, a high voltage signal is applied to the control lines 76B, 76C, 76D through resDective diodes 86B, 86C, 86D, each forward biased in the direction from a respective control input line to a respective control line, bringing the sources of the transistors 54B, 56B, 54C, 56C, 54D, 56D high, so that signals applied to those transistors will have no switching effect (the drains of those transistor already being high through being coupled to the voltage supply terminal 72). Thus, with only the control line 76A signal low, full testing of the circuit portion 52A can be undertaken by applying appropriate signals to the input lines 58A, 60A.
If it is then desired that the circuit portion 52B be tested, the signals to control lines 76A, 76C, 76D are taken high, while the signal to control line 542B is held low, and testing of that circuit portion 52B can be undertaken by applying appropriate signals to the 5 gates of transistors 58B, 60B.
The input leads 58A, 60A, 56B, 60B, etc. of each circuit portion include as a part thereof respective disconnectable links in the form of laser programmable fuses 94A, 96A, etc. Furthermore, each connection from the reference voltage terminal 84 to the gate of each transistor 78A, 78B, etc. respectively includes a disconnectable link in the form of a laser programmable fuse 98A, 98B, etc.
Once the desired circuit portion is chosen, the other circuit portions can be deleted fr-om the overall circuit 50 by blowing appropriate fuses. In such case, no power is consumed by the deleted circuit portions, and there is no speed penalty suffered by the remaining circuit portion upon such selective disconnection as described above. Blowing of the fuses which are part of the input and output leads reduces loading on the previous and following circuits, while blowing of the fuses connected with all transistors 78A, 78B, etc. avoids use of power as supplied by the voltage terminal 84.
It will readily be seen that each of these circuit portions is testable independently of any of the others, so that power needed to test each such circuit portion can be applied individually thereto.

Claims (18)

CLAIMS (WALITY
1. A circuit comprising:
first circuit -c.eans co-,nect--lnz a first input lead of the circuit wit', an output,ea= of the circuit; second circuit means con-.,z;,t-irg a second input lead of the circuit with output. lead of the circuit; and means for providing selective disconnection of the first input lead of the circuit from the output lead of the circu-4-'L-.; whereby test-ing cif first means and of the second circuit -,ieans can be undertaken prior to providing the disconnection.
is
2. A circuit as in c-".;->-im 1 wherein the power needed to test either the first and second circuit means can be applied individually thereto.
3. A circuit as claimed in claim 1 c:- 2 wherein no power is consumed by the first circuit means upon selective disconnection of the first input lead from the output lead.
4. A circuit as claimed in claim 1, 2 or 3 wherein there is no speed penalty suffered by the second circuit means due to loading from the first circuit means upon selective disconnection of the first input lead from the output lead.
5. A circuit as claimed in claim 1, 2, 3 or 4 wherein the means for providing selective disconnection comprise a disconnectable link. 30
6. A circuit as claimed in claim 1, 2, 3 or 4 wherein the means for providing selective disconnection comprise laser programmable means.
7. A circuit as claimed in claim C. wherein the means for providing selective disconnecti--n comprise a laser programmable fuse.
8. A circuit as claimed in any preceding c-laim wherein the means for providing selective disconne,7tion are part of the first input lead.
9. A circuit comprising:
first switch means having an input lead connected to a first input lead of the circuit, and an output lead connected to an output lead of the circuit; second switch means having an input lead connected to a second input lead of the circuit and an output lead connected to the output lead of the circuit; a f irst control line connected to the first switch means; a second control line connected to the switch means; a disconnectable link in the output lead of the first switch means; and a disconnectable link in the output lead of the second switch means.
10. A circuit as claimed in claim 9 having a disconnectable link in the input lead of the first switch means, and a disconnectable link in the input lead of the second switch means.
11. A circuit as claimed in claim 9 or 10 wherein the first switch means has a second output lead connected to a second output lead of the circuit, the second output lead of the first switch means including a disconnectable link, and wherein the second switch means has a second output lead connected to the second output lead of the circuit, the second output lead of the second switch means including a disconnectable link.
12. A circuit as claimed in claim 9, 10 or 11 wherein the first switch means has a second input lead connected to a third input lead of the circuit, the second input lead of the first switch means including a disconnectable link, and wherein the second switch means has a second input lead connected to a fourth input lead of the circuit, the second input lead of the second switch means including a disconnectable link.
13. A circuit comprising:
first switch means having a first input lead connected to a first input lead of the circuit, and a second input lead connected to a second input lead of the circuit; second switch means havina a first input lead connected to a third input lead of the circuit, and a second input lead connected to a fourth input lead of the circuit:
the first and second input leads of the first switch means including respective disconnectable links; the first and second input leads of the second switch means including respective disconnectable links; the first switch means including first and second output leads connected respectively to first and second output leads of the circuit, the second switch means including first and second output leads connected respectively to the first and second output leads of the circuit; the first and second output leads of the first switch means including respective disconnectable links; the first and second output leads of the second switch means including respective disconnectable links; first and second load means connecting the first and second output leads respectively of the circuit with a first voltage supply terminal; a first control line connected t6o the first switch means; third load means connecting the first control line to a second voltage supply terminal; a first control input line; fourth load means connecting the first control input line to the first control line; a second control line connected to the second switch means; fifth load means connecting the second control line to the second voltage supply terminal; a second control input line; and sixth load means connecting the second -4Inpu.,'- control line to the second control line.
14. A circuit as claimed in claim 13 wherein each of the fourth and sixth load means comprisiRs a diode forward biased in the direction from the respective control input line to the respective control line.
15. A circuit as claimed in claim 13 or 14 comprising a first transistor having a first current handling terminal connected to the first control line and second current handling terminal connected to the third load device, and a second transistor having a first current handling terminal connected to the second control line and a second current handling terminal connected to the fifth load device.
16. A circuit as claimed in claim 13, 14 or 15 wherein each of the switch means comprise a pair of transistors, each having a first current handling terminal, a control terminal, and a second current handling terminal, the second current handling terminals of the transistors are connected together and to the control line associated with that switch means, b the first current handling, terminals are c,-,nnec',-_e.5A to respective output leads of that switch means, and the control terminals of the transistors are conrected to respective input leads of that switch r-,teans. 5
17. A circuit as claimed in an, one cf claims 916 wherein each disconnectable link comprises a laser programmable fuse.
18. A multiplexing circuit substantially as herein described with reference to Fig. 2 of the accompanying drawings.
1 Publish; d1989.t The Pt.-t Otate House 66171 High HWborn, London WC1R 4TP. Purther copies maybe obtained from The Patent Orace.
Sales Branch, St MarY ffi.., State H..e, 6617l Hloh.H.1b.,-, Cray, Orpington, Kent BR5 3RD. Printed by Multiplex techniques ItcL St Maxy Cray, Kent, Con. 1187
GB8824338A 1987-10-20 1988-10-18 Programmable multiplexer circuit Withdrawn GB2211310A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/111,389 US4897836A (en) 1987-10-20 1987-10-20 Programmable connection path circuit

Publications (2)

Publication Number Publication Date
GB8824338D0 GB8824338D0 (en) 1988-11-23
GB2211310A true GB2211310A (en) 1989-06-28

Family

ID=22338257

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8824338A Withdrawn GB2211310A (en) 1987-10-20 1988-10-18 Programmable multiplexer circuit

Country Status (4)

Country Link
US (1) US4897836A (en)
JP (1) JPH02124628A (en)
DE (1) DE3835647A1 (en)
GB (1) GB2211310A (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367208A (en) 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US5281553A (en) * 1987-07-02 1994-01-25 Bull, S.A. Method for controlling the state of conduction of an MOS transistor of an integrated circuit
US5780323A (en) * 1990-04-12 1998-07-14 Actel Corporation Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
US5614756A (en) * 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
US5166556A (en) * 1991-01-22 1992-11-24 Myson Technology, Inc. Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits
KR930008655B1 (en) * 1991-07-02 1993-09-11 삼성전자 주식회사 Leakage protected switch
US5485031A (en) * 1993-11-22 1996-01-16 Actel Corporation Antifuse structure suitable for VLSI application
US5502413A (en) * 1994-01-31 1996-03-26 Motorola, Inc. Switchable constant gain summing circuit
US5917229A (en) * 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
US5808351A (en) * 1994-02-08 1998-09-15 Prolinx Labs Corporation Programmable/reprogramable structure using fuses and antifuses
US5572409A (en) * 1994-02-08 1996-11-05 Prolinx Labs Corporation Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board
US5726482A (en) * 1994-02-08 1998-03-10 Prolinx Labs Corporation Device-under-test card for a burn-in board
US5813881A (en) * 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
US5537108A (en) * 1994-02-08 1996-07-16 Prolinx Labs Corporation Method and structure for programming fuses
US5834824A (en) * 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5962815A (en) * 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
US5528179A (en) * 1995-05-31 1996-06-18 Texas Instruments Incorporated Constant capacitance prgrammable transconductance input stage
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5767575A (en) * 1995-10-17 1998-06-16 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US5872338A (en) * 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
DE59813158D1 (en) 1997-09-18 2005-12-08 Infineon Technologies Ag Method for testing an electronic circuit
US6034427A (en) * 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092589A (en) * 1977-03-23 1978-05-30 Fairchild Camera And Instrument Corp. High-speed testing circuit
WO1982002096A1 (en) * 1980-12-15 1982-06-24 Corp Ivac Electrical monitoring system
EP0066729A1 (en) * 1981-06-04 1982-12-15 International Business Machines Corporation Method of testing the operation of a programmable logic array
GB2105050A (en) * 1978-08-25 1983-03-16 Racal Automation Ltd Improvements in and relating to circuit testing apparatus
US4390837A (en) * 1980-08-25 1983-06-28 Kevin Hotvedt Test unit for a logic circuit analyzer
GB2149129A (en) * 1983-11-04 1985-06-05 Membrain Ltd Automatic test equipment
EP0207249A2 (en) * 1985-06-04 1987-01-07 Texas Instruments Deutschland Gmbh Electrically programmable logic array

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4206443A (en) * 1978-02-17 1980-06-03 Westinghouse Electric Corp. Protective load disconnect unit for remote load control systems
US4347602A (en) * 1978-05-31 1982-08-31 Vdo Adolf Schindling Ag Circuit arrangement for time division multiplex data transmission with a bus system
FR2498385A1 (en) * 1981-01-20 1982-07-23 Modeles Fs SAFETY ELECTRIC CURRENT DISTRIBUTION DEVICE ON LIGHT FLYING EQUIPMENT EQUIPPED FOR INSTRUMENT FLIGHT
US4387503A (en) * 1981-08-13 1983-06-14 Mostek Corporation Method for programming circuit elements in integrated circuits
US4409683A (en) * 1981-11-18 1983-10-11 Burroughs Corporation Programmable multiplexer
US4556975A (en) * 1983-02-07 1985-12-03 Westinghouse Electric Corp. Programmable redundancy circuit
JPS59162711A (en) * 1983-03-04 1984-09-13 株式会社東芝 Protective relaying device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092589A (en) * 1977-03-23 1978-05-30 Fairchild Camera And Instrument Corp. High-speed testing circuit
GB2105050A (en) * 1978-08-25 1983-03-16 Racal Automation Ltd Improvements in and relating to circuit testing apparatus
US4390837A (en) * 1980-08-25 1983-06-28 Kevin Hotvedt Test unit for a logic circuit analyzer
WO1982002096A1 (en) * 1980-12-15 1982-06-24 Corp Ivac Electrical monitoring system
EP0066729A1 (en) * 1981-06-04 1982-12-15 International Business Machines Corporation Method of testing the operation of a programmable logic array
GB2149129A (en) * 1983-11-04 1985-06-05 Membrain Ltd Automatic test equipment
EP0207249A2 (en) * 1985-06-04 1987-01-07 Texas Instruments Deutschland Gmbh Electrically programmable logic array

Also Published As

Publication number Publication date
GB8824338D0 (en) 1988-11-23
US4897836A (en) 1990-01-30
DE3835647A1 (en) 1989-05-03
JPH02124628A (en) 1990-05-11

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