GB2210757A - Phase shift keyed digital data modulator - Google Patents

Abstract

A phase shift keyed digital data modulator comprises means (1,4,3,5 Figs 4,6) for providing digital samples of a carrier signal, and of a data signal. Multiplier means multiplies representations of the carrier and data signals to provide a phase shift keyed output signal having relatively low amplitude sidebands. Separate ROM's may be provided for the carrier and data samples (Figs. 4,6). Instead of multiplication, a single ROM may be addressed by both carrier and data state signals to provide a modulated output. <IMAGE>

Description

PHRASE SHIFT KEYED DIGITAL DATA MO W LSTOR The present invention relates to digital data transmission systems of the kind using a modulated carrier signal.

Digital data transmission is normally concerned with transmitting a stream of binary data - a stream of l's and O's. The carrier can be modulated in a variety of ways, such as amplitude modulation, frequency modulation, and phase modulation; with digital data, the modulation is sometimes described as amplitude, frequency or phase shift keying. The present invention is a type of phase shift keyed (PSK) digital data modulator. In this type of modulation, a data logic 0 is represented by a carrier phase of Oo and logic 1 by a carrier phase of 1800.

Since phase is not an absolute quantity, some form of data encoding is normally used to define data polarity.

The usual means to implement phase shift keying is to multiply together the carrier signal and the digital data signal. The circuit which implements this function is variously called a multiplier, mixer or PSK modulator and for convenience will hereinafter be referred to as a multiplier.

9n important consideration in many circumstances is the bandwidth of the resulting modulated signal; it is often important to minimize the amount of signal outside the frequency band assigned for the signalling. This is of particular significance for digital signalling, because the basic data signal is binary, with ideally infinitely steep transitions between O's and l's, and such transitions tend to generate extensive (large amplitude) sidebands outside the assigned band. It is of course possible to bandpass filter the modulated signal to remove these sidebands, but although the theory and design of bandpass filters is long established and well developed, such fiLters are complicated and expensive.

9n alternative to bandpass filtering the modulated signal exists in a phase shift keyed digital data modulation system. The binary digital data signal can have its high frequency components removed by smoothing the transitions between binary 0 and 1 states and between binary 1 and 0 states.

This system may be implemented in analog terms by using a multiplier for multiplying the carrier signal by the data signal (in which 0's and l's are represented by equal and opposite voltages), with the data signal being passed through a lowpass filter before being fed to the multiplier. This method will be referred to hereinafter as phase shift keying with data prefilter.

It will be realized, of course, that the resulting modulated carrier signal will have a certain amount of amplitude modulation in addition to the phase modulation which carries the data signal. In fact, it will have an approximately V-shaped dip in amplitude at each transition of the data signal between differing data bits. The frequency spectrum of the modulated carrier is simply that of the filtered data signal, translated up in frequency and mirrored on either side of the carrier frequency. Thus the bandwith of the modulated signal will be exactly twice the bandwidth of the filtered data signal.

Figure 1 of the accompanying drawings shows a known analog implementation of phase shift keying with data prefilter. The data signal is +V or -V depending on its binary state. This signal feeds an analog multiplier (MUL) via a lowpass filter (tPF). The multipler is also fed by a carrier oscillator (OSC).

The operation of the circuit of Figure 1 is illustrated by Figure 2. The first line shows a typical bit sequence for the states of a data signal 001011. The next line shows the waveform after filtering through the lowpass filter LPF. ks sewn, the lowpass filter r,pF smooths the waveform and it is this filtered waveform which is fed to the multiplier MUL. The carrier oscillator waveform is not shown, but this is a continuous high frequency signal of constant amplitude.

The last line in Figure 2 indicates the nature of the multiplier output; this consists of a high frequency signal, the phase of which is indicated by the 0 and 1800, as appropriate, and the envelope of which is shown.

The multiplier MUL multiplies the two signals fed to it, namely the filtered data signal and the carrier signal. The amplitude of the output thus varies with the amplitude of the filtered data signal, and the phase is 0 or 1800 depending on the sign of the filtered data signal. The assignment of the phase for the first bit is arbitrary, but the phase of the modulated signal thereafter is fully determined.

It will be seen that the output signal is a phase modulated signal, with transitions between opposite phases being achieved by amplitude reductions of the signal passing through zero. These amplitude reductions will in general not affect a phase sensitive detector, which will react to the brief loss of signal at such transitions in much the same way as it would react to a burst of interference.

Whilst the use of a lowpass filter is much less complex, and hence less expensive, than a bandpass filter the integrated circuit implementation is still relatively difficult and it is an object of the present invention to provide a PSK digital data modulator which overcomes this problem.

according to the present invention there is provided a phase shift keyed digital data modulator comprising means for providing a digital sample of a carrier signaL, means for providing a digital sample of a data signal, means for storing the digital samples of the carrier and data signals and multiplier means for multiplying representations of the carrier and data signals to provide a phase shift keyed output signal having relatively low amplitude sidebands.

The digital carrier and data samples may be converted to analog form and passed through separate lowpass filters before being applied to the multiplier means. Xlternatively, the digital form of the carrier and data samples may be applied to the multiplier means and the output of the latter applied to a sign determining means to determine the correct sign of the PSK output signal. Separate or common means for storing the carrier and data samples may be provided and the multiplier means may be incorporated into common storage or memory means.

It will be seen that the present invention is a novel form of digital implementation of a digital data transmission system employing phase shift keying with data prefilter. Both the data and carrier signals are represented by digital samples which exist within the system as digital, binary-encoded words. These words are held for times referred to as the data sample period and the carrier sample period, respectively, before the digital data and carrier samples are changed to the next value. Figures 3A and 3B of the accompanying drawings show examples of the digital data and carrier sample waveforms, respectively. These are the waveforms which would be seen at the output of a digital-to-analog converter to which the respective digital sample words are sequentially applied. Figure 39 shows that a data transition occupies 15 data sample periods and Figure 3B shows that a carrier cycle occupys 30 carrier sample periods. These are, of course, only for illustration and any number of sample periods may be employed in both cases. It will be realized that the time scales of Figures 39 and 3B are different. In fact, the carrier signal of Figure 3B may go through several full cycles for each count or step in Figure 39.

The data and carrier samples may be stored in read only memories (ROMs) which are sequentially referenced to produce the required digital sample sequences. These sample sequences may then be digitally multiplied to form a digital sample sequence which, when digital-to-analog converted, results in the required PSK signal.

Three embodiments of the present invention will be described in greater detail, by way of example, with reference to Figures 4 to 7 of the accompanying drawings, in which: Figure 4 is a block diagram of a first embodiment, Figure 5 is a diagram useful in explaining the operation of the first embodiment, Figure 6 is a block diagram of a second embodiment, and Figure 7 is a block diagram of a third embodiment.

Referring first to Figure 4, the first embodiment comprises a carrier state machine (CSM) 1 which is cycled continuously at a high rate by carrier clock signal (CCLK) applied on an input line 2 so that each state represents a different phase of the carrier signal. The output from the CSM 1 is fed into a read only memory (ROM) 3, the state of the CSM output being an address to reference a particular word within the ROM. The contents of the particular word is a digital, binary-encoded version of the carrier waveform as shown in Figure 3B at the phase (or time) represented by the address word supplied to the ROM 3 from the CSM 1.

Figure 5 shows the required transitions between states in an N state machine. State transitions are in the sequence shown for increasing transition numbers t Following transition t 2N-2 from state 2 to state 1, the sequence starts over again with transition t from state 1 to state 2, i.e, transicions proceed continuously up and down Figure 5. The period of the resultant carrier signal is thus (2N-2) times the carrier sample period.

TABLE 1 STATE SIGN MAGNITUDE COSINE WXVE (i) BIT ADDRESS BITS VALUES 16 1 111 1.0 15 1 110 0.978 14 1 101 0.914 13 1 100 0.809 12 1 011 0.669 11 1 010 0.5 10 1 001 0.309 9 1 000 0.105 8 0 000 -0.105 7 0 001 -0.309 6 0 010 -0.5 5 0 011 -0.669 4 0 100 -0.809 3 0 101 -0.914 2 0 110 -0.978 1 0 111 -1 . O Y = COS [(N-i).t ] i [-(N-1) ] An example of this is shown in Table 1 above for a N=16 state machine. However, it will be appreciated that any number of states is of course possible.In this example, the CSM 1 is a 4-bit device and follows the sequence starting at the bottom of Figure 5, going up the top of the Figure, then down to the bottom, then up again, and so on, i.e.:0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111, 1110 1101, 1100, 1011, 1010, 1001, 1000, 0000, 0001, 0010 0011, 0100, 0101, 0110, 0111, 0110, 0101, etc., The contents of the ROM 3 is a digital representation of the cosine wave values (Y.). Figure 3B shows the cosine wave read out from the ROM 3 for the case of 30 samples per carrier cycle, using the data in Table 1.

There is also provided in the embodiment of Figure 4 a data state machine (DSM) 4, which is cycled intermittently and at a much lower rate than the CSM 1 to represent the timing of the smoothed transitions of the filtered data signal. Each state represents a sample time in the smoothed transition. The output of the DSM is fed into a second ROM 5, the state of the output of the DSM being an address to -reference a particular word within the ROM 5. The contents of the particular word is a digital binary- encoded version of the data signal waveform as shown in Figure 3R at the time represented by the address word supplied to the ROM 5 from the DSM 4.

The DSM 4 is clocked by a data clock signal (DCLK) which may be the same as CCLK, a sub-division of it or a completely separate frequency.

If desired, a sign determining circuit may be employed in the embodiment of Figure 4 between the ROM 3 and the D9C 6 and between the ROM 5 and the DAC 7.

Figure 5 also shows the required transitions between states in an N state machine. For steady portions (i.e.

runs of l's or O's) of the digital data stream (DAT), the DSM 4 stays in a single state depending only on the digital data bit polarity. For example, the data DSM 4 might reside in state N when sending a logic 1 data bit, and state 1 when sending a logic 0 data bit. In state N, the particular word addressed within the ROM 5 would be the maximum positive value, and in state 1 the most negative value.

When a transition occurs in the digital data stream, the DSM 4 changes states, clocked by data clock DOLK, untiL the opposite polarity maximum state is reached.

Thus if a logic 0 data bit has just finished being sent, the DSM 4 will be in state 1. If the next data bit to be sent is a logic 1, state transitions tl, t2, will occur until state N is reached, when transitions stop. Similarly, if a logic 1 bit has just finished, the DSM 4 will be in state N. If the next bit is a logic 0, state transitions tN, tN+l, 2N-2 2 will occur until state 1 is reached, when transitions stop.

The above described transitions between states 1 and N and vice-versa are made to take place over a proportion of a digital data bit period equal to (N-l) times the data sample period. If this proportion is the whole bit period then the effective digital lowpass filtering applied has a low cut-off frequency and some PSK output signal energy reduction occurs, i.e. this results in relatively narrow bandwidth, but also significant signal energy (and hence signal-to-noise ratio) loss in a given situation. However if the transitions are made to occur over a small proportion of a data bit period (say a quarter), then there is less lowpass filtering applied, wider PSK output signal bandwidth, but also a lower signal-to-noise ratio loss.

The values held in the data ROM 5 are preferably made to represent a half cycle of a cosine wave exactly as for the carrier ROM 3. Thus, each data bit transition consists of a half cycle cosine wave, also known as a Hanning Function. Note however that wave shapes other than a half-cycle cosine wave are also possible and are included within the scope of the invention.

Table 1 is also an example of the correspondence of relevant parameters for the DSM 4.

The digital values read out of ROMs 3 and 5 are fed to digital-to-analog converters (DOC) 6 and 7, respectively. The output of the DAC 6 is of the form shown in Figure 3B and output of DAC 7 is of the form shown in Figure 3x. The outputs of the D9C's 6 and 7 are low pass filtered using low complexity filters 8 and 9, respectively, although in some cases these may be omitted.

The outputs of the lowpass filters 8 and 9 are fed to a multiplier 10, the output of which is the desired PSK signal.

Advantage may be taken of the symmetry of the cosine carrier to minimise circuitry and this is achieved by the second embodiment of Figure 6. The output from the CSM 1 is split into a sign bit and a number of magnitude address bits. Only the magnitude address bits need be sent to the ROM 3. The sign bit is applied to a sign determining circuit (SIGN) 11 along with a data sign bit to determine the correct sign for the final output. Thus the states held within the CSM 1 are split into two halves which differ only in the sign bit. Referring to Figure 5 again, it can be said that state 1 represents the most negative carrier digital sample value and state N the most positive value. Thus states 1 to N/2 would output a negative sign bit, and states N/2 +1 to N a positive sign bit.Apart from the sign bit, the address output to the ROM 3 would be the same for pairs of states 1 and N, 2 and N-1, 3 and N-2, ----N/2 and N/2 +1 (assuming N is an even number, although it could be an odd number).

The digital values read out of the ROMs 3 and 5 are fed to a digital multiplier MUL 12. The output of the digital multiplier 12 is fed to the sign determining circuit 11. The output of the sign determining circuit (DAC) 11 is fed to a digital-to-analog converter (DOC) 13, which produces the final output signal which corresponds generally to the PSK signal of Figure 2.

There is, of course, high frequency quantizing noise associated with the output signal, which must be removed using conventional continuous time analog filtering.

However, this filtering is much simpler than would be required if no data prefiltering were used.

The third embodiment of the invention (Figure 7) is a modification of the second embodiment of Figure 6 in as much as the ROMs 3 and 5 and the multiplier 12 are replaced by a single ROM 14 arranged functionally as a matrix. The outputs from the CSM 1 and the DSM 4 provide a row and column address to the ROM 14. The contents of the ROM 14 the values which would have been obtained by the multiplication of the two values addressed in ROMs 3 and 5 in the second embodiment described above in relation to Figure 6.

The other elements of the third embodiment 1, 4, 11 and 13 are the same as in the second embodiment.

It will be understood that the sign determining circuits 11 of the embodiments of Figures 6 and 7 may be omitted with the ROMs 3, 5; 14 storing both polarities.

Alternatively, a sign determining circuit could be located after ROM 3 and/or ROM 5 with a feed from the CSM 1 and/or DSM 4.

Claims (9)

1. A phase shift keyed digital data modulator characterised in that it comprises means (1) for providing a digital sample of a carrier signal, means (4) for providing a digital sample of a data signal, means (3,5;14) for storing the digital samples of the carrier and data signals, and multiplier means (10;12;14) for multiplying representations of the carrier and data signals to provide a phase shift keyed output signal having relatively low amplitude sidebands.

2. A modulator according to claim 1, characterised in that means (6,7) are provided for converting the digital carrier and data samples to analog form before being applied to the multiplier means (10).

3. A modulator according to claim 1, characterised in that the digital carrier and data samples are applied to the multiplier means (12) and in that sign determining means (11) are provided to determine the correct sign of the phase shift keyed output signal.

4. A modulator according to claim 3, characterised in that the means for storing the digital carrier and data samples and the multiplier means are all embodied in memory means (14) the output of which is applied to the sign determining means.

5. A modulator according to claim 4, characterised in that the memory means is a read only memory (14).

6. A modulator according to any of claims 1 to 3, characterised in that the means for storing the carrier and data samples are read only memories (3,5).

7. A modulator according to any of the preceding claims, characterised in that the means for providing the carrier samples is a carrier state machine (1) and the means for providing the data samples is a data state machine (4).

8. A modulator according to claim 7, characterised in that the carrier state machine (1) is clocked at a greater rate than the data state machine (4).

Amendments to the claims have been filed as follows 1. x phase shift keyed digital data modulator characterised in that it comprises means (1) for providing a digital sample of a carrier signal, means (4) for providing a digital sample of a data signal, means (3,5;14) for storing the digital samples of the carrier and data signals, and multiplier means (10;12;14) for multiplying representations of the carrier and data signals to provide a phase shift keyed output signal having relatively low amplitude sidebands.

2. A modulator according to claim 1, characterised in that means (6,7) are provided for converting the digital carrier and data samples to analog form before being applied to the multiplier means (10).

3. A modulator according to claim 1, characterised in that the digital carrier and data samples are applied to the multiplier means (12) and in that sign determining means (11) are provided to determine the correct sign of the phase shift keyed output signal.

4. A modulator according to claim 3, characterised in that the means for storing the digital carrier and data samples and the multiplier means are all embodied in memory means (14) the output of which is applied to the sign determining means.

5. A modulator according to claim 4, characterised in that the memory means is a read only memory (14).

6. A modulator according to any of claims 1 to 3, characterised in that the means for storing the carrier and data samples are read only memories (3,5).

7. x modulator according to any of the preceding claims, characterised in that the means for providing the carrier samples is a carrier state machine (1) and the means for providing the data samples is a data state machine (4).

8. A modulator according to claim 7, characterised in that the carrier state machine-(l) is clocked at a greater rate than the data state machine (4).

9. A phase shift keyed digital data modular substantially as hereinbefore described with reference to and/or as illustrated in any one or more of the accompanying drawings.