GB2208776A - Switching device - Google Patents

Abstract

A first switching section, or space switch, SS has ports EP for connection to communications lines T of a network, and further ports IP, and can set up connections between selected ports. The ports IP are connected to ports TP of a second switching section, or time switch, TS by means of which selected slots of a multiplexed signal structure, of selected ports, can be interconnected. <IMAGE>

Description

Switching Device The present invention relates to switching devices for communication systems.

According to the present invention there is provided a switching device for a communications system comprising first and second switching sections the first switching section having a plurality of first ports for connection to communication lines and a plurality second ports connected to ports of the second switching section, and being arranged in operation to connect selected ones of the first ports to respective selected other ones of the first ports or to respective selected ones of the second parts, the second switching section being operable, in accordance with a multiplex signal structure comprising successive frames each containing a plurality of slots, to effect connection between selected slots of multiplen signals at the selected first ports connected thereto.

One embodiment of the I invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram cf a switching device in accordance with tne invention; Figure 2 is a block diagram of the space switch SS of the device of figure 1; Figure 3 is in block diagram of the time switch TS of the device of figure 1; and Figure 4 is a block diagram of one individual switching unit TSU of the switch of figure 3.

Figure 1 illustrates in outline a node of a telecommunications trunk network. It assumes digital, bit serial, synchronous transmission at a single rate - for example the CCITT G703 Recommendation rate of 139264 kbit/sec, referred to below as 140Mbits. Transmission is formatted within a framing structure having a number of slots permitting usage of the system on a time division multiplex basis. One possible format is a 544 bit frame consisting of 64 usable slots of 8 bits each, a 12 bit frame alignment signal, an error check word, and 12 bits for synchronisation, supervisory signalling and spare bits It follows that each slot represents a capacity of 2048 kbit/s, referred to below as 2 Mbit/s.

The slot itself may have been formed by multiplexing a number of sources; however this is immaterial for present purposes since, at slot level, the node is transparent.

The node has a cross-connect switch having a plurality of 140 Mbit/s (external) bidirectional ports which are connected via interfaces I to trunk lines T or local 140 Mbit/s links L. Some ports may instead communicate via muitiplexer/demultiplexer units M which have 2 Mbit/s links (or multiples of 2 Mbit/s).

The function of the cross-connect switch is (a) to connect any desired port to any other desired port (in a non-blocking manner);.

(b) to switch one or more slots of a selected port to the same or different slot(s) of another port.

It is assumed that a connection between port A and port 3 (and similarly for slot A and slot B) will result in incoming traffic on port A being output on port B and vice versa - and indeed this is likely to be the most usual situation - but the architecture to be described is capable of switching forward and return paths independently. The switch comprises two parts, a space switch section SS and a time switch section TS. All the ports of the switch (the external ports) are connected to ports EP of the space switch which however has additional ports (internal ports IP) connected to ports TP of the time switch. The space switch is capable of connecting any port or ports to any other port or ports and therefore can set up essentially transparent communication by linking any of the trunk lines T, local links L and units M with any other one of those.The external and internal ports of the space switch are indistinguishable within the space switch (in the sense that they are physically equivalent) so that the space switch can also link any external port, via an internal port, to the time switch.

The time switch operates to switch not ports, but slots; it can switch any slot on any of its ports through to any slot on any other of its ports.

Thus (for example) a trunk line may be switched by the space switch SS to another trunk line either directly, or via the time switch TS so that different slots are linked to slots of another trunk line.

The construction of the space switcn SS is illustrated in figure 2. It shows a 32x32 (ie m by m) 140 Mbit/s crosspoint switch made up of four 16x16 crosspoint switch units CS1....CS4. These may be integrated circuits. however, the 32x32 crosspoint switch could comprise a different number of crosspoint switcn units of different dimensions.

In figure 2 each bidirectional port Pi...P32 is shown as a separate input line and an output line as shown by the arrows (as mentioned above, the internal and external ports are inoistinguishable at this level). Each input is fed to a horizontal pair CS1 and CS2 (or CS3 and CS4) of switches, whilst each output is fed by a vertical pair CSl and CS3 (or CS2 and CS4). It will be appreciated that a bidirectional connection from P2 to P32 (for example) requires actuation of a crosspoint in CS4 (for the forward path) and another in CS1 (for the return path).

In order to actuate a crosspoint, it is necessary to apply an eight bit address (from an address bus AB) and an enable signal to the relevant switch; the instruction is then latched by the switch - ie the selected crosspoint remains enabled until a further command is received. A control unit CU supplies a five bit row address, five bit column address and a strobe signal; the highest order bit of each address and the strobe signal are decoded (decoder AD) to apply an enable signal to the input EN of the appropriate switch whilst the remaining eight bits are applied to the bus. The control unit responds to external signals to produce the appropriate signals to set up the desired connections; it may also perform other functions such as maintaining a map of switch states, or performing routine line testing.

In the event that (as would be the case in practice) larger arrangements are required, a larger matrix of switches could be constructed.

A time switch TS, having eight ports ..... .8(though again a larger switch would be required for a practical noae) is shown in figure 3. The input of each port is supplied to a serial to parallel converter S/P, which produces an 8-oit output. In the interests of speed the 8-Dit division is not synchronised with tne frame structure. The 8-Dit output is supplied to an interface unit II which serves to recognise the frame alignment word and then converts the incoming 8-bit words into 8-bit words corresponding to respective time slots, providing an alignment control signal FA indicating the timing of the frame. The interface unit II may also include a cyclic redundancy check, and other overhead functions.

In general, the frame alignment of signals at different ports will not be the same, and therefore the next stage is a variable delay buffer store B which is controlled by the control signal FA so that all such stores output, at the same time, the 8-bits corresponding to a given time slot position within the frame. The output of each buffer store is connected to a respective one of 8 column lines (C1..C8) of an 8x8 time switch matrix.

Each element of the matrix is essentially a frame store; each row line (R1...R8) of the matrix is essentially a bus on which an output frame may be assembled by reading out desired slots from selected frame stores. Figure 3 shows a convenient form of construction in which sixteen time switch units TSU each contain four frame stores. One such unit is shown in figure 4.

Firstly the operation of one element within the unit of figure 4 will be described - that between an input IA (from one of the buffers B of figure 3)and an output OA connected to one of the row (bus) lines of figure 3.

The input IA (which is assumed to include a ninth, parity bit) is connected to the data input of a dual-port read-write memory RAM/AA, and a frame of data is read in with the aid of addresses from a time slot counter TSC. The architecture of the dual port memory is such that this frame is availaoie for readout untii the process of writing in the next frame is complete. During that process, the address sequence from the counter T5C is also used to access a time slot map (dual-port read-write memory RAM/MA).

The map has one location for each of the 64 time slots of the frame which is to be formed on the column bus. Each location has eignt bits (b7 to bO) plus a parity bit. Bits bO to D5 form an address which is applied to the read address input of the frame store RAM/AA and indicate which slot (if any) of the input frame supplied to input IA of this unit is to form the output for the time slot in question. Bits b6 and b7 indicate whether the time slot in question is in fact to be derived from that port, and if it is, enable a tri-state buffer TSB/A to place the 8 bits read out from the frame store onto the row bus.

Thus the element represented by RAM/AA, in conjunction with other elements connected to the same column line, can enable an output frame to be formed, each slot of which can be derived from any slot of any input port, as determined by the relevant maps.

Looking now at the other components in figure 4, a second frame store, RAM/BA receives a frame from an input IB, and, like RAM/AA can output slots via the buffer TSB/A, with the aia of a multiplexer MUX/A. The map RAM/MA also addresses RAM/AA, bit 7 indicating that a slot from either RAM/AA or RAM/BA is to be output (and hence controlling the buffer TSB/A). The lower 6 bits of the map location are connected to both frame stores and signify a location in one or other of them according to the state of bit b6 (which controls the mutiplexer MUX/A).

The contents of the map RAM/MA can be changed since its data input and input address input are connected via an interface MI to a microprocessor data bus MB (common to all 16 time switch units of figure 3). In order that its contents may be read whilst being continously read out under control of the time slot counter TSC, its data output is connected to the input of a duplicate map RAM/DA which can be read via the microprocessor bus MB and interface MI. As well as components, RAM/AA, RAM/BA, RAM/MA, RAM/DA, MUX/A and TSB/B, components RAM/AB, RAM/BB, RAM/MB, RAM/DB, MUX/B ana TSB/B are providea to serve similar functions for a second output OB.

Returning to figure 3, each column line is connected to an interface unit Ol for reinsertion of a checksum, frame alignment code and other overhead or signalling information, followed by a parallel to serial converter P/S which provides a 140 Mbit/s output to the respective internal port IP1...8.

It will be noted that one map store (RAM/MA or RAM/MB) serves two frame stores. In principle it would be possible for it to serve more, or even all the frame stores feeding the same output point, since only one frame store will deliver a slot to a given output during any one slot period. The arrangement shown is a convenient one, permitting the time switch unit of figure 4 to be made as a single integrated circuit without an excessive number of external connections.

A microprocessor controllea control unit TCU is connected te the bus MB for controlling operation of the time switch.

To effect control of the node, a node control unit (not shown) may be provided to issue instructions to the time switch and space switch control units TCU,SCU. This could be controlled manually, but in a practical situation tne control units of several nodes of a trunK network might be connected by communication links to a central controller which would then co-ordinate the routing of links between nodes, or via several nodes.

As an example of the operation of the node shown, assume that links are to De set up between slots 40 and 49 of a trunk line connected to port P3 of the space switch, and, respectively, slot 7 of a trunk line connected to port P10 and slot 44 of a local link connectea to port P12. This is indicated diagrammatically in figure 5. It is assumed that ports P25-P32 of the space switch are the internal ports, connected to ports TP1-TP8 respectively of the time switch.

The links referred to require three internal port connections to be set up; whichever these are is arbitrary and P25/TP1, P26/TP2 and P27/TP3 are assumed.

This requires: 1 In the space switch; Actuation of a crosspoint in CS4 to connect P3 input to P25 output.

Actuation of a crosspoint in CSl to connect P25 input to P3 output Actuation of a crosspoint in CS4 to connect PlO input to P26 Actuation of a crosspoint in CS1 to connect P26 input to PlO Actuation of a crosspoint in CS4 to connect P12 input to P27 Actuation of a crosspoint in CS1 to connect P27 input to P12 2 In the time switch TP1 leads to TP2 via RAMJAB of TSUil, so location 7 of RAM/MB indicates (bit 36) RAM/AB and contains (bits DO-b5) address 40 TP2 leads to TPi via RAM/BA of TSUll, so location 40 of RAM/MA indicates (Dit b6) RAM/BA and contains (bits bO-b5) address 7.

Similarly,location 44 of RAM/MA of TSU21 indicates RAM/AA and aodress 49 and location 49 of RAM/MA of TSU12 indicates RAM/AA and address 44.

The appropriate data being written into the maps by tne control unit TCU.

In practice of course, other slots would also be in use, and further connections can be set up in the same manner.

Claims (5)

1. A switching device for a communications system comprising first and second switching sections, the first switching section having a plurality of first ports for connection to communication lines and a plurality of second ports connected to ports of the second switching section, and being arranged in operation to connect selected ones of the first ports to respective selected other ones of the first ports or to respective selected ones of the second ports, the second switching section being operable, in accordance with a multiplex signal structure comprising successive frames each containing a plurality of slots, to effect connection between selected slots of multiplex signals at the selecteo first ports connected thereto.

2. A switch accoroing to claim 1 in which the second switching section comprises frame store means for storing frames input thereto, ana map store means into which can be written cata representing addresses within the frame store means from which slots are to be reaa out to desired outputs.

3. A switch according to claim 2 in which the second switching section has n ports each oeing a two-way port consisting of an input stage and an output stage, the frame store means comprises n groups of n frame stores, in each group ail tne stores have aata inputs connected to the same input port ane each store has a data output connecteo to a aifferent output stage, and the second switching means also has addressing means to read in succession from the map store means items of data for successive slots of frames to be output, each item indicating, for each output port, from wnich group of stores (if any) a slot is to be read ana the address within the relevant one of the stores of the group.

4. A switch according to any one of Claims 1 to 3 in which the first switching section comprises a space switch of m by m crosspoint switch units, where m is equal to the sum of the plurality of first ports and the plurality of second ports.

5. A switching device substantially as herein described with reference to the accompanying drawings.