GB2205701A - Diode clamp - Google Patents

Abstract

A clamping circuit comprises a capacitor 15, a diode 17, a reference voltage source 18, 19, 20, and a high input impedance butter 10, 13. An input 16 is connected to one plate of the capacitor 15, whose other plate is connected to the diode 17 and the input of the butter 10, 13. The diode 17 is connected to the voltage reference source, which preferably comprises two series-connected diodes 19, 20 forward biased by a resistor 18. The buffer preferably comprises a transistor 10 connected in the common collector configuration. <IMAGE>

Description

CLAMP The present invention relates to clamps. Such clamps may be used to provide precision clamping, for instance of video signals.

According to a the invention, there is provided a clamping circuit comprising an input connected to a first plate of a coupling capacitor. a diode connected between a second plate of the coupling capacitor and a reference voltage source, and a high input impedance buffer connected between the second plate of the capacitor and an output.

Preferably the buffer comprises a transistor connected in the common collector configuration.

It is thus possible to provide a clamping circuit which is capable of substantially reducing clamping level variations and of operating with wide bandwidth signals such as video signals. A preferred application of such a circuit is in the system disclosed in British Patent Application No 8527006, in which precision clamping may be necessary in order to achieve reliable mapping into and out of the amplitude domain.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 illustrates schematically a conventional type of clamping circuit; Figure 2 is a simplified equivalent circuit diagram of a known clamping circuit; Figure 3 shows graphs against time of voltages appearing in the circuit of Figure 2; Figure 4 is an equivalent circuit diagram of a known clamping circuit; Figure 5 shows graphs against time of voltages appearing in the circuit of Figure 4; Figure 6 is a schematic diagram of a clamping circuit constituting a preferred embodiment of the invention; Figure 7 shows equivalent circuits of the type of clamping circuit shown in Figure 6; and Figure 8 is a circuit diagram of a clamping circuit constituting another preferred embodiment of the invention.

Clamping circuits are used to maintain the direct voltage or current level of an alternating voltage or current signal at a predetermined value. Figure 1 illustrates two forms of a known type of clamping circuit. The arrangement on the left hand side of Figure 1 provides positive clamping: the negative peaks of the input signal are clamped to a reference voltage so that the waveform is above the clamping level. The arrangement shown at the right hand side of Figure 1 provides negative clamping: the positive peaks of the input signal are clamped to the voltage reference so that the waveform is below the clamping level.

As shown in Figure 1, a signal voltage source Es having a source impendance Rs is connected via a capacitor C to a circuit VR which also provides a reference voltage. A diode D is connected between the capacitor C and the reference voltage. The difference between the two arrangements shown in Figure 6 is merely in the polarity of the diode D.

Figure 2 is an equivalent circuit of the arrangement shown in Figure 1, in particular the positive clamping arrangement. The output voltage of the clamping circuit is indicated by Eo and the diode has been replaced by its equivalent circuit comprising an ideal diode Di, its forward resistance Rf, and its reverse resistance Rr.

Assuming that the reverse resistance Rr is infinite or at least so large as to have negligible effect on operations of the circuit, the circuit operation is as follows. At time t = 0, the capacitor is initially discharged and a square wave having an amplitude E symmetrical about zero volts is supplied by the source Es, as shown in Figure 3. Assuming that the signal Es is initially negative, the capacitor charges via the diode Di which is forwardly biased at a rate determined by its time constant Tc which is equal to C. (Rf + Rs).

At time t the polarity of the input signal reverses so that the diode Di is reverse biased and charging of the capacitor C stops. Provided Tc is substantially less than the period tl, the capacitor will be substantially fully charged and cannot discharge, or can discharge at only a negligible rate, through Rr. During the period between tl and t2, the output voltage Eo is therefore equal to 2E.

When the polarity of the input signal reverses at time t2, the capacitor C remains charged so that the output voltage Eo is clamped to zero.

Thus, in this idealized equivalent circuit of the clamping circuit of Figure 1, the capacitor C always remains fully charged and has a voltage E across it and, following initial charging of the capacitor ie after time tl, the diode Di remains reverse biased.

Figure 4 shows a more realistic equivalent circuit of the positive clamping circuit shown in Figure 1. The reverse resistance Rr of the diode Di is now assumed to be finite and, in addition, the input impedance Ri of a circuit connected to receive the output voltage Eo is shown. Figure 5 illustrates the operation of this equivalent circuit.

The charging time constant Tc for the capacitor during the interval to time tl is now given by the expression: Tc = C (((Rf. Ri)/(Rf + Ri)) + Rs) This time constant is less than that of the idealized equivalent circuit of Figure 7, so that the capacitor C will again be fully charged by time tl.

In the period between tl and t2 when the input signal has risen to a value +E, the diode becomes reverse biased but the capacitor C is now able to discharge through the finite reverse resistance Rr of the diode but more importantly through the input impedance Ri, the time constant of this discharge being given by the expression: C.(Rr. Ri)/(Rr + Ri) In general, the input impedance Ri is much less than the actual reverse resistance Rr of the diode Di, so that the time constant becomes C.Ri. Thus, at time t2 when the input signal changes to -E and the output voltage becomes E c - E, the output of the clamping circuit effectively becomes negative because the voltage E c across the capacitor C has fallen below the value E.Between times t2 and t3, the diode D. again becomes forward biased allowing the capacitor to recover its charge. This continues for successive cycles of the input signal, with the capacitor alternately charging and discharging. As a result, the output waveform is distorted with respect to the input waveform.

Figure 6 illustrates schematically a clamping circuit constituting a preferred embodiment of the invention. This clamping circuit is shown connected to a signal voltage source Es having an internal impedance Rs. The circuit comprises an input coupling capacitor C, a diode D, and a reference voltage source V1 all of which are equivalent to the similar elements shown in Figure 6. The clamping circuit further comprises a high input impedance buffer in the form of a transistor TR connected as an emitter-follower with an emitter load resistor R . A power supply for the emitter-follower is shown at V2. The output of the clamping circuit is taken from across the resistor R .

Figure 7 shows an equivalent circuit of the clamping circuit of Figure 6 together with a similar equivalent circuit for negative clamping. The emitter follower has been idealized as an element E having a gain approximately equal to 1 and a substantially infinite input impedance. The diode D has again been shown as an ideal diode Di with a forward resistance Rs and a reverse resistance Rr. Operation of this circuit is similar to that of the equivalent circuit shown in Figure 4 except that the input impedance Ri is no longer significant. Thus, the capacitor discharge or voltage droop between times tl and t2 becomes approximately zero and at least sufficiently small to be insignificant. This clamping circuit therefore approaches very closely the ideal operation as illustrated in Figure 3.

It has been found possible to reduce variations of the clamping level, caused by different input waveforms, to less than 20 millivolts and even to less than 10 millivolts, whereas conventional clamping circuits could produce variations of many hundreds of millivolts when subjected to similar "worse-casetj waveforms. Also, the effective isolation of the clamp permits adjustment of the other parameters to the signal in order to interface to succeeding circuitry. In particular, impedance matching of the signal may be achieved by choosing a suitable value for the emitter resistor Ro and the DC level can be made compatible with the succeeding circuitry by adjusting the reference voltage V1, thus permitting direct connection if required.

Operation of the clamping circuit has been described on the basis of present understanding, but it is acknowledged that this may not be completely understood. In particular, the base-emitter junction of the transistor TR may have some significance on the operation of the clamping circuit.

The clamping circuit shown in Figure 8 comprises a transistor 10 whose collector is connected to a positive supply line 11 and whose emitter is connected to an output 12 of the clamping circuit and via an emitter load resistor 13 to a negative supply line 14. The base of the transistor 10 is connected to one plate of a capacitor 15 whose other plate is connected to an input 16 of the clamping circuit. The base of the transistor is also connected to the cathode of a diode 17. The anode of the diode 17 is connected to a circuit for producing a reference voltageacomprising a series connection of a resistor 18 and forwardly-biased diodes 19 and 20 connected between the positive supply line 11 and a common line 21.

Operation of the clamping circuit shown in Figure 8 is essentially the same as operation of the circuit shown in Figure 6. However, the clamping circuit of Figure 8 has certain advantageous features. Thus, variations in forward voltage drop with temperature of the diode 17 and the base-emitter junction of the transistor 10 are effectively cancelled by corresponding variations in the series-connected diodes 19 and 20.

Thus, the clamping action is substantially insensitive to temperature variations. It is also possible to match the forward voltage drops so that the clamped level at the output 12 is equal to the potential of the common line 21. The negative supply line 14 is normally more negative than the common line 21 so as to allow the output signal to be developed across the resistor 13.

However, in certain circumstances, it is possible for the negative supply line 14 to function also as the common line 21, as indicated in the circuit of Figure 6.

The clamping circuit of Figure 8 gives accurate and stable operation and, with suitable choice of the transistor 10 and the diodes 17, 19 and 20, and suitable choices of values for the other components, can operate over a range of frequences from close to zero to several tens of megahertz. A practical embodiment has functioned reliably and accurately up 35 MHz.

Claims (4)

1. A clamping circuit comprising an input connected to a first plate of a coupling capacitor, a diode connected between a second plate of the coupling capacitor and a reference voltage source, and a high input impedance buffer connected between the second plate of the capacitor and an output.

2. A clamping circuit as claimed in Claim 1, in which the buffer comprises a transistor connected in the common collector configuration.

3. A clamping circuit as claimed in Claim 2, in which the reference voltage source comprises two series-connected diodes arranged to be forward biased.

4. A clamping circuit substantially as hereinbefore described with reference to and as illustrated in Figures 6 to 8 of the accompanying drawings.