GB2201816A

GB2201816A - High speed digital processor

Info

Publication number: GB2201816A
Application number: GB8704699A
Authority: GB
Inventors: Shin-Tsai Lin
Original assignee: Mitac Inc
Current assignee: Mitac Inc
Priority date: 1987-02-27
Filing date: 1987-02-27
Publication date: 1988-09-07
Also published as: GB8704699D0

Abstract

The present invention provides a high speed digital processor having an erasable programmable read only memory, EPROM, and a random access memory, RAM, equipped as the program memory and also having a circuit control device for loading the program data in the erasable programmable read only memory into the random access memory when the processor is turned on. The access time of the random access memory can meet the requirement of the instruction cycle of the central processing unit of the processor. Furthermore, the replacement of the programmable read only memory with the erasable programmable read only memory in a conventional high speed digital processor can significantly reduce the cost of the high speed digital processor. <IMAGE>

Description

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The present invention relates to a high speed digital processor and more particularly to a processor using an erasable programmable read only memory and a random access memory as the program memory thereof.

Due to the rapid development of the information science and the necessity to process data very fast, many kinds of high speed digital processors have been created recently. The central processing unit (abbreviated CPU) of a high speed processor usually has a very fast instruction cycle for fetching the data in the memory.

To32010 is a CPU manufactured by Texas Instrument Inc.

U.S.A. having an instruction cycle of 200 ns. To complement the high speed instruction cycle of the CPU in a processor, the access time of the program memory must be in the area of below 100 ns. For this particular reason, conventional high speed processor is always equipped with a bipolar programmable read only memory as the program memory because of the very rapid access time thereof.

It has been noted that high speed digital processor using programmable read only memory (hereinafter abbreviated as PROM) as the program memory thereof has several disadvantages. First, during the initial stages of program development , the program will be revised after test from to time. Once the program is changed, a new PROM must be fabricated and embedded. This results in elevated research and development costs. In addition, the cost of each PROM is relatively high.

Second, the apparatus used for embedding PROM, conventionally known in the computer field as PROM writer, may be structurally different from its counterparts depending on the preference of the manufacturer. However, the laboratory of a computer memory manufacturer usually only has apparatus for embeddings erasable programmable read only memory (hereinafter abbreviated as EPROM). Therefore, the installation of PROM writer will also cause the cost of PROM to be increased.

Third, the manufacturer of the processor usually has the obligation to furnish the user with a new PROM if the operation system program is revised or changed. This will also increase the cost of the processor.

Fourth, despite the disadvantage of PROM that the embedded program data can not be erased, the price of PROM is much more expensive than the same of an EPROM.

It is, therefore, the main object of the present invention to provide an EPROM and a random access memory (hereinafter abbreviated as RAM) to be used as the program memory of a high speed digital processor in avoiding those disadvantages of a conventional processor using a PROM as the memory.

The main feature of the present invention is to provide an EPROM for storing the program data which shall be downloaded to a RAM when the processor is turned on.

Since the access time of the RAM is about 85 to 100 ns., it is compatible with the instruction cycle of the CPU in the processor.

Another feature of the present invention is to provide a circuit control means which will be responsive to the reset signal when turnning on the processor and cause the program data stored in the EPROM to be downloaded into the RAM.

A further feature of the present invention is to provide a program counter during the download of the program data. The system address bus is preferred as the program counter without introducing other complicated circuitry.

A still further feature of the present invention is to provide a clock divider for slowing down the instruction cycle of the CPU of the processor during the download of the program data from EPROM to RAM.

Another feature of the present invention is to provide a high speed digital processor wherein the program memory can include a plurality of RAMs for the expansion of the memory space. The program data stored in the EPROM can be downloaded into the various RAMs.

Accordingly, the high speed digital processor comprises a CPU; a program memory means which includes an EPROM for storing the program data and a RAM; and a download control circuit means responsive to the reset signal of the turning on of the processor for actuating said CPU to write the program data of the EPROM into the RAM for completing the download operation.

Those and other objects, features and advantages of the high speed digital processor according to the present invention will become apparent from the following detailed description of the preferred embodiment of the present invention with reference to the accompanying drawings, wherein: Fig. 1 is a block diagram illustrating the high speed digital processor of the present invention; and Fig. 2 is an embodiment of a circuit diagram of the high speed digital processor of the present invention.

Referring to Fig. 1 which shows a block diagram illustrating the high speed digital processor of the present invention, the processor comprises a CPU which outputs a system address bus and a system data bus, and a program memory which includes an EPROM and a RAM connected between said two buses. The program data is stored in the EPROM before the processor is turned on and will be downloaded into the RAM after the processor is turned on.

It is to be noted that by replacing the conventional PROM with an EPROM and a RAM, the program data can be revised or changed very easily by simply erasing the stored parent program data in the EPROM and embedding the new program data into the EPROM. Also, by using a RAM having an access time below 100 ns., the program memory is compatible with the high speed instruction cycle of the CPU of the processor.

The high speed digital processor also comprises a download circuit means for downloading the stored program from the EPROM to the RAM. The circuit means includes a first flip-flop F.F.1 , a second flip-flop F.F.2 ,a first buffer BUF1 and a second buffer BUF2. The circuit means also includes an oscillation block OSC connected by a 1/2 divider and also connected to the clock output CLK of the first flip-flop F.F.1. The output of the divider is connected to a multiplexer block MUX and a write timing control block 10 which is further connected to the terminal WR of the RAM through an OR Gate 11.

When the processor is turned on, the reset signal of turning on serves as the download trigger signal which is fed to the first flip-flop F.F.1 causing the output Q and Q to become low and high respectively. The low output of Q resets the CPU of the processor. In the meantime, the high output of Q of the first flip-flop causes the second flip-flop to have a high and low output of Q and Q respectively. The high output of Q of the second flipflop F.F.2 disenables the first buffer BUF1 from fetching data along the system data bus. And in the meantime, the low output of Q of the second flip-flop F.F.2 enables the terminal OE of the EPROM to output program data.Also in the meantime, the low output of Q of the second flip-flop F.F.2 enables the second buffer BUF2 of the CPU to fetch the no operation code from the second buffer.

The output of CLK of the first flip-flop F.F.1 actuates the OSC and the divider to slow down the clock of the CPU through a multiplexer MUX. Besides, the write timing control 10 will actuate the write operation of the program data into the RAM. Since the system data bus is blocked by the first buffer BUF1, the CPU will only fetch the no operation code Arorn the second buffer nUF2 at 2 slow down instruction cycle to fit the access time of the EPROM. Meanwhile all the program data stored in the EPROM is downloaded into the RAM.

When the program counter reaches the maximum address of the RAM, the download operation is completed and a download ending signal is generated and fed to the second flip-flop F.F.2. The output of the second flip-flop F.F.2 at Q and 0 will then be reversed to enable the first buffer BUF1 and disenable the second buffer BUF2. Now the download operation is completed and the CPU of the high speed digital processor starts to fetch the program data now stored in the RAM. Since the access time of the RAM is below half of the instruction cycle of the CPU, the processor can process the data at a high speed.

Referring to Fig. 2 which shows a circuit diagram of the embodiment of the high speed digital processor, it can be readily observed and understood that the CPU is a Tri32010 I.C., the EPROM consists of two 8-bit 2764 IC, and the RAM consists of four 6116 IC. The download control circuits are best shown and illustrated in Fig. 2 by referring to the corresponding blocks shown in Fig. 1, such as first and second flip-flops, first and second buffers, write timing controller, download ending signal generator, system address bus, etc. The operation of the circuit shown in Fig. 2 is exactly the same as that of the block diagram shown in Fig. 1 and will not be detailed further.

It is to be noted that if the program data stored in the EPROM has a larger space than the same in a single RAM, then we can add more RAMs for downloading the program data in another block of EPROM. If the instruction cycle of the CPU is 200 ns. and there are 4K program data stored in the EPROM, the total time for completing the download operation will be 400 x 10 x 4 x a 10 = 16 x 10 second. Therefore, at almost the same time the processor is turned on, the program data is downloaded into the RAM. Consequently, the CPU can immediately fetch the data stored in the RAM or RAMs.

It is to be noted that the high speed digital processor of the present invention has been described by way of preferred embodiment. It is possible that other changes or modifications may be made by those skilled in the art without departing from the scope of the present invention.

Claims

CLAIMS:

1. A high speed digital processor comprising a central processing unit (CPU) for fetching and processing data and a program memory means for storing program data wherein said program memory means includes an erasable programmable read only memory (EPROM) for storing the program data; a random access memory (RAM) for storing the program data when the processor is turned on; and a downloading control circuit means responsive to the turn on of the processor which actuates the said CPU to download the program from tne said EPROM to said RAM.

2. A high speed digital processor as claimed in Claim 1 further comprising an address bus and a data bus connecting said CPU to said EPROM and RAM.

3. A high speed digital processor as claimed in Claim 1 wherein said downloading control circuit means further comprises a program counter for counting the advance of the address of said RAM for generating a download ending signal when said RAM reaches the maximum thereof.

4. A high speed digital processor as claimed in claim 3 wherein said program counter is an address bus connecting said EPROM and said RAM.

5. A high speed digital processor as claimed in Claim 1 wherein said program memory means further comprises a plurality of added RAMs for expanding the program space of the processor.

6. A high speed digital processor as claimed in Claim 1 wherein said downloading control circuit means further comprises a circuit means for slowing down the instruction cycle of the said CPU for complementing the access time of the said EPROM for downloading the program data into the said RAM.

7. A high speed digital processor as claimed in Claim 2 wherein said data bus further comprises a buffer connected thereto for disenabling the data bus during the downloading operation period.

8. A high speed digital processor as claimed in Claim 2 wherein said data bus further comprises second buffer connected thereto for providing a no operation code to be fetched by said CPU during the downloading operation period.

9. A high speed digital processor as hereinbefore described with reference to the accompanying drawings.