GB2198247A

GB2198247A - Circuit for measuring small differences in capacitance

Info

Publication number: GB2198247A
Application number: GB08727453A
Authority: GB
Inventors: Frank Schmucker; Frank Assmann; Reinhard Arend; Dietmar Pensold; Wilfried Westhus
Original assignee: WEINERT E MESSGERAETEWERK
Current assignee: WEINERT E MESSGERAETEWERK
Priority date: 1986-11-27
Filing date: 1987-11-24
Publication date: 1988-06-08
Also published as: DE3732756A1; GB8727453D0

Description

2198217

-1DESCRIPTION A CIRCUIT ARRANGEMENT FOR MEASURING SMALL DIFFERENCES IN CAPACITANCE.

The present invention is concerned with a circuit arrangement for measuring small differences in capacitance for use in evaluating measured values using capacitive sensors, such as the measurement of nonelectrical magnitudes in process measurement technology and in particular, but not exclusively, for measuring angles using capacitive sensors.

In "Rundfunk/Fernsehen/Elektronik", Berlin 33 (1984), Issue 11, page 717, H.Hoffrichter describes a capacitive measuring transducer, a capacitive bridge circuit being used which is supplied with a periodic signal.

The measuring capacitors are a component of the bridge circuit, whose bridge diagonal voltage is evaluated when the measuring capacitances change. The disadvantages of bridge circuits are the necessity for close tolerance components within the bridge and the large temperature drift. It is thus not possible to use them in widely varying ambient temperatures.

DD-PS 186 873 describes a circuit arrangement for the capacitive acquisition of measured values, which comprises two measuring capacitors, each of which can be charged by a current source and discharged by way of a parallel transistor. One measuring capacitor is charged -2until a trigger threshold is reached, while the other measuring capacitor is short-circuited by a transistor. When the trigger threshold is reached, the charged measuring capacitor is short-circuited and the other measuring capacitor is charged such that an oscillation is obtained at the output of the arrangement, whose mark-space ratio is proportional to the difference in capacitance of the two measuring capacitors.

A disadvantage of this arrangement is the effect of temperature drift, which is caused by the collectoremitter barrier capacitance of the switching transistors, which are connected in parallel with the measuring capacitors, and which, particularly in the case of small changes in measuring capacitance, causes severe falsifications to the measured values. It is also disadvantageous that, in order to adjust the zero point, the mark-space ratio of 1:1 at the output of the arrangement can only be adjusted with a relatively high expenditure on circuit balance, since the varying trigger threshold values of the comparators can only be balanced by adjusting the current source or by inserting balance capacitors in addition to the measuring capacitors.

It is an object of the present invention to provide a circuit arrangement for the capacitive acquisition of measured values, which provides high measuring accuracy with a low expenditure on balancing, and is insensitive to wide variations in ambient temperature. Measurement 1 error is to be kept to a minimum even in the event of wide variations in ambient temperature.

In accordance with the present iniention there is provided a circuit arrangement for measuring small differences in capacitance, wherein two oppositely adjustable measuring capacitors are connected to respe2tive square-wave generators so as to influence their oscillating frequencies, and wherein a respective presettable counter is connected downstream of each square-wave Eenerator, the output of the first counter being connected to the release input of the second square-wave generator and the input of a negator, the output of the second counter being connected to the reset input of the first counter, and the output of the negator being connected to the release input of the first square-wave generator and the reset input of the second counter, whereby a periodic output signal is obtained at the output of the negator whose mark-space ratio alters in proportion to the difference in capacitances of the two measuring capacitors.

To adjust the zero point, a simply balanceable periodic output signal is generated with a mark-space ratio of 1:1.

According to the preset value at the first counter, the second squarewave generator is blecked until the maximum counter reading is reached. When the counter reaches its m,-.iximum counter reading, the second square wave generator is released, the second counter is reset by way of the negator and the first square-wave generator is blocked.

When the second counter reaches its maximum counter reading, the first counter is reset by the output signal of the second counter, the second square-wave generator is blocked and the first square-wave generator is released. A periodic output signal is thus obtained at the output of the negator, whose mark-space ratio is proportional to the change in the difference in capacitaince Gf the two measuring capacitors. The two counters, which are arranged as fr:quency dividers, make it possible to evaluate a piurality of measuring cycles, as a result of which a high degree of measureMEnt accuracy is obtained and it is possible to adjust the zero point in a simple manner by corresponding adjustment of the counter reading.

The invention is described further hereinafter, by way of example only, with reference to the accompanying drawing (Fig. 1) which is a block circuit diagram of one embodiment in accordance with the present invention.

Two measuring capacitors Cl and C2, whose values are altered in opposite directions by a capacitive angular value sensor, are arranged to forn, frequencydetermining elements connected to square-wave generators 1,2 respectively. A counter 3,4 which is arranged as a g 1 -5frequency divider, is disposed at the output of each of the square-wave generators 1,2 respectively. The output of the first counter 3 is connected to the input of a negator 5 and the release input of the second square-wave generator 2. in accordance with the preset value on the first counter 3, the square-wave pulses from the squarewave generator 1 are counted by the first counter 3 until the maximum counter reading is reached. When the maximum counter reading of the first counter 3 is reached, the latter counter alters its output voltage, by which the square-wave generator 2 is released and the squarewave generator 1 is blocked by way of the negator 5. Furthermore, the second counter 4 is reset by the output signal of the negator 5. When the second counter 4 reaches its maximum counter reading, the first counter 3 is reset from the output of the second counter 4, as a result of which the square-wave generator 2 is blocked and the square-wave generator 1 is released by way of the negator 5. As a result, a periodic output signal is obtained at the output of the negator 5, whose deviation from a mark- space ratio 1:1 is proportional to the change in the difference in capacitance of the two measuring capacitors Cl,C2.

A low pass filter 6, which is connected downstream of the negator 5, converts the periodic output signal into an analog quantity, so that a direct voltage is 1 obtained at the output of the low pass filter 6, which is representative of the magnitude of the change in the difference in capacitances between the measuring capacitors C1,C2, and hence to the magnitude of the measured angular value.

......................................... o.

............

Claims

-7CLAIMS

1. A circuit arrangement for measuring small differences in capacitance, wherein two oppositely adjustable measuring capacitors are connected to respective square-wave generators so as to influence their oscillating frequencies, and wherein a respective presettable counter is connected downstream of each square-wave generator, the output of the first counter being connected to the release input of the second square- wave generator and the input of a negator, the output of the second counter being connected to the reset input cf the first counter, and the output of the negator being connected to the release input of the first square-wave generator and the reset input of the second counter, whereby a periodic output signal is obtained at the output of the negator whose mark-space ratio alters in proportion to the difference in capacitances of the two measuring capacitors.

2. A circuit arrangement as claimed in claim 1, wherein a low pass filter i.s connected downstream of the negator so that the output of the circuit arrangement is a d.c. level representative of the magnitude of the change in the difference in capacitance between the two measuring capacitors.

3. A circuit arrangement for measuring smal 1 differences in capacitance, substantially as hereinbefore described, with reference to and as illustrated in the accompanying drawing.

Published 1988 t The Patent Office. State iouse, 66171 High Holborn, London W01R 4TP. Further copies may be obtained from The Patent Lunce. Sales Branch, St Mary Cray. Orpington, Kent BRS 3RD- Printed by Mu2tiplex techniques ltd. St Mary Cray. Kent. Con. 1187. Qn I - I;=nh_ St Marv Crav. orpington, rLenT, no o- - -u.Y