GB2197096A - Microcode monitor - Google Patents

Abstract

A hardware microcode monitor 22 monitors the efficiency of microcode sequences held in a microcode memory 14 in a data processing system under test 10 for use by a monitored processor 12. The hardware monitor 22 monitors microcode addresses 16 and abort signals 20 from the monitored processor 12 under control from the monitored processor clock signal 24. In the testing mode, the abort signals control for example branching and jumping within microcode sequences, or other signals pertinent to the test. The hardware monitor 22 uses start and stop addresses within microcode sequences to accumulate elapsed time and number-of-times-of-use information concerning selected microcode sequences. The accumulated test results are selectably transferable to an analysing processor 26 for analysis of the efficiency of the selected microcode sequences, comparing for example the times taken for performance of distinct microcode sequences achieving the same purpose. <IMAGE>

Description

SPECIFICATION Microcode monitor The present invention relates to monitors for assessing the performance of data processors.

The present invention particularly relates to monitors for assessing the efficiency of computer microcode instruction sequences.

Data processors employ microcode memories to store sequences of micro instructions to perform allotted tasks. The micro instructions are called up in turn to perform a microcode instruction sequence. Thus, to cause the processor to execute a complex series of operations, it is merely necessary to cause the processor to access the first micro instruction in the sequence of micro instructions which will make the processor perform the desired operation.

Each micro instruction indicates the address in the microcode memory where the next microcode instruction is to be found. Other abort addresses [otherwise known as jump addresses] are stored with each micro instruction and, dependently upon the condition of flag or abort lines in the processor, another next micro instruction address may be selected. The abort signals may indicate positive negative or zero register or accumulator conditions, imposed interrupts and the like.

In assessing the utility of a particular microcode sequence some basis of comparison must be provided against other microcode sequences. Each microcode memory contains a large number of different sequences. A microcode monitor is required to distinguish one sequence from another and to record pertinent aspects concerning the utilisation of the individual sequences.

It has been known to employ a micro processor to analyse microcode utilisation of a monitored processor. If the monitored processor runs very slowly a micro processor may be so used. Because the micro processor itself employs micro instruction sequences to perform operations which may be many dozens of clock cycles long, the micro processor is required to run at many times the clock rate of the monitored processor. This severely limits the capacity of one processor to monitor the microcode operations of another.

It is desirable therefore to provide means whereby a processor may have its micro instruction sequences monitored without a limit being imposed by the speed of a monitoring micro processor.

The present invention consists in a monitor for monitoring operation of a data processor employing microcode instruction sequences, said monitor comprising; a plurality of channels each comprising an elapsed time memory; a decoder operative to monitor microcode addresses in the processor, operative in response to receipt of a first predetermined microcode address to provide a channel start command to a selected one of said channels and operative in response to a second predetermined microcode address to provide a channel stop command to the selected channel; a clock circuit operative to provide output indicative of passing time; and elapsed time adding means coupled to monitor said clock and to monitor said decoder for said channel start command and operative to add to said elapsed time memory in the selected channel the amount of time intervening between said channel start command and said channel stop command.

The preferred embodiment of the present invention is also operative to select and increment a counter memory on each instance of a micro instruction sequence being used. The preferred embodiment is also operative not to increment the elapsed time memory or the counter memory if a channel start command has not been followed by a stop command.

Whenever the decoder is not in receipt of a predetermined microcode address it provides a null output which allows a supervising controller in the form of a micro processor to gain access to the counter memory and elapsed time memory for a selectable channel for accumulated stored information to be obtain even while a test is still running and transferred to an external analysing processor.

In the preferred embodiment a particular channel may be selected by more than one microcode address. Certain microcode addresses are indicative of a single cycle operation in the monitored processor in which instance the monitor responds by incrementing the counter memory even although a channel stop signal has not been detected.

The monitor comprises a random access memory look up table which is loaded by the supervising controller prior to operation, addresses in the elapsed time memory and in the counter memory corresponding to each microcode sequence start and finish address.

The microcode addresses are provided as addressing input to the random access memory look up table which in turn provides the addressing output to the counter and elapsed time memories.

The random access memory look up table, as well as storing addresses for the elapsed time memory and for the counter memory, also stores associated flags and conditions which are combined with the abort signals from the minitored processor to initiative and terminate entire testing operations by generation of enabling and disabiing control signals to the logging portion of the monitor.

The present invention is further explained, by way of an example, by the following description taken in conjunction with the appended drawings in which: FIG. 1 shows a block diagram of the data processing environment wherein the present invention is employed: FIG.2 shows a block diagram of the microcode monitor according to the present invention; FIG.3 shows a block diagram of the decoder portion of the microcode monitor shown in FIG.2; and FIG.4 shows a block diagram of the logger portion of the microcode monitor shown in FIG .2.

FIG. 1 shows a schematic block diagram of the environment wherein the present invention is used.

In a data processing system under test 10 a monitored processor 12 executes any selected one from among a sequence of micro-routines stored in a microcode memory 14. The monitored processor 12 provides a micro instruction address bus 16 as an addressing input to the microcode memory 14. In turn the microcode memory 14 provides output on a micro instruction bus 18 coupled back to control the monitored processor 12. The micro instruction bus 18 not only provides micro instructions but also next-address information to indicate to the monitored processor 12 at what address in the microcode memory 14 the next micro instruction is to be found.

The monitored processor 12 generates abort signals [externalised on an abort signal bus 20] indicative of the states of various registers within the monitored processor 12.

For example, the abort signals 20 may include indication whether the contents of a particular register are negative positive or zero. The abort signals 20 may include flag signals indicative of some event having taken place and may include interrupt signals used in the operations of the data processing system under test 10. In general terms the abort signals 20 are used by the monitored processor to select which out of a plurality of next micro instruction addresses provided on the micro instruction bus 18 is to be used as the address of the next micro instruction. Thus in general terms the abort signals 20 control the branching and jumping within each of a plurality of microcode sequences stored in the microcode memory 14.

While the abort signals 20 are generally used for the above purpose, so far as the present invention is concerned the abort signals 20 can include any other signals within the data processing system under test 10 which may be considered relevant to the testing of the system 10. For example, it may not be desired to commence a test until after some peripheral device has reset a flag. While the flag signal would not normally be used by the monitored processor 12 to control branching and jumping within microcode sequences, as will later become clear, the present invention can utilise such a flag signal. This last example is quoted merely by way of demonstration and is not intended to represent a limiting case.

The micro instruction address bus 16 and the abort signal bus 20 are coupled out of the data processing system 10 into a hardware monitor 22. The hardware monitor 22 is the subject of the present invention. The monitored processor 12 also provides a clock signal on a clock line 24 used to control movements of data within the hardware monitor 22.

The hardware monitor 22 monitors the processes within the system 10 and accumulates results within itself. An analysing processor 26 periodically interrogates the hardware monitor 22 which provides test results via a test result coupling 28 to the analysing processor 26. The analysing processor 26 can analyse the test results and provide statistical information concerning the utilisation of the stored microcode sequences in the microcode memory 14. The analysing processor 26 and the data processing system 10 are not of themselves part of the present invention.

The microcode memory 14 stores a large number of different microcode sequences. The monitored processor 12 employs different microcode sequences and different sequences of microcode sequences at various times to achieve the purpose of the data processing system 10. In order to execute a microcode sequence the start address of a particular sequence is provided on the micro instruction address bus 16 so that the next micro instruction to be obeyed is in turn provided on the micro instruction bus 18. Each micro instruction sequence is thus provided with a micro instruction start address.

A selected microcode sequence will in general consist in a number of different possible microcode addresses presented in turn on the micro instruction address bus 16. The microcode sequence will be terminated by an exit from the sequence when a particular terminating or stop address is presented on the micro instruction address bus 16.

Some micro instructions executed by the monitored processor 12 are single-cycle micro instructions consisting in an operation taking only one clock cycle. In general terms however a selected microcode sequence may range in time anywhere from one or two clock cycles up to many tens of clock cycles where complicated shifting and processing operations are required.

The monitor 22 has, as its purpose, the making of a record of the total amount of time spent executing a selected microcode sequence. The monitor 22 also keeps a record of how many times a selected microcode sequence has been used. During a test the data processing system 10 is caused to perform either real-life operations or a set of simulated real-life operations. The monitor 22 is capable of recording the elapsed time and number of instances of use of a very large number of different microcode sequences at the same time. At the end of a test period the test results are stored and compared with test results for different microcode sequences used in the microcode memory 14.In general terms, if a modified microcode sequence achieving the same purpose as another microcode sequence takes up less total time to run than that other microcode sequence, then the microcode sequence which takes up less time in the general running of the data processing system 10 is considered better than the microcode sequence which takes up more time.

Likewise, the running count of the number of times a particular microcode sequence was called up is a reflection upon the manner of operation of the software operating system used in the data processing system 10. The monitor 22 is thus capable of providing information concerning not only the efficiency of the microcode sequences stored in the microcode memory 14 but also concerning the manner of access to the monitored processor 12 of the operating system used in the data processing system 10.

FIG.2 shows a block diagram of the hardware monitor 22 shown in FIG. 1.

The hardware monitor 22 comprises a decoder 30 and a logger 32. A controller 34 provides controlling input both to the decoder 30 and to the logger 32. The controller 34 comprises a conventional micro processor programmed to perform the tasks hereinafter ascribed to it and providing some or all of its data and address buses as a control bus 36 provided both to the decoder 30 and to the logger 32.

Bi-directional coupling 38 joins the controller 34 to a communication port 40 which drives signals onto the test result coupling 28 so that the analysing processor 26 may request the controller 34 to provide test results and the controller 34 can communicate the test results back to the analysing processor 26.

The communication port 40 can be any kind known in the art. For preference, in this embodiment of the invention the communication port is an RS232 serial port. It is to be understood that the communication port might equally comprise direct couplings, modems, fibre optic devices and the like. It is not important to the present invention what manner of communication port 40 is employed save that it be capable of performing the functions ascribed to it.

The decoder 30 is in receipt of the micro instruction address bus 16, the abort signal bus 20 and the clock line 24. The decoder 30 employs the micro instruction address bus 16 and the abort signal bus 20 to select test stop and start conditions and particular elapsed time memory locations and counter memory locations within the logger 22. The controller 34 pre-loads the decoder 30 with information and interrogates the logger 32 to recover information which in turn is passed to the analysing processor 26 through the communication port 40.

Transfer of results from the logger 32 to the analysing processor 26 can take place not only at the end of a test operation but also during the course of that operation.

A decoder output bus 42 provides controlling input to the logger 32.

FIG.3 shows a schematic block diagram of the decoder 30 of FIG.2.

The micro instruction address bus 16 is firstly coupled as input to a RAM address latch 44 clocked by the clock line 24 of the monitored processor 12. Output 46 from the RAM address latch 44 is a direct representation of the micro instruction address last provided on the micro instruction address bus 16 and is coupled as an addressing input to a dual-port random access memory lookup table 48. For each addressed location in the random access memory lookup table 48 the random access memory 48 provides a pre-stored logger address word on a random access memory address output bus 50.

Each storage location in the random access memory lookup table 48 not only stores the logger address to be provided on the random access memory address output bus 50 but also stores a control word which is provided as output on a random access memory control output bus 52.

Thus as each memory location in the random access memory lookup table 48 is accessed by the stored contents of the RAM address latch 44 so a logger address and a control word are provided as output.

The abort signal bus 20 is coupled as input to an abort latch 54 also clocked by the clock line 24. The output of the abort latch 54 is a direct representation of the signals on the abort signal bus 20. The output 56 of the abort latch 54 is coupled as input firstly to priority logic 58 and secondly as input to a logic array 60. The random access memory control output bus 52 is coupled as a further input to the logic array 60. The micro instruction address bus 16 is provided as yet another input to the logic array 60.

Test control logic 62 coupled to receive instructions from the controller 34 [this coupling not being shown in FIG.3] is responsive to the contents and condition of the RAM address latch 44, and of the abort latch 54, to control whether or not the RAM address latch 44 or the abort latch 54 functions. The controller 34 is thus able directly to influence which signals are allowed entry to the decoder 30.

The random access memory address output bus 50 is coupled as input to a counter/timer latch 64. The counter/timer latch 64 is also clocked by the clock line 24 frqm the monitored processor 12.

The random access memory address output bus 50 is also coupled as input to an abort address latch 66 also clocked by the clock line 24. The counter/timer latch 64 accepts and provides as output that logger address which is to be accessed in the event of an abort condition not being fulfilled. The abort address latch 66 accepts stores and provides as output that portion of the signal on the random access memory address output bus 50 indicative of the logger address to be accessed in the event of an abort condition signalled on the output 56 of the abort latch 54 being fulfilled.

The control bus 36 from the controller 34, consisting in the combined address and data bus of the micro processor in the controller 34, is coupled firstly to the dual-port random access memory lookup table 48 and secondly to a null cycle latch 68. The controller 34 stores in the null cycle latch 68 a null-address word Before commencement of a testing period, the controller 34 uses the control bus 36 to load the dual-port random access memory lookup table 48. The controller 34 may already have stored within itself the contents of the dual-port random access memory lookup table 48. Equally the controller 34 may be instructed by the analysing processor [or indeed any other external source] as to what the dual-port random access memory lookup table contents should be.

If a particular micro instruction address received on the micro instruction address bus 16 is the start-address of a microcode sequence to be monitored, a genuine logger address is stored for later provision on the random access memory address output bus 50 together with a control word for later provision on the random access memory control output bus 52. The same action is taken if the micro instruction address provided on the micro instruction address bus 16 designates a final or stop address in a microcode sequence or represents the address of a single-cycle micro instruction.

If the micro instruction address provided on the micro instruction address bus 16 represents none of these, but is merely indicative of a micro instruction which appears in the middle of a microcode sequence to be monitored, the controller 34 stores the null-character [otherwise stored in the null cycle latch 68] in that location.

Starting and stopping of a particular testing operation or epoch is controlled by the logic array 60. It may be desired to start a testing operation on a particular microcode sequence only when a particular micro instruction address with particular abort conditions is encountered. The control word provided on the random access memory control output bus 52 is combined in the logic array with the output 56 from the abort latch 54 and the contents of the micro instruction address bus 16 to provide control signals 42a to the registers memories and arithmetic units hereinafter described in the logger 32 to enable or disable their operation.

The output of the null cycle latch 68, the counter/timer latch 64 and the abort address latch 66 are all coupled as input to the priority logic 58. The priority logic 58 monitors all of its inputs and selectively provides address 42b and control signals 42c to the logger 32.

The priority logic 58 also controls ALU and register logic 70 which in turn also provides output 42d used to provide enabling signals to the various memories and arithmetic logic units hereinafter described in the logger 32.

The various outputs 42a,42b,42c and 42d together represent the decoder output bus 42 shown in FIG.2.

FIG.4 shows a schematic block diagram of the logger 32 of FIG.2.

The address output 42b from the priority logic 58 is coupled as an address input to a counter memory 72 and a timer memory 74.

Both the counter memory 72 and the timer memory 74 comprise 256 separa e storage locations. When an address is provided each 72,74 accesses its respective address storage location. The pair of access storage locations is designated a "channel" and each channel can be used to monitor a separate microcode sequence. The decoder 30 and the logger 32 are therefore able together to accumulate and store information concerning the performance of up to 256 different microcode sequences operating at the same time.

The counter memory 72 counts the number of occasions on which a microcode sequence has been used. The counter memory 72 provides its output on a counter memory output bus 76 which is provided as input to a counter output register 78 and to a first arithmetic logic unit 80. The first arithmetic logic unit 80 has hard wiring 82 causing it to increment the binary number presented on the counter memory output bus 76 by one. The first arithmetic logic unit 80 provides its incremented output on a first arithmetic logic unit output bus 84 which is coupled as a data input to the counter memory 72. Thus, whenever the priority logic 58 receives from the dual-port random access memory lookup table 48 an address which is not the null address in the null cycle latch 68, the priority logic address output 42b addresses the appropriate storage location in the counter memory 72, and the ALU and register logic 70 and the priority logic 58 provide respective outputs 42c and 42d to strobe the first arithmetic logic unit 80 and the counter memory 72 to cause the presently stored contents of the address location to be incremented by one and then stored back in the same location.

The timer memory 74 stores the total elapsed time that each microcode sequence which is to be monitored has used during the course of a testing operation. A real time clock generator circuit 86 provides, on a real time clock bus 88, a running tally of passing time. The real time clock bus 88 is provided as a first input to a second arithmetic logic unit 90. The timer memory 74 provides a representation of its stored and address contents on a timer memory output bus 92 which is coupled as a second input to the second arithmetic logic unit 90. A second arithmetic logic unit output bus 94 couples output from the second arithmetic logic unit 90 as data input to the timer memory 74.The second arithmetic logic unit 90 is pre-programmed to co-operate with signals 42c, 42d via the priority logic 58 to store, in each memory location addressed in the timer memory 74, the total elapsed time that a particular monitored microcode sequence has taken up. When the priority logic address output 42b addresses a particular location in the timer memory 74 as a start address [as signalled via 42a,42c, and 42d ] , the second arithmetic logic unit 90 acquires and retains the current time represented by the signal on the real time clock bus 88.

When the storage location in the timer memory 74 is again addressed with a microcode sequence stop address [as signalled by 42a,42c,42d], the second arithmetic logic unit 90 acquires the recovered stored elapsed time presented on the timer memory output bus 92 and subtracts from it the previously acquired signal which was presented on the real time clock output bus 88 at the start of the microcode sequence. The second arithmetic logic unit 90 then adds to the result the signal on the real time clock output bus 88 at the instant when the microcode sequence stop address was received. In this way the stored elapsed time for the particular monitored microcode sequence has added to it the elapsed time between receipt of the microcode sequence start address and the microcode sequence stop address.This result is presented on the second arithmetic logic unit output bus 94 and is stored in the time memory 74 in place of the previously-stored elapsed time.

A problem arises if two start addresses are received in sequence, two stop addresses are received in sequence, or if a stop address is not received within a predetermined number of clock cycles on the clock line 24 after receipt of a start address. The timer memory 74 stores a start or stop bit [ FIG.1 or FIG.O ] together with the current elapsed time. If a stop address follows a stop address or a start address follows a start address or more than the predetermined number of clock cycles on the clock line 24 have elapsed, the second arithmetic logic unit 90 is inhibited from performing its arithmetic operations. The timer memory 74 thus retains its current elapsed time. As an option the timer memory 74 may also store an error bit which is set if any of the above described error conditions ensues.

Some channel addresses received from the dual-port random access memory lookup table 48 are flagged [on 52] as single-cycle micro instructions to be executed by the monitored processor 12. In such an instance it would be inappropriate for the timer memory 74 to be incremented. Accordingly, when the logic array 60 provides output indicative of an address [42b] being a single-cycle address, the second arithmetic logic unit 90 is inhibited from adding and subtracting real time clock 86 signals 88. Also for such single-cycle micro instructions there is no error flag in the timer memory 74 if the same address is received twice. Likewise since there is no start address and no stop address no error can be flagged if a stop address does not follow a start address in due time.

The real time clock bus 88 is coupled as input to a clock output register 96. The timer memory output bus 92 is coupled as an input to a timer output register 98.

The dual-port random access memory lookup table 48 stores the null character otherwise contained in the null cycle latch 68 not only for those micro instruction addresses which lie between a start address and a stop address for a particular microcode sequence to be monitored, but also for all microcode addresses received from the micro instruction address bus 16 for all those microcode sequences which are not to be monitored. Thus, unless the location addressed in the dual-port random access memory lookup table 48 is a monitored microcode sequence start address, a monitored microcode sequence stop address, or a monitored single-cycle micro instruction, the null character is stored.Whenever the priority logic 58 detects the null character from the counter/timer latch 64 it provides a signal on a flag line 100 to the controller 34 indicative of the fact that no arithmetic or storage operation is currently being executed by the logger 32.

All elements in the decoder 30 and the logger 32 are clocked and strobed in synchronism with the clock signal provided on the clock line 24 from the monitored processor 12. The only exception to this rule occurs when the controller 34 loads the dual-port random access memory lookup table 48 and loads the null cycle latch 68. Thus all elements work in synchronism with the monitored processor 12 and there is no speed limitation caused by the presence of the micro processor in the controller 34.

The counter output register 78 stores the last presented output from the counter memory 72. The clock output register 96 stores the current output from the real time clock 86. The timer output register 98 stores the last presented output from the timer memory 74. The controller 34 is coupled to the counter output register 78, the clock output register 96 and the timer output register 98 to cause any selected one of them to present its stored output on the control bus 36 otherwise shown in FIG.2. When the priority logic 58 provides the signal on the flag line 100 indicative of the null character being received, the controller 34 then has the option of reading the intermediate test results for any selected one of the 256 channels. The control bus 36 from the controller 34 is coupled as a further input to priority logic 58.The controller 34 provides indication of the address signal 42b to be provided to the counter memory 72 and to the time memory 74. The logic array 60, ALU and register logic 70 and the priority logic 58 all co-operate to set the counter memory 72 and the timer memory 74 into reading mode. The contents of the desired memory location are thus strobed on the next instance of presentation of the clock signal on the clock line 24 into their respective output registers 78,98. The controller 34 can then selectively strobe and so activate the selected one from among the counter output register 78, the clock output register 96, or the timer output register 98 to recover the desired stored data. The controller 34 may then, if required, transfer that data via the communication port 40 to the analysing processor 26.

The controller 34 runs on its own independent clock and is not subject to direct timing control from the clock line 24 except in as much as operations by the controller 34 must wait until events controlled by the clock line 24 are completed. Those registers 78 96 98 strobed by the controller 34 and the loading of the random access memory lookup table 98 are controlled by the independent controller clock. Likewise, the communication port 40 may contain internal clock sources for control of data transmission and will co-operate with the independent clock of the controller 34 and an independent clock in the analysing processor 26 to achieve its data transfer function.

Those skilled in the art will be aware that gating of the above mentioned independent clock signals with the clock signal from the monitored processor 12 provided on the clock line 24 to achieve synchronism and freedom from races can be employed.

As soon as the null character ceases to be received by the priority logic 58 from the dual-port random access memory lookup table 48, the whole system reverts to the normal data-acquiring mode of operation as previously described.

At commencement of a testing operation the controller 34 resets the timer memory 74 and the counter memory 72 such that the contents of each location are zero. The real time clock 86 is set either to zero time or to the correct time of day.

In the dual-port random access memory lookup table each channel or pair of locations in the counter memory 72 and the timer memory 74 may have more than one micro instruction start address and stop address. The only constraint is that no micro instruction start address can be used for more than one channel in the logger 32.

As well as the functions already described the logic array 60 is operative, dependently upon signals presented on the random access memory control output bus 52, to stop the real time clock 86 from incrementing. The logic array 60 is also operative when required to cause the logger 32 to be incremented not by the clock signal from the clock line 24 of the monitored processor 12 but from a single step clock source [not shown in the Figures] for test purposes. The logger 32 also provides a monitoring function [not shown in the Figures] whereby, if the real time clock 86 overflows, the overflow condition is signalled by the real time clock 86 to the controller 34.

The controller 34 then knows that the values stored in the timer memory 74 will themselves begin to overflow. Likewise, if the contents of any location in the counter memory 72 overflows, indication is also provided to the controller 34.

The logic array 60 may cause the logger 32 to start and stop logging on numerous occasions during a testing epoch. For example, if the monitored processor 12 provides a line on the abort signal bus 20 indicative of a programme currently being executed, the logic array 60 can respond by causing the logger 32 only to perform logging operations when the abort latch 54 output 56 provides indication that the programme is actually running. As another alternative, the monitored processor 12 can provide indication through the abort latch 54 when a particular selected programme from among a plurality of possible programmes is being run. The logic array 60 can then respond by enabling the logger 32 to function only on those occasions when the selected programme is being run. In this way the monitor 22 can operate as a very precise analysing tool.

The random access memory control output bus 52 is also used to start and stop a logging operation. A particular binary digit, presented [when recalled ] on the random access memory control output bus 52 and initially stored in the dual-port random access memory lookup table 48 by the controller 34, controls the logic array 60 to start and stop logging operations. The logic array 60 inhibits the logger 32 until such time as a flagged "start testing micro instruction address is received on the micro instruction address bus 16. The logic array 60 then maintains the logger 32 in operation until it receives a "stop testing" flag via the random access memory control output bus 52 when a particular pre-selected micro instruction address is received on the micro instruction address bus 16. In this way, during a testing epoch, the logic array 60 can be used via the dual-port random access memory lookup table 48 loaded by the controller 34 to start and stop the logger 32 on numerous occasions. This operation can be used to focus the activity of the monitor 22 onto specific micro instruction sequences.

In the present invention the logic array 60 can be configured in any desired manner to start and stop the logger 32 upon receipt of any particular signal from the dual-port random access memory lookup table 48 via the random access memory control output bus 52, via some or all of the binary digits in the addresses received from the micro instruction address bus 16, and any conditions which may be signalled to the monitor 22 via the abort signal bus 20 onto the abort latch output 56.

One particularly advantageous implementation of the logic array 60 includes providing a dual-port random access memory [similar to though not necessarily the same size as the lookup table 48] which is also loaded by the controller 34 at the start of overall operations.

Some or all of the bit lines in the micro instruction address bus 16, the bit lines from the abort latch 54 and the bit lines from the random access memory control output bus 52 [in whole or in part] are employed as an address input to the random access memory used in the logic array 60 and the data output provided as control signals 42a. This particular embodiment of the logic array 60 allows for extreme flexibility of use and allows the monitor 22 to be readily transferred from monitored processor 12 to another of the same type or from one type of monitored processor 12 to another. Alternatively, where the monitor 22 is to be used with one particular kind of monitored processor 12 the logic array 60 can be implemented in the form of a programmed READ-ONLY memory or in the form of a programmed logic array.

The logic array 60 is operative to cause the logger 32 to commence logging on the next received sub routine start address. For example, it may be desired to determine the exit-usage of a sub routine. The sub routine is then flagged with its final address providing indication on the random access memory control output bus 52 that logging is to commence for the next monitored microcode sequence and to terminate at the end of that sequence unless an instruction to the contrary is provided. The logic array 60 then commands the logger 32 to log the next microcode sequence which is to be monitored and return the logger 32 to an inert state until the logic array 60 is once again caused to reactivate the logger 32.In this way the monitor 22 can be made an even more precise tool to probe the operations of microcode sequences by showing statistically the exit routines from particular sub routines.

The stop address for a particular sub routine need not be the exit address from the sub routine. For example, it may be that, in a particular microcode sequence to be monitored, a stop address is selected which is not the ter minating or exit address for the routine in question. The routine can continue on past that address and/or can jump back into other points in the routine. By setting the microcode sequence stop address at a particular location within a mocrocode sequence it is possible to analyse the efficiency of the code up to that point. The only restraint upon this operation is that, in the execution of the microcode se quence, each instance of provision of the stop address is preceded by provision of a start address. Likewise, the start address need not be the first address in the microcode sequence.By placing the start address and stop address in a microcode sequence where there is no exit there-between, it is possible to provide a detailed analysis of the efficiency of portions of microcode within a larger micro code sequence. This facility allows the monitor 22 to provide an even more precise probe into the efficiency of operation of microcode sequences.

Returning briefly to FIG.1, it is to be appreciated that whereas a separate analysing processor 26 is shown as a part of the overall system wherein the hardware monitor 22 is used, the analysing processor 26 could in fact be the data processing system 10 which is under test. The hardware monitor 22 could equally be made a permanent resident part of the data processing system 10.

The disclosure of the present invention has shown a counter memory 72 and a timer memory 74 each having 256 separate locations or channels. The counter memory 72 need not have the same number of addressable storage locations as the timer memory 74, there being no necessity to record elapsed time for single clock cycle micro instructions.

It is to be appreciated that a monitor 22 can be constructed according to the present invention with as few or as many channels as is required. In the present disclosure the micro instruction address bus 16 is chosen for preference to be sixteen bits wide. The micro instruction address bus 16 may of course be any required width and its width depends upon the nature of the monitored processor 12. In the present disclosure the dual-port random access memory lookup table 48 is ad dressed by the full sixteen bits of the micro instruction address bus 16. It is to be appreci ated that the dual-port random access memory lookup table 48 may be smaller than the maximum number of addressable locations by the micro instruction address bus 16 and may have less than the full number of bit lines on the micro instruction address bus 16 provided as its address input.

Claims (13)

1. A monitor for monitoring operation of a data processor employing microcode instruc tion sequences, said monitor comprising; a plurality of channels each comprising an elapsed time memory; a decoder operative to monitor microcode addresses in the processor, operative in response to receipt of a first predetermined microcode address to provide a channel start command to a selected one of said channels and operative in response to a second predetermined microcode address to provide a channel stop command to the selected channel; a clock circuit operative to provide output indicative of passing time; and elapsed time adding means coupled to monitor said clock and to monitor said decoder for said channel start command and operative to add to said elapsed time memory in the selected channel the amount of time intervening between said channel start command and said channel stop command.

2. A monitor according to Claim 1 wherein each channel further comprises a counter memory; and wherein said monitor comprises counter adding means coupled to receive said channel start signal and said channel stop signal and operative to increment the contents of the counter memory in the selected channel each time a microcode instruction sequence is executed by the data processor.

3. A monitor according to Claim 2 wherein said counter adding means is inhibited from incrementing the counter memory in the selected channel if a channel start command for the selected channel is not followed by a channel stop command.

4. A monitor according to Claim 3 wherein, in the event of said counter adding means being inhibited, output is provided indicative of a channel start command not having been followed by a channel stop command.

5. A monitor according to any of the preceding Claims wherein said decoder is operative, when not in receipt of a predetermined microcode address, to provide a null output signal; said monitor comprising means operative to detect said null signal, and, in response thereto, to provide as output, the contents of the elapsed time memory in a selected channel.

6. A monitor according to Claim 5 when dependent upon Claim 2 wherein said means operative to detect said null signal is also operative to provide as output the contents of the counter memory in the selected channel.

7. A monitor according to any of the preceding Claims wherein said decoder is operative to provide said channel start command in response to receipt of any one of a plurality of microcode addresses.

8. A monitor according to Claim 7 wherein said decoder is operative to provide said channel stop command in response to any one of a plurality of microcode addresses.

9. A monitor according to Claim 2, or according to any of Claims 3 to 7 when dependent upon Claim 2, wherein said decoder is operative to detect a single-cycle instruction microcode and to provide output indicative thereof; and wherein said counter adding means is operative in response to said output indicative of a single-cycle microcode to increment the counter memory in the selected channel regardlessly of whether or not a channel stop command has been received from said decoder.

10. A monitor according to Claim 9 wherein said elapsed time adding means is inhibited from adding elapsed time to the elapsed time memory in the selected channel in the event of receipt from said decoder of said output indicative of a single-cycle micro instruction.

11. A monitor according to any of the preceding Claims coupled to receive abort lines from the data processor and operative to commence or terminate a testing operation in response to selection of a predetermined channel together with a predetermined abort condition.

12. A monitor according to Claim 11 operative to commence or terminate a testing operation on the next microcode instruction after selection of the predetermined channel with a predetermined abort condition.

13. A monitor substantially as described with reference to the appended drawings.